2001 Integrated Device Technology, Inc.

DSC-4512/1

APRIL 2001

3.3 VOLT CMOS SuperSync FIFOTM
32,768 X 18
65,536 X 18

IDT72V275
IDT72V285

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

.EATURES:

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Choose among the following memory organizations:

IDT72V275

32,768 x 18

IDT72V285

65,536 x 18

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·

Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs

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·

10ns read/write cycle time (6.5ns access time)

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Fixed, low first word data latency time

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Auto power down minimizes standby power consumption

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Master Reset clears entire FIFO

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Partial Reset clears data, but retains programmable
settings

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Retransmit operation with fixed, low first word data
latency time

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Empty, Full and Half-Full flags signal FIFO status

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Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets

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Program partial flags by either serial or parallel means

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·

Select IDT Standard timing (using

EF and FF

FF flags) or First Word

Fall Through timing (using

OR and IR

IR flags)

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Output enable puts data outputs into high impedance state

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Easily expandable in depth and width

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Independent Read and Write clocks (permit reading and writing
simultaneously)

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Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin

Slim Thin Quad Flat Pack (STQFP)

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High-performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

DESCRIPTION:

The IDT72V275/72V285 are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:

The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs, RCLK
or WCLK, is running at the higher frequency.

The period required by the retransmit operation is now fixed and short.

The first word data latency period, from the time the first word is written to
an empty FIFO to the time it can be read, is now fixed and short. (The
variable clock cycle counting delay associated with the latency period
found on previous SuperSync devices has been eliminated on this
SuperSync family.)

SuperSync FIFOs are particularly appropriate for network, video, telecom-
munications, data communications and other applications that need to buffer
large amounts of data.

.UNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

32,768 x 18
65,536 x 18

FLAG

LOGIC

PAF

PAE

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET

LOGIC

WEN

WCLK

-D

MRS

REN

RCLK

-Q

OFFSET REGISTER

PRS

FWFT/SI

SEN

4512 drw 01

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

PIN CON.IGURATIONS

TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)

TOP VIEW

DESCRIPTION (Continued)

PIN 1

WEN

SEN

(1)

GND

D17

D16

D15

D14

D13

D12

D11

D10

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Q17

Q16

GND

Q15

Q14

Q13

Q12

Q11

GND

Q10

GND

WCLK

PRS

MRS

FWFT/SI

GND

PAF

PAE

RCLK

REN

GND

4512 drw 02

The input port is controlled by a Write Clock (WCLK) input and a Write Enable

(

WEN) input. Data is written into the FIFO on every rising edge of WCLK when

WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (

REN) input. Data is read from the FIFO on every rising

edge of RCLK when

REN is asserted. An Output Enable (OE) input is provided

for three-state control of the outputs.

The frequencies of both the RCLK and the WCLK signals may vary from 0

to f

MAX

with complete independence. There are no restrictions on the frequency

of the one clock input with respect to the other.

There are two possible timing modes of operation with these devices: IDT

Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not appear

on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating

REN and enabling a rising RCLK edge,

will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly

to the data output lines after three transitions of the RCLK signal. A

REN does

not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on

REN for access. The state of

the FWFT/SI input during Master Reset determines the timing mode in use.

For applications requiring more data storage capacity than a single FIFO

can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.

NOTE:
1. DC = Don't Care. Must be tied to GND or V

, cannot be left open.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

DESCRIPTION (Continued)

Figure 1. Block Diagram of Single 32,768 x 18 and 65,536 x 18 Synchronous FIFO

DATA OUT (Q

- Q

)

DATA IN (D

- D

)

MASTER RESET (

MRS

)

READ CLOCK (RCLK)

READ ENABLE (

REN

)

OUTPUT ENABLE (

)

EMPTY FLAG/OUTPUT READY (

)

PROGRAMMABLE ALMOST-EMPTY (

PAE

)

WRITE CLOCK (WCLK)

WRITE ENABLE (

WEN

)

LOAD (

)

FULL FLAG/INPUT READY (

)

PROGRAMMABLE ALMOST-FULL (

PAF

)

IDT

72V275
72V285

PARTIAL RESET (

PRS

)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

RETRANSMIT (

)

4512 drw 03

HALF-FULL FLAG (

)

SERIAL ENABLE(

SEN

)

These FIFOs have five flag pins,

EF/OR (Empty Flag or Output Ready),

FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and

PAF (Programmable Almost-Full flag). The EF and

FF functions are selected in IDT Standard mode. The IR and OR functions
are selected in FWFT mode.

HF, PAE and PAF are always available for

use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point

in memory. (See Table 1 and Table 2.) Programmable offsets determine the
flag switching threshold and can be loaded by two methods: parallel or serial.
Two default offset settings are also provided, so that

PAE can be set to switch

at 127 or 1,023 locations from the empty boundary and the

PAF threshold can

be set at 127 or 1,023 locations from the full boundary. These choices are made
with the

LD pin during Master Reset

For serial programming,

SEN together with LD on each rising edge of

WCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming,

WEN together with LD on each rising edge of WCLK, are used

to load the offset registers via D

REN together with LD on each rising edge

of RCLK can be used to read the offsets in parallel from Q

regardless of whether

serial or parallel offset loading has been selected.

During Master Reset (

MRS) the following events occur: The read and write

pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The

LD pin selects either a partial flag default

setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.

The Partial Reset (

PRS) also sets the read and write pointers to the first

location of the memory. However, the timing mode, partial flag programming
method, and default or programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect.

PRS is useful for resetting a device in mid-operation, when

reprogramming partial flags would be undesirable.

The Retransmit function allows data to be reread from the FIFO more than

once. A LOW on the

RT input during a rising RCLK edge initiates a retransmit

operation by setting the read pointer to the first location of the memory array.

If, at any time, the FIFO is not actively performing an operation, the chip will

automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.

The IDT72V275/72V285 are fabricated using IDT's high speed submicron

CMOS technology.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

PIN DESCRIPTION

Symbol

Name

I/O

Description

Data Inputs

Data inputs for a 18-bit bus.

MRS

Master Reset

MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.

PRS

Partial Reset

PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.

Retransmit

RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the

EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb

the write pointer, programming method, existing timing mode or programmable flag
settings.

RT is useful to reread data from the first physical location of the FIFO.

FWFT/SI

First Word Fall

During Master Reset, selects First Word Fall Through or IDT Standard mode.

Through/Serial In

After Master Reset, this pin functions as a serial input for loading offset registers

WCLK

Write Clock

When enabled by

WEN, the rising edge of WCLK writes data into the FIFO and

offsets into the programmable registers for parallel programming, and when
enabled by

SEN, the rising edge of WCLK writes one bit of data into the

programmable register for serial programming.

WEN

Write Enable

WEN enables WCLK for writing data into the FIFO memory and offset registers.

RCLK

Read Clock

When enabled by

REN, the rising edge of RCLK reads data from the FIFO

memory and offsets from the programmable registers.

REN

Read Enable

REN enables RCLK for reading data from the FIFO memory and offset registers.

Output Enable

OE controls the output impedance of Q

SEN

Serial Enable

SEN enables serial loading of programmable flag offsets.

Load

During Master Reset,

LD selects one of two partial flag default offsets (127 or 1,023

and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers

Don't Care

This pin must be tied to either V

or GND and must not toggle after Master

Reset.

FF/IR

Full Flag/

In the IDT Standard mode, the

FF function is selected. FF indicates whether or

Input Ready

not the FIFO memory is full. In the FWFT mode, the

IR function is selected. IR

indicates whether or not there is space available for writing to the FIFO memory.

EF/OR

Empty Flag/

In the IDT Standard mode, the

EF function is selected. EF indicates whether or

Output Ready

not the FIFO memory is empty. In FWFT mode, the

OR function is selected.

OR indicates whether or not there is valid data available at the outputs.

PAF

Programmable

PAF goes LOW if the number of words in the FIFO memory is more than

Almost-Full Flag

total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.

PAE

Programmable

PAE goes LOW if the number of words in the FIFO memory is less than offset n,

Almost-Empty Flag

which is stored in the Empty Offset register. There are two possible default values
for n: 127 or 1,023. Other values for n can be programmed into the device.

Half-Full Flag

HF indicates whether the FIFO memory is more or less than half-full.

Data Outputs

Data outputs for an 18-bit bus.

Power

+3.3 Volt power supply pins.

GND

Ground

Ground pins.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

Symbol

Rating

Commercial

Unit

TERM

Terminal Voltage

0.5 to +4.6

with respect to GND

STG

Storage

55 to +125

° C

Temperature

OUT

DC Output Current

50 to +50

NOTES:
1. With output deselected, (

2. Characterized values, not currently tested.

DC ELECTRICAL CHARACTERISTICS

(Commercial: V

= 3.3V ± 0.3V, T

= 0

C to +70

C; Industrial: V

CC =

3.3V

0.3V, TA = -40

C to +85

Symbol

Parameter

(1)

Conditions

Max.

Unit

(2)

Input

= 0V

Capacitance

OUT

(1,2)

Output

OUT

= 0V

Capacitance

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage(Com'l & Ind'l)

3.0

3.3

3.6

GND

Supply Voltage(Com'l & Ind'l)

Input High Voltage
(Com'l & Ind'l)

2.0

+ 0.5

(1)

Input Low Voltage
(Com'l & Ind'l)

0.8

Operating Temperature

Commercial

Operating Temperature

-40

Industrial

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

IDT72V275L
IDT72V285L

Com''l & Ind'l

(1)

CLK

= 10, 15, 20 ns

Symbol

Parameter

Min.

Max.

Unit

(2)

Input Leakage Current

µ A

(3)

Output Leakage Current

µA

Output Logic "1" Voltage, I

= 2 mA

2.4

Output Logic "0" Voltage, I

= 8 mA

0.4

CC1

(4,5,6)

Active Power Supply Current

CC2

(4,7)

Standby Current

NOTES

Industrial temperature range product for the 15ns is available as a standard device.

2. Measurements with 0.4

IH,

0.4

OUT

CC.

4. Tested with outputs open (I

OUT

= 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. Typical I

CC1

= 11 + 1.65*f

+ 0.02*C

(in mA) with V

= 3.3V, t

= 25

C, f

= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f

/2, C

= capacitive load (in pF).

7. All Inputs = V

- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

ABSOLUTE MAXIMUM RATINGS

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING

CONDITIONS

CAPACITANCE

= +25

C, f = 1.0MHz)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: V

= 3.3V ± 0.3V, T

= 0

C to +70

C; Industrial: V

= 3.3V

3.3V, TA = -40

C to + 85

Commercial Com'l & Ind'l

(2)

Commercial

IDT72V275L10 IDT72V275L15 IDT72V275L20

IDT72V285L10

IDT72V285L15

IDT72V285L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Clock Cycle Frequency

100

66.7

MHz

Data Access Time

6.5

CLK

Clock Cycle Time

CLKH

Clock High Time

4.5

CLKL

Clock Low Time

4.5

Data Setup Time

Data Hold Time

0.5

ENS

Enable Setup Time

ENH

Enable Hold Time

0.5

LDS

Load Setup Time

LDH

Load Hold Time

0.5

Reset Pulse Width

(3)

RSS

Reset Setup Time

RSR

Reset Recovery Time

RSF

Reset to Flag and Output Time

FWFT

Mode Select Time

RTS

Retransmit Setup Time

OLZ

Output Enable to Output in Low Z

(4)

Output Enable to Output Valid

OHZ

Output Enable to Output in High Z

(4)

WFF

Write Clock to

FF or IR

6.5

REF

Read Clock to

EF or OR

6.5

PAF

Write Clock to

PAF

6.5

PAE

Read Clock to

PAE

6.5

Clock to

SKEW1

Skew time between RCLK and WCLK

for

FF/IR

SKEW2

Skew time between RCLK and WCLK

for

PAE and PAF

SKEW3

Skew time between RCLK and WCLK

for

EF/OR

NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2 Industrial Temperature Range Product for the 15ns speed grade is available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 2

AC TEST CONDITIONS

Figure 2. Output Load

* Includes jig and scope capacitances.

4512 drw 04

330

30pF*

510

3.3V

D.U.T.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

When configured in IDT Standard mode, the

EF and FF outputs are double

Relevant timing diagrams for IDT Standard mode can be found in Figure

7, 8 and 11.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags,

IR, PAF, HF, PAE, and OR operate in the

manner outlined in Table 2. To write data into to the FIFO,

WEN must be LOW.

Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (

OR)

flag will go LOW. Subsequent writes will continue to fill up the FIFO.

PAE will

go HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for this value is stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.

If one continued to write data into the FIFO, and we assumed no read

operations were taking place, the

HF would toggle to LOW once the 16,386th

word for the IDT72V275 and 32,770th word for the IDT72V285, respectively
was written into the FIFO. Continuing to write data into the FIFO will cause the
PAF to go LOW. Again, if no reads are performed, the PAF will go LOW after
(32,769-m) writes for the IDT72V275 and (65,537-m) writes for the IDT72V285,
where m is the full offset value. The default setting for this value is stated in the
footnote of Table 2.

When the FIFO is full, the Input Ready (

IR) flag will go HIGH, inhibiting further

write operations. If no reads are performed after a reset,

IR will go HIGH after

D writes to the FIFO. D = 32,769 writes for the IDT72V275 and 65,537 writes
for the IDT72V285, respectively. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.

If the FIFO is full, the first read operation will cause the

IR flag to go LOW.

Subsequent read operations will cause the

PAF and HF to go HIGH at the

conditions described in Table 2. If further read operations occur, without write
operations, the

PAE will go LOW when there are n + 1 words in the FIFO, where

n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO,

OR will go

HIGH inhibiting further read operations.

REN is ignored when the FIFO is

empty.

When configured in FWFT mode, the

OR flag output is triple register-

buffered, and the

IR flag output is double register-buffered.

Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and

12.

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable. The IDT72V275/

72V285 has internal registers for these offsets. Default settings are stated in the
footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO
in one of two ways; serial or parallel loading method. The selection of the loading
method is done using the

LD (Load) pin. During Master Reset, the state of the

LD input determines whether serial or parallel flag offset programming is
enabled. A HIGH on

LD during Master Reset selects serial loading of offset

values and in addition, sets a default

PAE offset value of 3FFH (a threshold

1,023 words from the empty boundary), and a default

PAF offset value of 3FFH

(a threshold 1,023 words from the full boundary). A LOW on

LD during Master

Reset selects parallel loading of offset values, and in addition, sets a default

PAE

offset value of 07FH (a threshold 127 words from the empty boundary), and
a default

PAF offset value of 07FH (a threshold 127 words from the full

boundary). See Figure 3, Offset Register Location and Default Values.

In addition to loading offset values into the FIFO, it also possible to read the

current offset values. It is only possible to read offset values via parallel read.

.UNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE

The IDT72V275/72V285 support two different timing modes of operation:

IDT Standard mode or First Word Fall Through (FWFT) mode. The selection
of which mode will operate is determined during Master Reset, by the state of
the FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode

will be selected. This mode uses the Empty Flag (

EF) to indicate whether or

not there are any words present in the FIFO. It also uses the Full Flag function
(

FF) to indicate whether or not the FIFO has any free space for writing. In IDT

Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (

REN) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be

selected. This mode uses Output Ready (

OR) to indicate whether or not there

is valid data at the data outputs (Q

. It also uses Input Ready (

IR) to indicate

whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Q

after three RCLK rising

edges,

REN = LOW is not necessary. Subsequent words must be accessed

using the Read Enable (

REN) and RCLK.

Various signals, both input and output signals operate differently depending

on which timing mode is in effect.

IDT STANDARD MODE

In this mode, the status flags,

FF, PAF, HF, PAE, and EF operate in the

manner outlined in Table 1. To write data into to the FIFO, Write Enable (

WEN)

must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (

EF) will go HIGH. Subsequent writes will continue

to fill up the FIFO. The Programmable Almost-Empty flag (

PAE) will go HIGH

after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for this value is stated in the footnote of Table 1. This
parameter is also user programmable. See section on Programmable Flag
Offset Loading.

If one continued to write data into the FIFO, and we assumed no read

operations were taking place, the Half-Full flag (

HF) would toggle to LOW once

the 16,385th word for IDT72V275 and 32,769th word for IDT72V285
respectively was written into the FIFO. Continuing to write data into the FIFO
will cause the Programmable Almost-Full flag (

PAF) to go LOW. Again, if no

reads are performed, the

PAF will go LOW after (32,768-m) writes for the

IDT72V275 and (65,536-m) writes for the IDT72V285. The offset "m" is the full
offset value. The default setting for this value is stated in the footnote of Table 1.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.

When the FIFO is full, the Full Flag (

FF) will go LOW, inhibiting further write

operations. If no reads are performed after a reset,

FF will go LOW after D writes

to the FIFO. D = 32,768 writes for the IDT72V275 and 65,536 for the
IDT72V285, respectively.

If the FIFO is full, the first read operation will cause

FF to go HIGH.

Subsequent read operations will cause

PAF and HF to go HIGH at the

conditions described in Table 1. If further read operations occur, without write
operations,

PAE will go LOW when there are n words in the FIFO, where n

is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, the

EF will

go LOW inhibiting further read operations.

REN is ignored when the FIFO is

empty.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

Number of

Words in

FIFO

1 to n

(1)

(n+1) to 16,384

16,385 to (32,768-(m+1))

(32,768-m)

(2)

to 32,767

32,768

1 to n

(1)

(n+1) to 32,768

32,769 to (65,536-(m+1))

(65,536-m)

(2)

to 65,535

65,536

TABLE 2. STATUS FLAGS FOR FWFT MODE

72V275

72V285

FF PAF HF PAE EF

TABLE 1. STATUS FLAGS FOR IDT STANDARD MODE

4512 drw 05

1 to n+1

(1)

(n+2) to 16,385

(32,769-m)

(2)

to 32,768

32,769

1 to n+1

(1)

(n+2) to 32,769

32,770 to (65,537-(m+1))

(65,537-m)

(2)

to 65,536

65,537

IR PAF HF PAE OR

72V275

72V285

Number of

Words in

FIFO

16,386 to (32,769-(m+1))

NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

Figure 4, Programmable Flag Offset Programming Sequence, summa-

rizes the control pins and sequence for both serial and parallel programming
modes. For a more detailed description, see discussion that follows.

The offset registers may be programmed (and reprogrammed) any time after

Master Reset, regardless of whether serial or parallel programming has been
selected.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

SERIAL PROGRAMMING MODE

If Serial Programming mode has been selected, as described above, then

programming of

PAE and PAF values can be achieved by using a

combination of the

LD, SEN, WCLK and SI input pins. Programming PAE

and

PAF proceeds as follows: when LD and SEN are set LOW, data on the

SI input are written, one bit for each WCLK rising edge, starting with the Empty
Offset LSB and ending with the Full Offset MSB. A total of 30 bits for the
IDT72V275 and 32 bits for the IDT72V285. See Figure 13, Serial Loading of
Programmable Flag Registers, for the timing diagram for this mode.

Using the serial method, individual registers cannot be programmed

selectively.

PAE and PAF can show a valid status only after the complete

set of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.

Write operations to the FIFO are allowed before and during the serial

programming sequence. In this case, the programming of all offset bits does
not have to occur at once. A select number of bits can be written to the SI input
and then, by bringing

LD and SEN HIGH, data can be written to FIFO memory

via D

by toggling

WEN. When WEN is brought HIGH with LD and SEN

restored to a LOW, the next offset bit in sequence is written to the registers via
SI. If an interruption of serial programming is desired, it is sufficient either to set
LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once
LD and SEN are both restored to a LOW level, serial offset programming
continues.

From the time serial programming has begun, neither partial flag will be valid

until the full set of bits required to fill all the offset registers has been written.
Measuring from the rising WCLK edge that achieves the above criteria;

PAF

will be valid after two more rising WCLK edges plus t

PAF

PAE will be valid

after the next two rising RCLK edges plus t

PAE

plus t

SKEW2

It is not possible to read the flag offset values in a serial mode.

PARALLEL MODE

If Parallel Programming mode has been selected, as described above, then

programming of

PAE and PAF values can be achieved by using a

combination of the

LD, WCLK , WEN and D

input pins. Programming

PAE

and

PAF proceeds as follows: when LD and WEN are set LOW, data on

the inputs D

are written into the Empty Offset Register on the first LOW-to-HIGH

transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK, data
are written into the Full Offset Register. The third transition of WCLK writes, once
again, to the Empty Offset Register. See Figure 14, Parallel Loading of
Programmable Flag Registers, for the timing diagram for this mode.

The act of writing offsets in parallel employs a dedicated write offset register

pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.

Write operations to the FIFO are allowed before and during the parallel

programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing

LD HIGH, write operations can be redirected to

the FIFO memory. When

LD is set LOW again, and WEN is LOW, the next

offset register in sequence is written to. As an alternative to holding

WEN LOW

and toggling

LD, parallel programming can also be interrupted by setting LD

LOW and toggling

WEN.

Note that the status of a partial flag (

PAE or PAF) output is invalid during

the programming process. From the time parallel programming has begun, a
partial flag output will not be valid until the appropriate offset word has been

written to the register(s) pertaining to that flag. Measuring from the rising WCLK
edge that achieves the above criteria;

PAF will be valid after two more rising

WCLK edges plus t

PAF

PAE will be valid after the next two rising RCLK edges

plus t

PAE

plus t

SKEW2

The act of reading the offset registers employs a dedicated read offset

-Q

pins when

LD is set LOW and REN is set LOW. Data are read via Q

from the

Empty Offset Register on the first LOW-to-HIGH transition of RCLK. Upon the
second LOW-to-HIGH transition of RCLK, data are read from the Full Offset
Register. The third transition of RCLK reads, once again, from the Empty Offset
Register. See Figure 15, Parallel Read of Programmable Flag Registers, for
the timing diagram for this mode.

It is permissible to interrupt the offset register read sequence with reads or

writes to the FIFO. The interruption is accomplished by deasserting

REN, LD,

or both together. When

REN and LD are restored to a LOW level, reading

of the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.

Parallel reading of the offset registers is always permitted regardless of

which timing mode (IDT Standard or FWFT modes) has been selected.

RETRANSMIT OPERATION

The Retransmit operation allows data that has already been read to be

accessed again. There are two stages: first, a setup procedure that resets the
read pointer to the first location of memory, then the actual retransmit, which
consists of reading out the memory contents, starting at the beginning of memory.

Retransmit setup is initiated by holding

RT LOW during a rising RCLK edge.

REN and WEN must be HIGH before bringing RT LOW. At least one word,
but no more than D - 2 words should have been written into the FIFO between
Reset (Master or Partial) and the time of Retransmit setup. D = 32,768 for the
IDT72V275 and D = 65,536 for the IDT72V285. In FWFT mode, D = 32,769
for the IDT72V275 and D= 65,537 for the IDT72V285.

If IDT Standard mode is selected, the FIFO will mark the beginning of the

Retransmit setup by setting

EF LOW. The change in level will only be noticeable

EF was HIGH before setup. During this period, the internal read pointer is

initialized to the first location of the RAM array.

When

EF goes HIGH, Retransmit setup is complete and read operations

may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on

REN to enable the rising edge of RCLK. See Figure 11,

Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.

If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit

setup by setting

OR HIGH. During this period, the internal read pointer is set

to the first location of the RAM array.

When

OR goes LOW, Retransmit setup is complete; at the same time, the

contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on

REN is necessary. Reading

all subsequent words requires a LOW on

REN to enable the rising edge of

RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.

For either IDT Standard mode or FWFT mode, updating of the

PAE, HF

and

PAF flags begin with the rising edge of RCLK that RT is setup. PAE is

synchronized to RCLK, thus on the second rising edge of RCLK after

RT is

setup, the

PAE flag will be updated. HF is asynchronous, thus the rising edge

of RCLK that

RT is setup will update HF. PAF is synchronized to WCLK, thus

the second rising edge of WCLK that occurs t

SKEW

after the rising edge of RCLK

that

RT is setup will update PAF. RT is synchronized to RCLK.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

SIGNAL DESCRIPTION

INPUTS:

DATA IN (D

- D

)

Data inputs for 18-bit wide data.

CONTROLS:

MASTER RESET (

MRS

MRS)

A Master Reset is accomplished whenever the

MRS input is taken to

a LOW state. This operation sets the internal read and write pointers to the
first location of the RAM array.

PAE will go LOW, PAF will go HIGH, and

HF will go HIGH.

If FWFT is LOW during Master Reset then the IDT Standard mode,

along with

EF and FF are selected. EF will go LOW and FF will go HIGH.

If FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.

LD is LOW during Master Reset, then PAE is assigned a threshold

127 words from the empty boundary and

PAF is assigned a threshold 127

words from the full boundary; 127 words corresponds to an offset value of
07FH. Following Master Reset, parallel loading of the offsets is permitted,
but not serial loading.

LD is HIGH during Master Reset, then PAE is assigned a threshold

1,023 words from the empty boundary and

PAF is assigned a threshold

1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.

Parallel reading of the registers is always permitted. (See section

describing the

LD pin for further details.)

During a Master Reset, the output register is initialized to all zeroes. A

Master Reset is required after power up, before a write operation can take
place.

MRS is asynchronous.

See Figure 5, Master Reset Timing, for the relevant timing diagram.

PARTIAL RESET (

PRS

PRS)

A Partial Reset is accomplished whenever the

PRS input is taken to a LOW

state. As in the case of the Master Reset, the internal read and write pointers are
set to the first location of the RAM array,

PAE goes LOW, PAF goes HIGH, and

HF goes HIGH.

Whichever mode is active at the time of Partial Reset, IDT Standard mode

or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then

FF will go HIGH and EF will go LOW. If the First Word

Fall Through mode is active, then

OR will go HIGH, and IR will go LOW.

Following Partial Reset, all values held in the offset registers remain

unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes.

PRS is asynchronous.

A Partial Reset is useful for resetting the device during the course of

operation, when reprogramming partial flag offset settings may not be
convenient.

See Figure 6, Partial Reset Timing, for the relevant timing diagram.

RETRANSMIT (

RT)

The Retransmit operation allows data that has already been read to be

Retransmit setup is initiated by holding

RT LOW during a rising RCLK edge.

REN and WEN must be HIGH before bringing RT LOW.

If IDT Standard mode is selected, the FIFO will mark the beginning of

the Retransmit setup by setting

EF LOW. The change in level will only be

noticeable if

EF was HIGH before setup. During this period, the internal

read pointer is initialized to the first location of the RAM array.

When

EF goes HIGH, Retransmit setup is complete and read opera-

tions may begin starting with the first location in memory. Since IDT
Standard mode is selected, every word read including the first word
following Retransmit setup requires a LOW on

REN to enable the rising

edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for
the relevant timing diagram.

If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit

setup by setting

OR HIGH. During this period, the internal read pointer is set to

the first location of the RAM array.

When

OR goes LOW, Retransmit setup is complete; at the same time,

the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on

REN is

necessary. Reading all subsequent words requires a LOW on

REN to

enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

This is a dual purpose pin. During Master Reset, the state of the FWFT/SI

input determines whether the device will operate in IDT Standard mode or First
Word Fall Through (FWFT) mode.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard

mode will be selected. This mode uses the Empty Flag (

EF) to indicate

whether or not there are any words present in the FIFO memory. It also uses
the Full Flag function (

FF) to indicate whether or not the FIFO memory has

any free space for writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read Enable (

REN)

and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will

be selected. This mode uses Output Ready (

OR) to indicate whether or not

there is valid data at the data outputs (Q

. It also uses Input Ready (

IR)

to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to
Q

after three RCLK rising edges,

REN = LOW is not necessary. Subse-

quent words must be accessed using the Read Enable (

REN) and RCLK.

After Master Reset, FWFT/SI acts as a serial input for loading

PAE and

PAF offsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.

WRITE CLOCK (WCLK)

A write cycle is initiated on the rising edge of the WCLK input. Data setup

and hold times must be met with respect to the LOW-to-HIGH transition of
the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle,
the

FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only

capable of updating

HF flag to LOW.) The Write and Read Clocks can either

be independent or coincident.

WRITE ENABLE (

WEN

WEN)

When the

WEN input is LOW, data may be loaded into the FIFO RAM

array on the rising edge of every WCLK cycle if the device is not full. Data
is stored in the RAM array sequentially and independently of any ongoing
read operation.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

When

WEN is HIGH, no new data is written in the RAM array on each

WCLK cycle.

To prevent data overflow in the IDT Standard mode,

FF will go LOW,

inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + t

SKEW

after the RCLK cycle.

To prevent data overflow in the FWFT mode,

IR will go HIGH, inhibiting

further write operations. Upon the completion of a valid read cycle,

IR will go

LOW allowing a write to occur. The

IR flag is updated by two WCLK

cycles + t

SKEW

after the valid RCLK cycle.

WEN is ignored when the FIFO is full in either FWFT or IDT Standard

mode.

READ CLOCK (RCLK)

A read cycle is initiated on the rising edge of the RCLK input. Data can be

read on the outputs, on the rising edge of the RCLK input. It is permissible to
stop the RCLK. Note that while RCLK is idle, the

EF/OR, PAE and HF flags

will not be updated. (Note that RCLK is only capable of updating the

HF flag

to HIGH.) The Write and Read Clocks can be independent or coincident.

READ ENABLE (

REN

REN)

When Read Enable is LOW, data is loaded from the RAM array into the output

When the

REN input is HIGH, the output register holds the previous data

and no new data is loaded into the output register. The data outputs Q

-Q

maintain the previous data value.

In the IDT Standard mode, every word accessed at Q

, including the first

word written to an empty FIFO, must be requested using

REN. When the last

word has been read from the FIFO, the Empty Flag (

EF) will go LOW, inhibiting

further read operations.

REN is ignored when the FIFO is empty. Once a write

is performed,

EF will go HIGH allowing a read to occur. The EF flag is updated

by two RCLK cycles + t

SKEW

after the valid WCLK cycle.

In the FWFT mode, the first word written to an empty FIFO automatically goes

to the outputs Q

, on the third valid LOW to HIGH transition of RCLK + t

SKEW

after the first write.

REN does not need to be asserted LOW. In order to access

all other words, a read must be executed using

REN. The RCLK LOW to HIGH

transition after the last word has been read from the FIFO, Output Ready (

OR)

will go HIGH with a true read (RCLK with

REN = LOW), inhibiting further read

operations.

REN is ignored when the FIFO is empty.

SERIAL ENABLE (

SEN

SEN)

The

SEN input is an enable used only for serial programming of the offset

registers. The serial programming method must be selected during Master
Reset.

SEN is always used in conjunction with LD. When these lines are both

LOW, data at the SI input can be loaded into the program register one bit for each
LOW-to-HIGH transition of WCLK. (See Figure 4.)

When

SEN is HIGH, the programmable registers retains the previous

settings and no offsets are loaded.

SEN functions the same way in both IDT

Standard and FWFT modes.

OUTPUT ENABLE (

OE)

When Output Enable is enabled (LOW), the parallel output buffers receive

data from the output register. When

OE is HIGH, the output data bus (Q

) goes

into a high impedance state.

LOAD (

LD)

This is a dual purpose pin. During Master Reset, the state of the

LD input

determines one of two default offset values (127 or 1,023) for the

PAE and PAF

flags, along with the method by which these offset registers can be programmed,
parallel or serial. After Master Reset,

LD enables write operations to and read

operations from the offset registers. Only the offset loading method currently
selected can be used to write to the registers. Offset registers can be read only
in parallel. A LOW on

LD during Master Reset selects a default PAE offset

value of 07FH (a threshold 127 words from the empty boundary), a default

PAF

offset value of 07FH (a threshold 127 words from the full boundary), and parallel
loading of other offset values. A HIGH on

LD during Master Reset selects a

default

PAE offset value of 3FFH (a threshold 1,023 words from the empty

boundary), a default

PAF offset value of 3FFH (a threshold 1,023 words from

the full boundary), and serial loading of other offset values.

After Master Reset, the

LD pin is used to activate the programming process

of the flag offset values

PAE and PAF. Pulling LD LOW will begin a serial

loading or parallel load or read of these offset values. See Figure 4, Program-
mable Flag Offset Programming Sequence.

OUTPUTS:

FULL FLAG (

FF/IR

IR)

This is a dual purpose pin. In IDT Standard mode, the Full Flag (

FF)

function is selected. When the FIFO is full,

FF will go LOW, inhibiting further write

operations. When

FF is HIGH, the FIFO is not full. If no reads are performed

after a reset (either

MRS or PRS), FF will go LOW after D writes to the FIFO

(D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285). See Figure
7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing
information.

In FWFT mode, the Input Ready (

IR) function is selected. IR goes LOW

when memory space is available for writing in data. When there is no longer
any free space left,

IR goes HIGH, inhibiting further write operations. If no reads

are performed after a reset (either

MRS or PRS), IR will go HIGH after

D writes to the FIFO (D = 32,769 for the IDT72V275 and 65,537 for the
IDT72V285) See Figure 9, Write Timing (FWFT Mode), for the relevant timing
information.

The

IR status not only measures the contents of the FIFO memory, but also

counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert

IR is one greater than needed to

assert

FF in IDT Standard mode.

FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR

are double register-buffered outputs.

EMPTY FLAG (

EF/OR

OR)

This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (

EF)

function is selected. When the FIFO is empty,

EF will go LOW, inhibiting further

read operations. When

EF is HIGH, the FIFO is not empty. See Figure 8, Read

Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
the relevant timing information.

In FWFT mode, the Output Ready (

OR) function is selected. OR goes LOW

at the same time that the first word written to an empty FIFO appears valid on
the outputs.

OR stays LOW after the RCLK LOW to HIGH transition that shifts

the last word from the FIFO memory to the outputs.

OR goes HIGH only with

a true read (RCLK with

REN = LOW). The previous data stays at the outputs,

indicating the last word was read. Further data reads are inhibited until

OR goes

LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.

EF/OR is synchronous and updated on the rising edge of RCLK.

In IDT Standard mode,

EF is a double register-buffered output. In FWFT

mode,

OR is a triple register-buffered output.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

PROGRAMMABLE ALMOST-FULL FLAG (

PAF

PAF)

The Programmable Almost-Full flag (

PAF) will go LOW when the FIFO

reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (

MRS), PAF will go LOW after (D - m) words are written

to the FIFO. The

PAF will go LOW after (32,768-m) writes for the IDT72V275

and (65,536-m) writes for the IDT72V285. The offset "m" is the full offset value.
The default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the

PAF will go LOW after (32,769-m) writes for the

IDT72V275 and (65,537-m) writes for the IDT72V285, where m is the full offset
value. The default setting for this value is stated in the footnote of Table 2.

See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard

and FWFT Mode), for the relevant timing information.

PAF is synchronous and updated on the rising edge of WCLK.

PROGRAMMABLE ALMOST-EMPTY FLAG (

PAE

PAE)

The Programmable Almost-Empty flag (

PAE) will go LOW when the FIFO

reaches the almost-empty condition. In IDT Standard mode,

PAE will go LOW

when there are n words or less in the FIFO. The offset "n" is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the

PAE will go LOW when there are n+1 words or less

in the FIFO. The default setting for this value is stated in the footnote of Table 2.

See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard

and FWFT Mode), for the relevant timing information.

PAE is synchronous and updated on the rising edge of RCLK.

HALF-FULL FLAG (

HF)

This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO

beyond half-full sets

HF LOW. The flag remains LOW until the difference

between the write and read pointers becomes less than or equal to half of the
total depth of the device; the rising RCLK edge that accomplishes this condition
sets

HF HIGH.

In IDT Standard mode, if no reads are performed after reset (

MRS or

PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 32,768
for the IDT72V275 and 65,536 for the IDT72V285.

In FWFT mode, if no reads are performed after reset (

MRS or PRS), HF

will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 32,769 for the
IDT72V275 and 65,537 for the IDT72V285.

See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),

for the relevant timing information. Because

HF is updated by both RCLK and

WCLK, it is considered asynchronous.

DATA OUTPUTS (Q

-Q

)

- Q

) are data outputs for 18-bit wide data.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)

NOTES:
1. t

SKEW3

is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that

EF will go HIGH (after one RCLK cycle plus t

REF

). If the time between the rising edge

of WCLK and the rising edge of RCLK is less than t

SKEW3

, then

EF deassertion may be delayed one extra RCLK cycle.

LD = HIGH.

3. First word latency: 60ns + t

REF

+ 1*T

RCLK

NOTES:
1. t

SKEW1

is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

FF will go high (after one WCLK cycle pus t

WFF

). If the time between the rising

edge of the RCLK and the rising edge of the WCLK is less than t

SKEW1

, then the

FF deassertion may be delayed one extra WCLK cycle.

LD = HIGH, OE = LOW, EF = HIGH.

Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)

NO OPERATION

RCLK

REN

4512 drw 11

CLK

CLKH

CLKL

ENH

REF

OLZ

- Q

WCLK

(1)

SKEW3

WEN

- D

ENS

ENH

DHS

OLZ

NO OPERATION

LAST WORD

ENS

ENH

OHZ

LAST WORD

REF

ENH

ENS

REF

ENS

ENH

- D

WEN

RCLK

REN

ENH

- Q

DATA READ

NEXT DATA READ

DATA IN OUTPUT REGISTER

SKEW1

(1)

4512 drw 10

WCLK

NO WRITE

WFF

ENS

SKEW1

(1)

CLK

CLKH

CLKL

WFF

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.

OPTIONAL CON.IGURATIONS

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting together the control

signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the

EF and FF functions in IDT Standard mode

and the

IR and OR functions in FWFT mode. Because of variations in skew

between RCLK and WCLK, it is possible for

EF/FF deassertion and IR/

OR assertion to vary by one cycle between FIFOs. In IDT Standard mode,
such problems can be avoided by creating composite flags, that is, ANDing

Figure 19. Block Diagram of 32,768 x 36 and 65,536 x 36 Width Expansion

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)

The IDT72V275 can easily be adapted to applications requiring depths

greater than 32,768 and 65,536 for the IDT72V285 with an 18-bit bus width.
In FWFT mode, the FIFOs can be connected in series (the data outputs of one
FIFO connected to the data inputs of the next) with no external logic necessary.
The resulting configuration provides a total depth equivalent to the sum of the
depths associated with each single FIFO. Figure 20 shows a depth expansion
using two IDT72V275/72V285 devices.

Care should be taken to select FWFT mode during Master Reset for all FIFOs

in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chainno read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's

OR line goes LOW,

enabling a write to the next FIFO in line.

For an empty expansion configuration, the amount of time it takes for

OR of

the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's

outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:

(N 1)*(4*transfer clock) + 3*T

RCLK

where N is the number of FIFOs in the expansion and T

RCLK

is the RCLK period.

Note that extra cycles should be added for the possibility that the t

SKEW3

specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the

OR flag.

The "ripple down" delay is only noticeable for the first word written to an empty

depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.

The first free location created by reading from a full depth expansion

configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's

IR line goes LOW, enabling the preceding FIFO

to write a word to fill it.

EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing

OR of every FIFO, and separately

ORing

IR of every FIFO.

Figure 19 demonstrates a width expansion using two IDT72V275/72V285

devices. D

- D

from each device form a 36-bit wide input bus and Q

-Q

from each device form a 36-bit wide output bus. Any word width can be attained
by adding additional IDT72V275/72V285 devices.

WRITE CLOCK (WCLK)

m + n

MASTER RESET (

MRS

)

READ CLOCK (RCLK)

DATA OUT

m + n

WRITE ENABLE (

WEN

)

FULL FLAG/INPUT READY (

)

PROGRAMMABLE (

PAF

)

PROGRAMMABLE (

PAE

)

EMPTY FLAG/OUTPUT READY (

) #2

OUTPUT ENABLE (

)

READ ENABLE (

REN

)

LOAD (

)

IDT

72V275
72V285

EMPTY FLAG/OUTPUT READY (

) #1

PARTIAL RESET (

PRS

)

IDT

72V275
72V285

4512 drw 22

FULL FLAG/INPUT READY (

) #2

HALF-FULL FLAG (

)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

RETRANSMIT (

)

FIFO

GATE

(1)

GATE

(1)

- Dm

DATA IN

- Dn

- Qm

- Qn

FIFO

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 72V275

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 72V275