3.3 VOLT CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING
64 x 36

IDT72V3613

MAY 2003

DSC-4661/1

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

FEATURES:

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·
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64 x 36 storage capacity FIFO buffering data from Port A to Port B

·
·
·
·
·

Supports clock frequencies up to 83MHz

·
·
·
·
·

Fast access times of 8ns

·
·
·
·
·

Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of data on
a single clock edge)

·
·
·
·
·

Mailbox bypass registers in each direction

·
·
·
·
·

Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)

·
·
·
·
·

Selection of Big- or Little-Endian format for word and byte bus
sizes

·
·
·
·
·

Three modes of byte-order swapping on Port B

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·
·
·
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Programmable Almost-Full and Almost-Empty flags

·
·
·
·
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Microprocessor interface control logic

·
·
·
·
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FF , AF flags synchronized by CLKA

·
·
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·
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EF , AE flags synchronized by CLKB

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·
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Passive parity checking on each Port

·
·
·
·
·

Parity Generation can be selected for each Port

·
·
·
·
·

Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)

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·
·
·
·

Pin and functionally compatible version of the 5V operating
IDT723613

·
·
·
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·

Industrial temperature range (40

°°
°°
°C to +85°°°°°C) is available

DESCRIPTION:

The IDT72V3613 is a pin and functionally compatible version of the

IDT723613, designed to run off a 3.3V supply for exceptionally low-power
consumption. This device is a monolithic, high-speed, low-power, CMOS
synchronous (clocked) FIFO memory which supports clock frequencies up to
83 MHz and has read-access times as fast as 8 ns. The 64 x 36 dual-port SRAM
FIFO buffers data from port A to port B. The FIFO operates in IDT Standard
mode and has flags to indicate empty and full conditions, and two programmable
flags, Almost-Full (

AF) and Almost-Empty (AE), to indicate when a selected

number of words is stored in memory. FIFO data on port B can be output in 36-
bit, 18-bit, and 9-bit formats with a choice of Big- or Little-Endian configurations.

FUNCTIONAL BLOCK DIAGRAM

Mail 2

Mail 1

Input

Output

64 x 36

Write

Pointer

Read

Pointer

Status Flag

Logic

CLKA

CSA

ENA

MBA

Port-A

Control

Logic

Device

Control

RST

PEFA

MBF2

Port-B

Control

Logic

MBF1

- B

4661 drw 01

Programmable

Flag Offset

Registers

- A

Parity

Gen/Check

Parity

Generation

FIFO

ODD/

EVEN

PGA

Parity

Gen/Check

PGB

PEFB

RAM ARRAY

64 x 36

Bus-Matching and

Byte Swapping

Output

CLKB

CSB
W/

ENB

BE
SIZ0
SIZ1
SW0
SW1

Port-B

Control

Logic

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

DESCRIPTION (CONTINUED)

PIN CONFIGURATION

NOTE:
1. NC = No internal connection

TQFP (PN120-1, order code: PF)

TOP VIEW

4661 drw 02

GND

NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND
B

AE
NC

90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61

AF FF

CSA ENA

CLKA

PGA

PEFA MBF2 MBA

ODD/

EVEN

RST GND

SW1

SW0

SIZ1

MBF1

SIZ0

PEFB

PGB

CLKB

ENB

CSB NC

33 34

36 37

48 49

50 51

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

GND

Three modes of byte-order swapping are possible with any bus-size selection.
Communication between each port can bypass the FIFO via two 36-bit mailbox
registers. Each mailbox register has a flag to signal when new mail has been
stored. Parity is checked passively on each port and may be ignored if not
desired. Parity generation can be selected for data read from each port. Two
or more devices may be used in parallel to create wider data paths.

The IDT72V3613 is a synchronous (clocked) FIFO, meaning each port

employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a continuous (free-running) port clock by

enable signals. The continuous clocks for each port are independent of one
another and can be asynchronous or coincident. The enables for each port are
arranged to provide a simple interface between microprocessors and/or buses
with synchronous interfaces.

The Full Flag (

FF) and Almost-Full (AF) flag of the FIFO are two-stage

synchronized to the port clock (CLKA) that writes data into its array. The Empty
Flag (

EF) and Almost-Empty (AE) flag of the FIFO are two-stage synchronized

to the port clock (CLKB) that reads data from its array.

The IDT72V3613 is characterized for operation from 0

°C to 70°C. Industrial

temperature range (40

°C to +85°C) is available by special order. This device

is fabricated using IDT's high speed, submicron CMOS technology.

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

GND

EF
B

GND
B

GND

NC
NC

GND

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

4661 drw 03

117

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

GND

AF FF CSA ENA CLKA W/

PGA

ODD/

EVEN

PEFA

MBF2

RST

GND

SW1

SW0

SIZ1

MBF1 GND PEFB

CLKB

ENB

CSB NC

GND

MBA

SIZ0

PGB

NOTES:
1. NC = No internal connection.
2. Uses Yamaichi socket IC51-1324-828.

PQFP

(2)

(PQ132-1, order code: PQF)

TOP VIEW

Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.

PIN CONFIGURATION (CONTINUED)

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol

Name

I/O

Description

-A

Port A Data

I/O

36-bit bidirectional data port for side A.

Almost-Empty Flag

Programmable Almost-Empty flag synchronized to CLKB. It is LOW when Port B the number of 36-bit

Port B

words in the FIFO is less than or equal to the value in the offset register, X.

Almost-Full Flag

Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty

Port A

empty locations in the FIFO is less than or equal to the value in the offset register, X.

-B

Port B Data

I/O

36-bit bidirectional data port for side B

Big-Endian Select

Selects the bytes on port B used during byte or word FIFO reads. A LOW on

BE selects the most

significant bytes on B0-B35 for use, and a HIGH selects the least significant bytes.

CLKA

Port A Clock

CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB.

FF and AF are synchronized to the LOW-to-HIGH transition of CLKA.

CLKB

Port B Clock

CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. Port-B byte swapping and data port sizing operations are also synchronous to the
LOW-to-HIGH transition of CLKB.

EF and AE are synchronized to the LOW-to-HIGH transition of CLKB.

CSA

Port A Chip Select

CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0-
A35 outputs are in the high-impedance state when

CSA is HIGH.

CSB

Port B Chip Select

CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0-
B35 outputs are in the high-impedance state when

CSB is HIGH.

Empty Flag

EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, the FIFO is empty, and

Port B

reads from its memory are disabled. Data can be read from the FIFO to its output register when

EF is

HIGH.

EF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKB after data is loaded into empty FIFO memory.

ENA

Port A Enable

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.

ENB

Port B Enable

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.

Full Flag

FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW, the FIFO is full, and

Port A

writes to its memory are disabled.

FF is forced LOW when the device is reset and is set HIGH by the

second LOW-to-HIGH transition of CLKA after reset.

, FS

Flag Offset Selects

The LOW-to-HIGH transition of

RST latches the values of FS0 and FS1, which loads one of four preset

values into the Almost-Full flag and Almost-Empty flag offsets.

MBA

Port A Mailbox

A high level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35

Select

outputs are active, mail2 register data is output.

MBF1

Mail1 Register Flag

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
mail1 register are inhibited while

MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of

CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH.

MBF1 is set HIGH when the

device is reset.

MBF2

Mail2 Register Flag

MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
mail2 register are inhibited while

MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of

CLKA when a port A read is selected and MBA is HIGH.

MBF2 is set HIGH when the device is reset.

ODD/

Odd/Even Parity

Odd parity is checked on each port when ODD/

EVEN is HIGH, and even parity is checked when

EVEN

Select

ODD/

EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity

generation is enabled for a read operation.

PEFA

Port A Parity Error

When any valid byte applied to terminals A0-A35 fails parity,

PEFA is LOW. Bytes (Port A) are organized

Flag

as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/

EVEN input.

The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH and PGA HIGH, the PEFA flag is forced HIGH
regardless of the state of the A0-A35 inputs.

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONTINUED)

Symbol

Name

I/O

Description

PEFB

Port B Parity Error

When any valid byte applied to terminals B0-B35 fails parity,

PEFB is LOW. Bytes are organized as

Flag

(Port B) B0-B8, B9-B17, B-18-B26, and B27-B35, with the most significant bit of each byte serving as the parity

bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is
determined by the state of the ODD/

EVEN input.

The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if
parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having
CSB LOW, ENB HIGH, W/RB LOW, SIZ1 and SIZ0 HIGH and PGB HIGH, the PEFB flag is forced HIGH
regardless of the state of the B0-B35 inputs.

PGA

Port A Parity

Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity

Generation

generated is selected by the state of the ODD/

EVEN input. Bytes are organized at A0-A8, A9-A17, A18-

A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte.

PGB

Port B Parity

Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is

Generation

selected by the state of the ODD/

EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and

B27-B35. The generated parity bits are output in the most significant bit of each byte.

RST

Reset

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while

RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF

flags LOW. The LOW-to-HIGH transition of

RST latches the status of the FS1 and FS0 inputs to select

Almost-Full flag and Almost-Empty flag offset.

SIZ0,

Port B Bus Size

A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and

BE, and the following LOW-to-

SIZ1

Selects

(Port B) HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be long

word, word, or byte. A HIGH on both SIZ0 and SIZ1 chooses a mailbox register for a port B 36-bit write or
read.

SW0,

Port B Byte Swap

At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by

SW1

Selects

(Port B) SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order

swapping is possible with any bus-size selection.

Port A Write/Read

A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH

Select

transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/

RA is HIGH.

Port B Write/Read

A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH

Select

transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/

RB is HIGH.

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE
RANGE (unless otherwise noted)

(1)

Symbol

Rating

Commercial

Unit

Supply Voltage Range

0.5 to +4.6

(2)

Input Voltage Range

0.5 to V

+0.5

(2)

Output Voltage Range

0.5 to V

+0.5

Input Clamp Current, (V

< 0 or V

> V

)

±20

Output Clamp Current, (V

< 0 or V

> V

)

±50

OUT

Continuous Output Current, (V

= 0 to V

)

±50

Continuous Current Through V

or GND

±500

STG

Storage Temperature Range

65 to 150

NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (unless otherwise noted)

Symbol

Parameter

Min. Typ.

Max.

Unit

(1)

Supply Voltage

3.0

3.3

3.6

HIGH Level Input Voltage

+0.5

LOW-Level Input Voltage

0.8

HIGH-Level Output Current

LOW-Level Output Current

Operating Free-air

Temperature

RECOMMENDED OPERATING
CONDITIONS

NOTES:
1. All typical values are at V

= 3.3V, T

= 25

2. For additional I

information, see Figure 1, Typical Characteristics: Supply Current (I

) vs. Clock Frequency (f

IDT72V3613
Commercial

CLK

= 12, 15, 20 ns

Symbol

Parameter

Test Conditions

Min.

Typ.

(1)

Max.

Unit

Output Logic "1" Voltage

= 3.0V,

= 4 mA

2.4

Output Logic "0" Voltage

= 3.0V,

= 8 mA

0.5

Input Leakage Current (Any Input)

= 3.6V,

= V

or 0

±5

µA

Output Leakage Current

= 3.6V,

= V

or 0

±5

µA

(2)

Standby Current

= 3.6V,

= V

- 0.2V or 0

500

µA

Input Capacitance

= 0,

f = 1 MHz

OUT

Output Capacitance

= 0,

f = 1 MHZ

NOTE:
1. For 12ns (83MHz operation), Vcc=3.3V +/-0.15V, JEDEC JESD8-A compliant

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

Figure 1. Typical Characteristics: Supply Current (I

) vs Clock Frequency (f

)

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3613 with CLKA and CLKB set

to f

. All date inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize

the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation
below.

CALCULATING POWER DISSIPATION

With I

CC(f

) taken from Figure 1, the maximum power dissipation (P

) of the IDT72V3613 may be calculated by:

= V

x I

CC(f)

x (V

OH -

OL)

x f

)

where:

number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus-size)

output capacitance load

switching frequency of an output

output high-level voltage

When no reads or writes are occurring on the IDT72V3613, the power dissipated by a single clock (CLKA or CLKB) input running at frequency f

is calculated

by:

= V

x f

x 0.025mA/MHz

100

125

150

= 3.3V

Clock Frequency MHz

CC(f)

Supply Current

data

= 1/2 f

= 25

°C

= 0 pF

= 3.0V

4661 drw 04

= 3.6V

175

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

IDT72V3613L12

IDT72V3613L15

IDT72V3613L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Clock Frequency, CLKA or CLKB

66.7

MHz

CLK

Clock Cycle Time, CLKA or CLKB

CLKH

Pulse Duration, CLKA and CLKB HIGH

CLKL

Pulse Duration, CLKA and CLKB LOW

Setup Time, A0-A35 before CLKA

and B0-B35 before CLKB

ENS

Setup Time,

CSA, W/RA, ENA, and MBA before CLKA

;

3.5

CSB, W/RB, and ENB before CLKB

SZS

Setup Time, SIZ0, SIZ1, and

BE before CLKB

3.5

SWS

Setup Time, SW0 and SW1 before CLKB

PGS

Setup Time, ODD/

EVEN and PGB before CLKB

(1)

RSTS

Setup Time,

RST LOW before CLKA

or CLKB

(2)

FSS

Setup Time, FS0 and FS1 before

RST HIGH

Hold Time, A0-A35 after CLKA

and B0-B35 after CLKB

0.5

ENH

Hold Time,

CSA W/RA, ENA and MBA after CLKA

; CSB,

0.5

RB, and ENB after CLKB

SZH

Hold Time, SIZ0, SIZ1, and

BE after CLKB

SWH

Hold Time, SW0 and SW1 after CLKB

PGH

Hold Time, ODD/

EVEN and PGB after CLKB

(1)

RSTH

Hold Time,

RST LOW after CLKA

or CLKB

(2)

FSH

Hold Time, FS0 and FS1 after

RST HIGH

SKEW1

(3)

Skew Time, between CLKA

and CLKB for EF and FF

5.5

SKEW2

(3,4)

Skew Time, between CLKA

and CLKB for AE and AF

NOTES:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.

Commercial: Vcc=3.3V

± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; T

= 0

C to +70

C; JEDEC JESD8-A compliant

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C

= 30pF

IDT72V3613L12

IDT72V3613L15

IDT72V3613L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Access Time, CLKA

to A0-A35 and CLKB to B0-B35

WFF

Propagation Delay Time, CLKA

to FF

REF

Propagation Delay Time, CLKB

to EF

PAE

Propagation Delay Time, CLKB

to AE

PAF

Propagation Delay Time, CLKA

to AF

PMF

Propagation Delay Time, CLKA

to MBF1 LOW or MBF2

HIGH and CLKB

to MBF2 LOW or MBF1 HIGH

PMR

Propagation Delay Time, CLKA

to B0-B35

(1)

and CLKB

to A0-A35

(2)

PPE

(3)

Propagation delay time, CLKB

to PEFB

MDV

Propagation Delay Time, SIZ1, SIZ0 to B0-B35 valid

11.5

PDPE

Propagation Delay Time, A0-A35 valid to

PEFA valid;

B0-B35 valid to

PEFB valid

POPE

Propagation Delay Time, ODD/

EVEN to PEFA and PEFB

POPB

(4)

Propagation Delay Time, ODD/

EVEN to parity bits (A8, A17,

A26, A35) and (B8, B17, B26, B35)

PEPE

Propagation Delay Time,

CSA, ENA, W/RA, MBA, or PGA

PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB

PEPB

(4)

Propagation Delay Time,

CSA, ENA, W/RA, MBA, or PGA

to parity bits (A8, A17, A26, A35);

CSB, ENB, W/RB, SIZ1,

SIZ0, or PGB to parity bits (B8, B17, B26, B35)

RSF

Propagation Delay Time,

RST to AE, EF LOW and AF,

MBF1, MBF2 HIGH

Enable Time,

CSA and W/RA LOW to A0-A35

active and

CSB LOW and W/RB HIGH to

B0-B35 active

DIS

Disable Time,

CSA or W/RA HIGH to A0-A35 at high-

impedance and

CSB HIGH or W/RB LOW to B0-B35 at

high-impedance

NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1 and SIZ0 are HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active.
3. Only applies when a new port-B bus size is implemented by the rising CLKB edge.
4. Only applies when reading data from a mail register.

Commercial: Vcc=3.3V

± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; T

= 0

C to +70

C; JEDEC JESD8-A compliant

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

TABLE 3 PORT B ENABLE FUNCTION TABLE

CSB

ENB

SIZ1, SIZ0

CLKB

Data B (B0-B35) I/O

Port Function

Input

None

Input

None

One, both LOW

Input

None

Both HIGH

Input

Mail2 write

One, both LOW

Output

None

One, both LOW

Output

FIFO read

Both HIGH

Output

None

Both HIGH

Output

Mail1 read (set

MBF1 HIGH)

FUNCTIONAL DESCRIPTION

RESET (

RST)

The IDT72V3613 is reset by taking the Reset (

RST) input LOW for at least

four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH
transitions. The Reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of the FIFO and forces the
Full Flag (

FF) LOW, the Empty Flag (EF) LOW, the Almost-Empty flag (AE) LOW,

and the Almost-Full flag (

AF) HIGH. A reset also forces the Mailbox Flags

(

MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH

transitions of CLKA. The device must be reset after power up before data is
written to its memory.

A LOW-to-HIGH transition on the

RST input loads the Almost-Full and

Almost-Empty Offset register (X) with the value selected by the Flag Select (FS0,
FS1) inputs. The values that can be loaded into the register are shown in Table
1. See Figure 5 for relevant FIFO Reset and preset value loading timing diagram.

FIFO WRITE/READ OPERATION

The state of the port A data (A0-A35) outputs is controlled by the port-A Chip

Select (

CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs

are in the high-impedance state when either

CSA or W/RA is HIGH. The A0-

A35 outputs are active when both

CSA and W/RA are LOW.

CSA

ENA

MBA

CLKA

Data A (A0-A35) I/O

Port Function

Input

None

Input

None

Input

FIFO write

Input

Mail1 write

Output

None

Output

None

Output

None

Output

Mail2 read (set

MBF2 HIGH)

TABLE 2 PORT A ENABLE FUNCTION TABLE

ALMOST-FULL AND

FS1

FS0

RST

ALMOST-EMPTY FLAG

OFFSET REGISTER (X)

TABLE 1 FLAG PROGRAMMING

Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH

transition of CLKA when

CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is

LOW, and

FF is HIGH (see Table 2). The relevant FIFO write timing diagram

can found in Figure 6.

The state of the port B data (B0-B35) outputs is controlled by the port B

Chip Select (

CSB) and the port B Write/Read select (W/RB). The B0-B35

outputs are in the high-impedance state when either

CSB or W/RB is HIGH. The

B0-B35 outputs are active when both

CSB and W/RB are LOW. Data is read

from the FIFO to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when
CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or
SIZ1 is LOW (see Table 3). Relevant FIFO read timing diagrams together with
Bus-Matching, Endian select and Byte-swapping operation can be found in
Figures 7, 8 and 9.

The setup and hold-time constraints to the port clocks for the port Chip Selects

(

CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write

and read operations and are not related to high-impedance control of the data
outputs. If a port enable is LOW during a clock cycle, the port's Chip Select and Write/
Read select can change states during the setup and hold time window of the cycle.

SYNCHRONIZED FIFO FLAGS

Each FIFO flag is synchronized to its port clock through two flip-flop stages.

This is done to improve the flags' reliability by reducing the probability of
metastable events on their outputs when CLKA and CLKB operate asynchro-
nously to one another.

FF and AF are synchronized to CLKA. EF and AE are

synchronized to CLKB. Table 4 shows the relationship of each port flag to the
level of FIFO fill.

EMPTY FLAG (

EF)

The FIFO Empty Flag is synchronized to the port clock that reads data from

its array (CLKB). When the

EF is HIGH, new data can be read to the FIFO output

EF is LOW, the FIFO is empty and attempted FIFO reads

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register

SYNCHRO-

NIZED

TO CLKB

TO CLKA

1 to X

(X+ 1) to [64 - (X + 1)]

(64 - X) to 63

NUMBER OF 36-BIT

WORDS IN THE FIFO

(1)

TABLE 4 FIFO FLAG OPERATION

are ignored. When reading the FIFO with a byte or word size on port B,

EF is

set LOW when the fourth byte or second word of the last long word is read.

The FIFO read pointer is incremented each time a new word is clocked to

its output register. The state machine that controls the

EF monitors a write-pointer

and read-pointer comparator that indicates when the FIFO memory status is
empty, empty+1, or empty+2. A word written to the FIFO can be read to the
FIFO output register in a minimum of three port B clock (CLKB) cycles.
Therefore, an

EF is LOW if a word in memory is the next data to be sent to the

FIFO output register and two CLKB cycles have not elapsed since the time the
word was written. The

EF of the FIFO is set HIGH by the second LOW-to-HIGH

transition of CLKB, and the new data word can be read to the FIFO output
register in the following cycle.

A LOW-to-HIGH transition on CLKB begins the first synchronization cycle

of a write if the clock transition occurs at time t

SKEW1

or greater after the write.

Otherwise, the subsequent CLKB cycle can be the first synchronization cycle
(see Figure 10).

FULL FLAG (

FF)

The FIFO Full Flag is synchronized to the port clock that writes data to its

array (CLKA). When the

FF is HIGH, a FIFO memory location is free to receive

new data. No memory locations are free when the

FF is LOW and attempted

writes to the FIFO are ignored.

Each time a word is written to the FIFO, its write-pointer is incremented. The

state machine that controls the

FF monitors a write-pointer and read-pointer

comparator that indicates when the FIFO memory status is full, full-1, or full-2.
From the time a word is read from the FIFO, its previous memory location is ready
to be written in a minimum of three CLKA cycles. Therefore, a

FF is LOW if less

than two CLKA cycles have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the

FF synchronizing clock

after the read sets the

FF HIGH and data can be written in the following clock cycle.

A LOW-to-HIGH transition on CLKA begins the first synchronization cycle

of a read if the clock transition occurs at time t

SKEW

or greater after the read.

Otherwise, the subsequent clock cycle can be the first synchronization cycle
(see Figure 11).

ALMOST-EMPTY FLAG (

AE)

The FIFO Almost-Empty flag is synchronized to the port clock that reads data

from its array (CLKB). The state machine that controls the

AE flag monitors a

write-pointer and read-pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-empty state is defined by the value of the Almost-Full and Almost-Empty
Offset register (X). This register is loaded with one of four preset values during
a device reset (see reset above). The

AE flag is LOW when the FIFO contains

X or less long words in memory and is HIGH when the FIFO contains (X+1)
or more long words.

Two LOW-to-HIGH transitions on the port B Clock (CLKB) are required after

a FIFO write for the

AE flag to reflect the new level of fill. Therefore, the AE flag

of a FIFO containing (X+1) or more long words remains LOW if two CLKB cycles
have not elapsed since the write that filled the memory to the (X+1) level. The
AE flag is set HIGH by the second CLKB LOW-to-HIGH transition after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH transition of CLKB
begins the first synchronization cycle if it occurs at time t

SKEW2

or greater after

the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent CLKB
cycle can be the first synchronization cycle (see Figure 12).

ALMOST FULL FLAG (

AF)

The FIFO Almost-Full flag is synchronized to the port clock that writes data

to its array (CLKA). The state machine that controls an

AF flag monitors a write-

pointer and read-pointer comparator that indicates when the FIFO memory
status is almost -full, almost- full-1, or almost-full-2. The almost-full state is defined
by the value of the Almost-Full and Almost-Empty Offset register (X). This register
is loaded with one of four preset values during a device reset (see Reset section).
The

AF flag is LOW when the FIFO contains (64-X) or more long words in

memory and is HIGH when the FIFO contains [64-(X+1)] or less long words.

Two LOW-to-HIGH transitions on the port A Clock (CLKA) are required after

a FIFO read for the

AF flag to reflect the new level of fill. Therefore, the AF flag

of a FIFO containing [64-(X+1)] or less words remains LOW if two CLKA cycles
have not elapsed since the read that reduced the number of long words in
memory to [64-(X+1)]. The

AF flag is set HIGH by the second CLKA LOW-to-

HIGH transition after the FIFO read that reduces the number of long words in
memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA begins the first
synchronization cycle if it occurs at time t

SKEW2

or greater after the read that

reduces the number of long words in memory to [64-(X+1)]. Otherwise, the
subsequent CLKA cycle can be the first synchronization cycle (see Figure 13).

MAILBOX REGISTERS

Two 36-bit bypass registers (mail1, mail2) are on the IDT72V3613 to pass

command and control information between port A and port B without putting it
in queue. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1
register when a port A write is selected by

CSA, W/RA, and ENA with MBA HIGH.

A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register
when a port B write is selected by

CSB, W/RB and ENB, and both SIZ0 and

SIZ1 are HIGH. Writing data to a mail register sets its corresponding flag (

MBF1

MBF2) LOW. Attempted writes to a mail register are ignored while its mail

flag is LOW.

When the port B data (B0-B35) outputs are active, the data on the bus comes

from the FIFO output register when either one or both SIZ1 and SIZ0 are LOW
and from the mail1 register when both SIZ1 and SIZ0 are HIGH. The Mail1
Register Flag (

MBF1) is set HIGH by a rising CLKB edge when a port B read

is selected by

CSB, W/RB, and ENB, and both SIZ1 and SIZ0 HIGH. The Mail2

MBF2) is set HIGH by a rising CLKA edge when a port A read

is selected by

CSA, W/RA, and ENA with MBA HIGH. The data in a mail register

remains intact after it is read and changes only when new data is written to the
register. See Figure 14 and 15 for relevant mail register and mail register flag
timing diagrams.

DYNAMIC BUS SIZING

The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-

bit byte format for data read from the FIFO. Word- and byte-size bus selections
can utilize the most significant bytes of the bus (Big-Endian) or least significant
bytes of the bus (Little-Endian). Port B bus-size can be changed dynamically
and synchronous to CLKB to communicate with peripherals of various bus widths.

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

The levels applied to the port B bus-size select (SIZ0, SIZ1) inputs and the

Big-Endian select (

BE) input are stored on each CLKB LOW-to-HIGH transition.

The stored port B bus-size selection is implemented by the next rising edge on
CLKB according to Figure 2.

Only 36-bit long-word data is written to or read from the FIFO memory on

the IDT72V3613. Bus-matching operations are done after data is read from the
FIFO RAM. Port B bus sizing does not apply to mail register operations.

BUS-MATCHING FIFO READS

Data is read from the FIFO RAM in 36-bit long-word increments. If a long-

word bus-size is implemented, the entire long word immediately shifts to the
FIFO output register upon a read. If byte or word size is implemented on port
B, only the first one or two bytes appear on the selected portion of the FIFO
output register, with the rest of the long word stored in auxiliary registers. In
this case, subsequent FIFO reads with the same bus-size implementation
output the rest of the long word to the FIFO output register in the order shown
by Figure 2.

Each FIFO read with a new bus-size implementation automatically unloads

data from the FIFO RAM to its output register and auxiliary registers. Therefore,
implementing a new port B bus-size and performing a FIFO read before all bytes
or words stored in the auxiliary registers have been read results in a loss of the
unread data in these registers.

When reading data from FIFO in byte or word format, the unused B0-B35

outputs are indeterminate.

BYTE SWAPPING

The byte-order arrangement of data read from the FIFO can be changed

synchronous to the rising edge of CLKB. Byte-order swapping is not available
for mail register data. Four modes of byte-order swapping (including no swap)
can be done with any data port size selection. The order of the bytes are
rearranged within the long word, but the bit order within the bytes remains
constant.

Byte arrangement is chosen by the port B Swap select (SW0, SW1) inputs

on a CLKB rising edge that reads a new long word from the FIFO. The byte
order chosen on the first byte or first word of a new long word read from the FIFO
is maintained until the entire long word is transferred, regardless of the SW0 and
SW1 states during subsequent reads. Figure 4 is an example of the byte-order
swapping available for long word reads. Performing a byte swap and bus-size
simultaneously for a FIFO read first rearranges the bytes as shown in Figure
4, then outputs the bytes as shown in Figure 2.

PORT-B MAIL REGISTER ACCESS

In addition to selecting port B bus sizes for FIFO reads, the port B bus Size

select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and
SIZ1 are HIGH, the mail1 register is accessed for a port B long-word read and
the mail2 register is accessed for a port B long-word write. The mail register is
accessed immediately and any bus-sizing operation that can be underway is
unaffected by the mail register access. After the mail register access is complete,
the previous FIFO access can resume in the next CLKB cycle. The logic diagram
in Figure 3 shows the previous bus-size selection is preserved when the mail
registers are accessed from port B. A port B bus-size is implemented on each
rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and

BE_Q.

PARITY CHECKING

The port A data inputs (A0-A35) and port B data inputs (B0-B35) each have

four parity trees to check the parity of incoming (or outgoing) data. A parity failure
on one or more bytes of the port A data bus is reported by a low level on the
port A Parity Error Flag (

PEFA). A parity failure on one or more bytes of the

port B data inputs that are valid for the bus-size implementation is reported by
a low level on the port B Parity Error Flag (

PEFB). Odd or Even parity checking

can be selected, and the Parity Error Flags can be ignored if this feature is not
desired.

Parity status is checked on each input bus according to the level of the Odd/

Even parity (ODD/

EVEN) select input. A parity error on one or more valid bytes

of a port is reported by a LOW level on the corresponding port Parity Error Flag
(

PEFA, PEFB) output. Port A bytes are arranged as A0-A8, A9-A17, A18-A26,

and A27-A35, and port B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35, and its valid bytes are those used in a port B bus size implementation.
When Odd/Even parity is selected, a port Parity Error Flag (

PEFA, PEFB) is

LOW if any byte on the port has an odd/even number of LOW levels applied
to its bits.

The four parity trees used to check the A0-A35 inputs are shared by the

mail2 register when parity generation is selected for port-A reads (PGA = HIGH).
When a port A read from the mail2 register with parity generation is selected with
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A
Parity Error Flag (

PEFA) is held HIGH regardless of the levels applied to the

A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are
shared by the mail1 register when parity generation is selected for port B reads
(PGB = HIGH). When a port B read from the mail1 register with parity generation
is selected with

CSB LOW, ENB HIGH, W/RB LOW, both SIZ0 and SIZ1 HIGH,

and PGB HIGH, the port B Parity Error Flag (

PEFB) is held HIGH regardless

of the levels applied to the B0-B35 inputs.

PARITY GENERATION

A HIGH level on the port A Parity Generate select (PGA) or port B Parity

Generate select (PGB) enables the IDT72V3613 to generate parity bits for port
reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8,
A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte used
as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35, with the most significant bit of each byte used as the parity bit. A write
to a FIFO or mail register stores the levels applied to all nine inputs of a byte
regardless of the state of the Parity Generate select (PGA, PGB) inputs. When
data is read from a port with parity generation selected, the lower eight bits of
each byte are used to generate a parity bit according to the level on the ODD/
EVEN select. The generated parity bits are substituted for the levels originally
written to the most significant bits of each byte as the word is read to the data
outputs.

Parity bits for FIFO data are generated after the data is read from the FIFO

memory and before the data is written to the output register. Therefore, the port
A Parity Generate select (PGA) and Odd/Even parity select (ODD/

EVEN) have

setup and hold time constraints to the port A Clock (CLKA) and the port B Parity
Generate select (PGB) and ODD/

EVEN select have setup and hold time

constraints to the port B Clock (CLKB). These timing constraints only apply for
a rising clock edge used to read a new long word to the FIFO output register
(see Figure 16 and 17).

The circuit used to generate parity for the mail1 data is shared by the port

B bus (B0-B35) to check parity and the circuit used to generate parity for the
mail2 data is shared by the port A bus (A0-A35) to check parity. The shared
parity trees of a port are used to generate parity bits for the data in a mail register
when the port Chip Select (

CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH,

and Write/Read select (W/

RA, W/RB) input is LOW, the mail register is selected

(MBA HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity
Generate select (PGA, PGB) is HIGH. Generating parity for mail register data
does not change the contents of the register. Parity Generation timing, when
reading from a mail register, can be found in Figure 18 and 19.

IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL TEMPERATURE RANGE

Figure 11.

Flag Timing and First Available Write when the FIFO is Full

NOTES:
1. t

SKEW1

is the minimum time between a rising CLKB edge and a rising CLKA edge for

EF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and

rising CLKA edge is less than t

SKEW1

, then the transition of

EF HIGH may occur one CLKA cycle later than shown.

2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, t

SKEW1

is referenced from the rising CLKB edge that reads the

last word or byte of the long word, respectively.

NOTES:
1. t

SKEW2

is the minimum time between a rising CLKA edge and a rising CLKB edge for

AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and

rising CLKB edge is less than t

SKEW2

, then

AE may transition HIGH one CLKB cycle later than shown.

2. FIFO write (

CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, either SIZ0 = LOW or SIZ1 = LOW).

3. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, t

SKEW2

is referenced to the last word or byte of the long word,

respectively.

Figure 12. Timing for

when the FIFO is Almost-Empty

CSB

SIZ1,
SIZ0

ENB

B0 -B35

CLKB

CLKA

CSA

A0 - A35

MBA

ENA

4661 drw 11

CLK

CLKH

CLKL

ENS

ENH

SKEW1

CLK

CLKH

CLKL

WFF

ENS

ENH

To FIFO

Previous Word in FIFO Output Register

Next Word From FIFO

LOW

HIGH

LOW

HIGH

(1)

FIFO Full

WFF

CLKA

ENA

CLKB

ENB

4661 drw 12

ENS

ENH

SKEW2

PAE

ENS

ENH

X Long Words in FIFO

(X+1) Long Words in FIFO

(1)

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