3.3 VOLT CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING
64 x 36 x 2
IDT72V3614
1
1
MAY 2003
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4663/1
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
Supports clock frequencies up to 83 MHz
Fast access times of 8 ns
Free-running CLKA and CLKB can be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single
clock edge is permitted)
Mailbox bypass Register for each FIFO
Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
Selection of Big- or Little-Endian format for word and byte bus
sizes
Three modes of byte-order swapping on port B
Programmable Almost-Full and Almost-Empty flags
Microprocessor interface control logic
EFA , FFA , AEA , and AFA flags synchronized by CLKA
EFB , FFB , AEB , and AFB flags synchronized by CLKB
Passive parity checking on each port
Parity generation can be selected for each port
Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723614
Industrial temperature range (40
C to +85C) is available
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Input
Register
Output
Register
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
Device
Control
RST
CLKB
CSB
W/
RB
ENB
Port-B
Control
Logic
MBF1
4663 drw 01
Mail 2
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
Parity
Gen/Check
A
0
- A
35
36
RAM
ARRAY
64 x 36
Parity
Generation
Parity
Gen/Check
Programmable Flag
Offset Register
Status Flag
Logic
Input
Register
Output
Register
RAM
ARRAY
64 x 36
Parity
Generation
Read
Pointer
PEFB
PGB
EFB
AEB
FFB
AFB
ODD/
EVEN
FFA
AFA
FS0
FS1
EFA
AEA
PGA
PEFA
MBF2
Write
Pointer
FIFO2
FIFO1
36
36
BE
SIZ0
SIZ1
SW0
SW1
Bus-Matching &
Byte Swapping
B
0
-B
35
Bus-Matching &
Byte Swapping
2
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
GND
AEB
EFB
B
0
B
1
B
2
GND
B
3
B
4
B
5
B
6
V
CC
B
7
B
8
B
9
GND
B
10
B
11
V
CC
B
12
B
13
B
14
GND
B
15
B
16
B
17
B
18
B
19
B
20
GND
B
21
B
22
B
23
GND
AEA
EFA
A
0
A
1
A
2
GND
A
3
A
4
A
5
A
6
V
CC
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
13
A
14
GND
A
15
A
16
A
17
A
18
A
19
A
20
GND
A
21
A
22
A
23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
4663 drw 02
117
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
V
CC
V
CC
A
24
A
25
A
26
A
27
GND
A
28
A
29
V
CC
A
30
A
31
A
32
GND
A
33
A
34
A
35
GND
B
35
B
34
B
33
GND
B
32
B
31
B
30
V
CC
B
29
B
28
B
27
GND
B
26
B
25
B
24
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
AFB
AFA
FFA
CSA ENA CLKA W/
R
A
V
CC
PGA
FS
0
ODD/
EVEN
FS
1
PEFA
MBF2
RST
BE
GND
SW1
SW0
SIZ1
MBF1 GND PEFB
V
CC
W/
R
B
CLKB
ENB
CSB FFB
GND
MBA
SIZ0
PGB
DESCRIPTION:
The IDT72V3614 is a pin and functionally compatible version of the
IDT723614, designed to run off a 3.3V supply for exceptionally low power
consumption. This device is monolithic, high-speed, low-power CMOS
bidirectional clocked FIFO memory. It supports clock frequencies up to 83 MHz
and has read access times as fast as 8 ns. The FIFO operates in IDT Standard
mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip
buffer data in opposite directions. Each FIFO has flags to indicate empty and
full conditions and two programmable flags (Almost-Full and Almost-Empty) to
PIN CONFIGURATIONS
indicate when a selected number of words is stored in memory. FIFO data on
port B can be input and output in 36-bit, 18-bit, and 9-bit formats with a choice
of Big- or Little-Endian configurations. Three modes of byte-order swapping are
possible with any bus size selection. Communication between each port can
bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored. Parity is checked passively on
each port and may be ignored if not desired. Parity generation can be selected
for data read from each port. Two or more devices can be used in parallel to
create wider data paths.
NOTES:
1. NC - No internal connection.
2. Uses Yamaichi socket IC51-1324-828.
*
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP
(2)
(PQ132-1, order code: PQF)
TOP VIEW
*
3
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TQFP (PN120-1, order code: PF)
TOP VIEW
PIN CONFIGURATIONS (CONTINUED)
DESCRIPTION (CONTINUED):
This device is a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the LOW-
to-HIGH transition of a continuous (free-running) port clock by enable signals.
The clocks for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are arranged to provide
a simple bidirectional interface between microprocessors and/or buses con-
trolled by a synchronous interface.
The Full Flag (
FFA, FFB) and Almost-Full flag (AFA, AFB) of a FIFO are
two-stage synchronized to the port clock that writes data to its array. The Empty
Flag (
EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage
synchronized to the port clock that reads data from its array.
The IDT72V3614 is characterized for operation from 0
C to 70C. Industrial
temperature range (40
C to +85C) is available by special order. This device
is fabricated using IDT's high speed, submicron CMOS technology.
B
22
B
21
GND
B
20
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
B
9
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
B
2
B
1
B
0
EFB
AEB
AFB
A
23
A
22
A
21
GND
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
GND
A
9
A
8
A
7
V
CC
A
6
A
5
A
4
A
3
GND
A
2
A
1
A
0
EFA
AEA
4663 drw 03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
AFA FFA
CSA ENA
CLKA
W/
R
A
V
CC
PGA
PEFA MBF
2
MBA
FS
1
FS
0
ODD/
EVEN
RST GND
BE
SW1
SW0
SIZ1 SIZ0
MBF
1
PEFB PGB
V
CC
W/
R
B
CLKB
ENB CSB
FFB
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45 46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
B
23
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
34
A
35
B
35
GND
B
34
B
33
B
32
B
30
B
31
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
A
32
A
33
4
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bit bidirectional data port for side A.
AEA
Port A Almost-
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of 36-bit words in
Empty Flag
(Port A) FIFO2 is less than or equal to the value in the offset register, X.
AEB
Port B Almost-
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of 36-bit words in
Empty Flag
(Port B) FIFO1 is less than or equal to the value in the offset register, X.
AFA
Port A Almost-Full
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty
Flag
(Port A) locations in FIFO1 is less than or equal to the value in the offset register, X.
AFB
Port B Almost-Full
O
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of 36-bit empty
Flag
(Port B) locations in FIFO2 is less than or equal to the value in the offset register, X.
B0-B35
Port B Data
I/O
36-bit bidirectional data port for side B.
BE
Big-Endian Select
I
Selects the bytes on port B used during byte or word data transfer. A LOW
on BE selects the most significant
bytes on B0-B35 for use, and a HIGH selects the least significant bytes.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB.
EFA, FFA, AFA, and AEA are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or
coincident to CLKA. Port B byte swapping and data port sizing operations are also synchronous to the
LOW-to-HIGH transition of CLKB.
EFB, FFB, AFB, and AEB are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA
Port A Chip Select
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The
A0-A35 outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip Select
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
B0-B35 outputs are in the high-impedance state when
CSB is HIGH.
EFA
Port A Empty Flag
O
EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA isLOW, FIFO2 is empty, and
(Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register when
EFA is
HIGH.
EFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after data is loaded into empty FIFO2 memory.
EFB
Port B Empty Flag
O
EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is empty, and
(Port B) and reads from its memory are disabled. Data can be read from FIFO1 to the output register when
EFB is
HIGH.
EFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after data is loaded into empty FIFO1 memory.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFA
Port A Full Flag
O
FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full, and writes
(Port A) to its memory are disabled.
FFA is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after reset.
FFB
Port B Full Flag
O
FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is LOW, FIFO2 is full, and writes
(Port B) writes to its memory are disabled.
FFB is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKB after reset.
FS1, FS0 Flag-Offset
I
The LOW-to-HIGH transition of
RST latches the values of FS0 and FS1, which selects one of four preset
Selects
values for the Almost-Full flag and Almost-Empty flag offset.
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35
Select
outputs are active, a HIGH level on MBA selects data from the mail2 register for output, and a LOW level
selects FIFO2 output register data for output.
MBF1
Mail1 Register
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
Flag
mail1 register are inhibited while
MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of
CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH.
MBF1 is set HIGH when the
device is reset.
PIN DESCRIPTION
5
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (Continued)
Symbol
Name
I/O
Description
MBF2
Mail2 Register
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
Flag
mail2 register are inhibited while
MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA
when a port A read is selected and MBA is HIGH.
MBF2 is set HIGH when the device is reset.
ODD/
Odd/Even
I
Odd parity is checked on each port when ODD/
EVEN is HIGH, and even parity is checked when
EVEN
Parity Select
ODD/
EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is
enabled for a read operation.
PEFA
Port A Parity
O
When any byte applied to terminals A0-A35 fails parity,
PEFA is LOW. Bytes are organized as A0-A8,
Error Flag
(Port A) A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type
of parity checked is determined by the state of the ODD/
EVEN input.
The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity
generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by having W/
RA
LOW, MBA HIGH, and PGA HIGH, the
PEFA flag is forced HIGH regardless of the A0-A35 inputs.
PEFB
Port B Parity
O
When any valid byte applied to terminals B0-B35 fails parity,
PEFB is LOW. Bytes are organized as B0-B8,
Error Flag
(Port B) B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity bit. A byte is valid
when it is used by the bus size selected for Port B. The type of parity checked is determined by the state of
the ODD/
EVEN input.
The parity trees used to check the B0-B35 inputs are shared by the mail 1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having W/
RB
LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the
PEFB flag is forced HIGH regardless of the state of the B0-
B35 inputs.
PGA
Port A Parity
I
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is selected
Generation
by the state of the ODD/
EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.
PGB
Port B Parity
I
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected
Generation
by the state of the ODD/
EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The
generated parity bits are output in the most significant bit of each byte.
RST
Reset
I
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while
RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA,
AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0
inputs to select Almost-Full and Almost-Empty flag offsets.
SIZ0, SIZ1 Port B Bus
I
A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and
BE, and the following LOW-to-HIGH
Size Selects
(Port B) transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be long word,
word or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit write or
read.
SW0, SW1 Port B Byte
I
At the beginning of each long word transfer, one of four modes of byte-order swapping is selected by SW0
Swap Select
(Port B) and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping
is possible with any bus-size selection.
W/
RA
Port A Write/
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
Read Select
transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/
RA is HIGH.
W/
RB
Port B Write/
I
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
Read Select
transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/
RB is HIGH.
6
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)
(1)
Symbol
Rating
Commercial
Unit
V
CC
Supply Voltage Range
0.5 to +4.6
V
V
I
(2)
Input Voltage Range
0.5 to V
CC
+0.5
V
V
O
(2)
Output Voltage Range
0.5 to V
CC
+0.5
V
I
IK
Input Clamp Current, (V
I
< 0 or V
I
> V
CC
)
20
mA
I
OK
Output Clamp Current, (V
O
< 0 or V
O
> V
CC
)
50
mA
I
OUT
Continuous Output Current, (V
O
= 0 to V
CC
)
50
mA
I
CC
Continuous Current Through V
CC
or GND
500
mA
T
STG
Storage Temperature Range
65 to 150
C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at
these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
(1)
Supply Voltage
3.0
3.3
3.6
V
V
IH
HIGH Level Input Voltage
2
--
V
CC
+0.5
V
V
IL
LOW-Level Input Voltage
--
0.8
V
I
OH
HIGH-Level Output Current
--
4
mA
I
OL
LOW-Level Output Current
--
8
mA
T
A
Operating Free-air
0
--
70
C
Temperature
RECOMMENDED OPERATING
CONDITIONS
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
NOTES:
1. All typical values are at V
CC
= 3.3V, T
A
= 25
C.
2. For additional I
CC
information, see Figure 1, Typical Characteristics: Supply Current (I
CC
) vs. Clock Frequency (f
S
).
IDT72V3614
Commercial
t
CLK
= 12, 15, 20 ns
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
OH
Output Logic "1" Voltage
V
CC
= 3.0V,
I
OH
= 4 mA
2.4
--
--
V
V
OL
Output Logic "0" Voltage
V
CC
= 3.0V,
I
OL
= 8 mA
--
--
0.5
V
I
LI
Input Leakage Current (Any Input)
V
CC
= 3.6V,
V
I
= V
CC
or 0
--
--
5
A
I
LO
Output Leakage Current
V
CC
= 3.6V,
V
O
= V
CC
or 0
--
--
5
A
I
CC
(2)
Standby Current
V
CC
= 3.6V,
V
I
= V
CC
- 0.2V or 0
--
--
500
A
C
IN
Input Capacitance
V
I
= 0,
f = 1 MHz
--
4
--
pF
C
OUT
Output Capacitance
V
O
= 0,
f = 1 MHZ
--
8
--
pF
NOTE:
1. For 12ns (83MHz operation), Vcc=3.3V +/-0.15V, JEDEC JESD8-A compliant
7
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The I
CC
(f)
current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3614 with CLKA and CLKB set
to f
S
. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize
the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With I
CC(f
) taken from Figure 1, the maximum power dissipation (P
T
) of the IDT72V3614 can be calculated by:
P
T
= V
CC
x I
CC(f)
+
(C
L
x V
OH
2
x
f
o
)
N
where:
N
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus-size)
C
L
=
output capacitance load
f
o
=
switching frequency of an output
V
OH
=
output high level voltage
When no reads or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency f
s
is calculated
by:
P
T
=V
CC
x f
S x
0.025 mA/MHz
Figure 1. Typical Characteristics: Supply Current (I
CC
) vs. Clock Frequency (f
S
)
0
10
20
30
40
50
60
70
0
25
50
75
100
125
150
V
CC
= 3.3V
f
S
Clock Frequency MHz
I
CC(f)
Supply Current
mA
f
data
= 1/2 f
S
T
A
= 25
C
C
L
= 0 pF
V
CC
= 3.0V
4663 drw 04
V
CC
= 3.6V
80
90
175
8
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3614L12
IDT72V3614L15
IDT72V3614L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
S
Clock Frequency, CLKA or CLKB
83
66.7
50
MHz
t
CLK
Clock Cycle Time, CLKA or CLKB
12
15
20
ns
t
CLKH
Pulse Duration, CLKA and CLKB HIGH
5
6
8
ns
t
CLKL
Pulse Duration, CLKA and CLKB LOW
5
6
8
ns
t
DS
Setup Time, A0-A35 before CLKA
and B0-B35 before
4
4
5
ns
CLKB
t
ENS
Setup Time,
CSA, W/RA, ENA and MBA before CLKA
;
3.5
5
5
ns
CSB,W/RB and ENB before CLKB
t
SZS
Setup Time, SIZ0, SIZ1,and
BE before CLKB
3.5
4
5
ns
t
SWS
Setup Time, SW0 and SW1 before CLKB
4
6
7
ns
t
PGS
Setup Time, ODD/
EVEN and PGA before CLKA
;
3
4
5
ns
ODD/
EVEN and PGB before CLKB
(1)
t
RSTS
Setup Time,
RST LOW before CLKA
or CLKB
(2)
4
5
6
ns
t
FSS
Setup Time, FS0 and FS1 before
RST HIGH
4
5
6
ns
t
DH
Hold Time, A0-A35 after CLKA
and B0-B35 after CLKB
0.5
1
1
ns
t
ENH
Hold Time,
CSA, W/RA, ENA and MBA after CLKA
; CSB,
0.5
1
1
ns
W/
RB, and ENB after CLKB
t
SZH
Hold Time, SIZ0, SIZ1, and
BE after CLKB
1
1
2
ns
t
SWH
Hold Time, SW0 and SW1 after CLKB
1
1
2
ns
t
PGH
Hold Time, ODD/
EVEN and PGA after CLKA
; ODD/EVEN
0
0
0
ns
and PGB after CLKB
(1)
t
RSTH
Hold Time,
RST LOW after CLKA
or CLKB
(2)
4
5
6
ns
t
FSH
Hold Time, FS0 and FS1 after
RST HIGH
4
4
4
ns
t
SKEW1
(3)
Skew Time, between CLKA
and CLKB for EFA, EFB,
5.5
8
8
ns
FFA, and FFB
t
SKEW2
(3,4)
Skew Time, between CLKA
and CLKB for AEA, AEB,
14
14
16
ns
AFA, and AFB
NOTES:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
Commercial: Vcc=3.3V
0.30V; for 12ns (83MHz) operation, Vcc=3.3V 0.15V; T
A
= 0
C to +70
C; JEDEC JESD8-A compliant
9
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C
L
= 30
P
F
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when a new port B bus size is implemented by the rising CLKB edge.
4. Only applies when reading data from a mail register.
IDT72V3614L12
IDT72V3614L15
IDT72V3614L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
A
Access Time, CLKA
to A0-A35 and CLKB to B0-B35
1
8
2
10
2
12
ns
t
WFF
Propagation Delay Time, CLKA
to FFA and CLKB to FFB
1
8
2
10
2
12
ns
t
REF
Propagation Delay Time, CLKA
to EFA and and CLKB
1
8
2
10
2
12
ns
to
EFB
t
PAE
Propagation Delay Time, CLKA
to AEA and CLKB to AEB
1
8
2
10
2
12
ns
t
PAF
Propagation Delay Time, CLKA
to AFA and CLKB to AFB
1
8
2
10
2
12
ns
t
PMF
Propagation Delay Time, CLKA
to MBF1 LOW or MBF2
1
8
1
9
1
12
ns
HIGH and CLKB
to MBF2 LOW or MBF1 HIGH
t
PMR
Propagation Delay Time, CLKA
to B0-B35
(1)
2
8
2
10
2
12
ns
and CLKB
to A0-A35
(2)
t
PPE
(3)
Propagation delay time, CLKB
to PEFB
2
8
2
10
2
12
ns
t
MDV
Propagation Delay Time, MBA to A0-A35 valid and SIZ1,
1
8
1
10
1
11. 5
ns
SIZ0 to B0-B35 valid
t
PDPE
Propagation Delay Time, A0-A35 valid to
PEFA valid;
2
8
2
10
2
11
ns
B0-B35 valid to
PEFB valid
t
POPE
Propagation Delay Time, ODD/
EVEN to PEFA and PEFB
2
8
2
10
2
12
ns
t
POPB
(4)
Propagation Delay Time, ODD/
EVEN to parity bits (A8, A17,
2
8
2
10
2
12
ns
A26, A35) and (B8, B17, B26, B35)
t
PEPE
Propagation Delay Time,
CSA, ENA,W/RA, MBA, or PGA to
1
8
1
10
1
12
ns
PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB
t
PEPB
(4)
Propagation Delay Time,
CSA, ENA, W/RA, MBA, or PGA to
2
8
2
10
2
12
ns
parity bits (A8, A17, A26, A35);
CSB, ENB, W/RB,SIZ1,
SIZ0, or PGB to parity bits (B8, B17, B26, B35)
t
RSF
Propagation Delay Time,
RST to (MBF1, MBF2) HIGH
1
10
1
15
1
20
ns
t
EN
Enable Time,
CSA and W/RA LOW to A0-A35 active and CSB
2
6
2
10
2
12
ns
LOW and
W/RB HIGH to B0-B35 active
t
DIS
Disable Time,
CSA or W/RA HIGH to A0-A35 at high-
1
6
1
8
1
9
ns
impedance and
CSB HIGH or W/RB LOW to B0-B35 at
high-impedance
Commercial: Vcc=3.3V
0.30V; for 12ns (83MHz) operation, Vcc=3.3V 0.15V; T
A
= 0
C to +70
C; JEDEC JESD8-A compliant
10
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
output register. When the Empty Flag is LOW, the FIFO is empty and attempted
FIFO reads are ignored. When reading FIFO1 with a byte or word size on port
B,
EFB is set LOW when the fourth byte or second word of the last long word
is read.
The read pointer of a FIFO is incremented each time a new word is clocked
to the output register. The state machine that controls an Empty Flag monitors
a write-pointer and read-pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2. A word written to a FIFO can
be read to the FIFO output register in a minimum of three cycles of the Empty
Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and two cycles of the port
clock that reads data from the FIFO have not elapsed since the time the word
was written. The Empty Flag of the FIFO is set HIGH by the second LOW-to-
HIGH transition of the synchronizing clock, and the new data word can be read
to the FIFO output register in the following cycle.
A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins the
first synchronization cycle of a write if the clock transition occurs at time t
SKEW1
or greater after the write. Otherwise, the subsequent clock cycle can be the first
synchronization cycle (see Figure 14 and 15).
FULL FLAG (
FFA, FFB)
The Full Flag of a FIFO is synchronized to the port clock that writes data to
its array. When the Full Flag is HIGH, a memory location is free in the FIFO to
receive new data. No memory locations are free when the full flag is LOW and
attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented. The
state machine that controls a Full Flag monitors a write-pointer and read-pointer
comparator that indicates when the FIFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, the previous memory location is ready
to be written in a minimum of three cycles of the Full Flag synchronizing clock.
Therefore, a Full Flag is LOW if less than two cycles of the Full Flag synchronizing
clock have elapsed since the next memory write location has been read. The
second LOW-to-HIGH transition on the Full Flag synchronization clock after the
read sets the Full Flag HIGH and the data can be written in the following clock
cycle.
A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the first
synchronization cycle of a read if the clock transition occurs at time t
SKEW1
or
greater after the read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle (see Figure 16 and 17).
ALMOST-EMPTY FLAGS (
AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array. The state machine that controls an Almost-Empty flag monitors
a write-pointer and a read-pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-empty state is defined by the value of the Almost-Full and Almost-Empty
Offset register (X). This register is loaded with one of four preset values during
a device reset (see Reset section). An Almost-Empty flag is LOW when the FIFO
contains X or less long words in memory and is HIGH when the FIFO contains
(X+1) or more long words.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock
are required after a FIFO write for the Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more long
words remains LOW if two cycles of the synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An Almost-Empty flag
is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock
after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition
of an Almost-Empty flag synchronizing clock begins the first synchronization
SIGNAL DESCRIPTIONS
RESET
The IDT72V3614 is reset by taking the Reset (
RST) input LOW for at least
four port A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH transitions.
The Reset input can switch asynchronously to the clocks. A device reset
initializes the internal read and write pointers of each FIFO and forces the Full
Flags (
FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW, the Almost-Empty
flags (
AEA, AEB) LOW and the Almost-Full flags (AFA, AFB) HIGH. A reset
also forces the Mailbox Flags (
MBF1, MBF2) HIGH. After a reset, FFA is set
HIGH after two LOW-to-HIGH transitions of CLKA and
FFB is set HIGH after
two LOW-to-HIGH transitions of CLKB. The device must be reset after power
up before data is written to its memory.
A LOW-to-HIGH transition on the
RST input loads the Almost-Full and
Almost-Empty Offset register (X) with the values selected by the Flag Select
(FS0, FS1) inputs. The values that can be loaded into the registers are shown
in Table 1. For the relevant Reset and preset value loading timing diagram, see
Figure 5.
FIFO WRITE/READ OPERATION
The state of port A data A0-A35 outputs is controlled by the port A Chip Select
(
CSA) and the port A Write/Read select (W/RA). The A0-A35 outputs are in
the high-impedance state when either
CSA or W/RA is HIGH. The A0-A35
outputs are active when both
CSA and W/RA are LOW. Data is loaded into FIFO1
from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when
CSA is LOW,
W/
RA is HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH. Data is read from
FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when
CSA
is LOW, W/
RA is LOW, ENA is HIGH, MBA is LOW, and EFA is HIGH (see Table
2). Port A read and write timing diagrams can be found in Figure 6 and 15.
The port B control signals are identical to those of port A. The state of the
port B data (B0-B35) outputs is controlled by the port B Chip Select (
CSB) and
the port B Write/Read select (W/
RB). The B0-B35 outputs are in the high-
impedance state when either
CSB or W/RB is HIGH. The B0-B35 outputs are
active when both
CSB and W/RB are LOW. Data is loaded into FIFO2 from the
B0-B35 inputs on a LOW-to-HIGH transition of CLKB when
CSB is LOW, W/
RB is HIGH, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW. Data
is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB
when
CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0
or SIZ1 is LOW (see Table 3). Port B read and write timing diagrams together
with Bus-Matching, byte-swapping and Endian select can be found in Figures
7 to 12.
The setup and hold time constraints to the port clocks for the port Chip Selects
(
CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write
and read operations and are not related to high-impedance control of the data
outputs. If a port enable is LOW during a clock cycle, the port Chip Select and
Write/Read select can change states during the setup and hold time window of
the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through two flip-flop stages. This
is done to improve flag reliability by reducing the probability of metastable events
on the output when CLKA and CLKB operate asynchronously to one another.
EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and
AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each
port flag to FIFO1 and FIFO2.
EMPTY FLAGS (
EFA, EFB)
The Empty Flag of a FIFO is synchronized to the port clock that reads data
from its array. When the Empty Flag is HIGH, new data can be read to the FIFO
11
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CSB
W/
RB
ENB
SIZ1, SIZ0
CLKB
Data B (B0-B35) I/O
Port Functions
H
X
X
X
X
Input
None
L
H
L
X
X
Input
None
L
H
H
One, both LOW
Input
FIFO2 Write
L
H
H
Both HIGH
Input
Mail2 Write
L
L
L
One, both LOW
X
Output
None
L
L
H
One, both LOW
Output
FIFO1 read
L
L
L
Both HIGH
X
Output
None
L
L
H
Both HIGH
Output
Mail1 Read (Set
MBF1 HIGH)
TABLE 3 PORT-B ENABLE FUNCTION TABLE
CSA
W/
RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Functions
H
X
X
X
X
Input
None
L
H
L
X
X
Input
None
L
H
H
L
Input
FIFO1 Write
L
H
H
H
Input
Mail1 Write
L
L
L
L
X
Output
None
L
L
H
L
Output
FIFO2 Read
L
L
L
H
X
Output
None
L
L
H
H
Output
Mail2 Read (Set
MBF2 HIGH)
TABLE 2 PORT-A ENABLE FUNCTION TABLE
ALMOST-FULL AND
FS1
FS0
RST
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H
H
16
H
L
12
L
H
8
L
L
4
TABLE 1 FLAG PROGRAMMING
Synchronized
Synchronized
Number of 36-Bit
to CLKB
to CLKA
Words in the FIFO1
(1)
EFB
AEB
AFA
FFA
0
L
L
H
H
1 to X
H
L
H
H
(X+1) to [64-(X+1)]
H
H
H
H
(64-X) to 63
H
H
L
H
64
H
H
L
L
TABLE 4 FIFO1 FLAG OPERATION
Synchronized
Synchronized
Number of 36-Bit
to CLKA
to CLKB
Words in the FIFO2
(1)
EFA
AEA
AFB
FFB
0
L
L
H
H
1 to X
H
L
H
H
(X+1) to [64-(X+1)]
H
H
H
H
(64-X) to 63
H
H
L
H
64
H
H
L
L
TABLE 5 FIFO2 FLAG OPERATION
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.
12
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
The levels applied to the port B bus Size select (SIZ0, SIZ1) inputs and the
Big-Endian select (
BE) input are stored on each CLKB LOW-to-HIGH transition.
The stored port B bus size selection is implemented by the next rising edge on
CLKB according to Figure 2.
Only 36-bit long-word data is written to or read from the two FIFO memories
on the IDT72V3614. Bus-matching operations are done after data is read from
the FIFO1 RAM and before data is written to the FIFO2 RAM. Port B bus sizing
does not apply to mail register operations.
BUS-MATCHING FIFO1 READS
Data is read from the FIFO1 RAM in 36-bit long word increments. If a long
word bus size is implemented, the entire long word immediately shifts to the
FIFO1 output register. If byte or word size is implemented on port B, only the
first one or two bytes appear on the selected portion of the FIFO1 output register,
with the rest of the long word stored in auxiliary registers. In this case, subsequent
FIFO1 reads with the same bus-size implementation output the rest of the long
word to the FIFO1 output register in the order shown by Figure 2.
Each FIFO1 read with a new bus-size implementation automatically unloads
data from the FIFO1 RAM to its output register and auxiliary registers. Therefore,
implementing a new port B bus size and performing a FIFO1 read before all bytes
or words stored in the auxiliary registers have been read results in a loss of the
unread long word data.
When reading data from FIFO1 in byte or word format, the unused B0-B35
outputs are indeterminate.
BUS-MATCHING FIFO2 WRITES
Data is written to the FIFO2 RAM in 36-bit long word increments. FIFO2
writes, with a long-word bus size, immediately store each long word in FIFO2
RAM. Data written to FIFO2 with a byte or word bus size stores the initial bytes
or words in auxiliary registers. The CLKB rising edge that writes the fourth byte
or the second word of long word to FIFO2 also stores the entire long word in
FIFO2 RAM. The bytes are arranged in the manner shown in Figure 2.
Each FIFO2 write with a new bus-size implementation resets the state
machine that controls the data flow from the auxiliary registers to the FIFO2 RAM.
Therefore, implementing a new bus size and performing a FIFO2 write before
bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM
results in a loss of data.
When writing data to FIFO2 in byte or word format, the unused B0-B35 inputs
are don't care
(1)
inputs.
PORT-B MAIL REGISTER ACCESS
In addition to selecting port-B bus sizes for FIFO reads and writes, the port
B bus Size select (SIZ0, SIZ1) inputs also access the mail registers. When both
SIZ0 and SIZ1 are HIGH, the mail1 register is accessed for a port B long word
read and the mail2 register is accessed for a port B long word write. The mail
register is accessed immediately and any bus-sizing operation that may be
underway is unaffected by the mail register access. After the mail register access
is complete, the previous FIFO access can resume in the next CLKB cycle. The
logic diagram in Figure 3 shows the previous bus-size selection is preserved
when the mail registers are accessed from port B. A port B bus size is
implemented on each rising CLKB edge according to the states of SIZ0_Q,
SIZ1_Q, and
BE_Q.
BYTE SWAPPING
The byte-order arrangement of data read from FIFO1 or data written to
FIFO2 can be changed synchronous to the rising edge of CLKB. Byte-order
swapping is not available for mail register data. Four modes of byte-order
swapping (including no swap) can be done with any data port size selection.
cycle if it occurs at time t
SKEW2
or greater after the write that fills the FIFO to (X+1)
long words. Otherwise, the subsequent synchronizing clock cycle can be the
first synchronization cycle (see Figure 18 and 19).
ALMOST FULL FLAGS (
AFA, AFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors
a write-pointer and read-pointer comparator that indicates when the FIFO
memory status is almost full, almost full-1, or almost full-2. The almost-full state
is defined by the value of the Almost-Full and Almost-Empty Offset register (X).
This register is loaded with one of four preset values during a device reset (see
Reset section). An Almost-Full flag is LOW when the FIFO contains (64-X) or
more long words in memory and is HIGH when the FIFO contains [64-(X+1)]
or less long words.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are
required after a FIFO read for the Almost-Full flag to reflect the new level of fill.
Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less words
remains LOW if two cycles of the synchronizing clock have not elapsed since
the read that reduced the number of long words in memory to [64-(X+1)]. An
Almost-Full flag is set HIGH by the second LOW-to-HIGH transition of the
synchronizing clock after the FIFO read that reduces the number of long words
in memory to [64-(X+1)]. A LOW-to-HIGH transition of an Almost-Full flag
synchronizing clock begins the first synchronization cycle if it occurs at time
t
SKEW2
or greater after the read that reduces the number of long words in
memory to [64-(X+1)]. Otherwise, the subsequent synchronizing clock cycle
can be the first synchronization cycle (see Figure 20 and 21).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The Mailbox
Select (MBA, SIZ0, SIZ1) inputs choose between a mail register and a FIFO
for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes
A0-A35 data to the mail1 register when a port A write is selected by
CSA, W/
RA, and ENA with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-
B35 data to the mail2 register when a port B write is selected by
CSB, W/RB,
and ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail register sets
the corresponding flag (
MBF1 or MBF2) LOW. Attempted writes to a mail register
are ignored while the mail flag is LOW.
When the port A data outputs (A0-A35) are active, the data on the bus comes
from the FIFO2 output register when MBA is LOW and from the mail2 register
when MBA is HIGH. When the port B data outputs (B0-B35) are active, the data
on the bus comes from the FIFO1 output register when either one or both SIZ1
and SIZ0 are LOW and from the mail2 register when both SIZ1 and SIZ0 are
HIGH. The Mail1 Register Flag (
MBF1) is set HIGH by a rising CLKB edge
when a port B read is selected by
CSB, W/RB, and ENB with both SIZ1 and
SIZ0 HIGH. The Mail2 Register Flag (
MBF2) is set HIGH by a LOW-to-HIGH
transition on CLKA when port A read is selected by
CSA, W/RA, and ENA and
MBA is HIGH. The data in the mail register remains intact after it is read and
changes only when new data is written to the register. Relevant mail register
and Mail Register Flag timing diagrams can be found in Figure 22 and Figure 23.
DYNAMIC BUS SIZING
The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-
bit byte format for data read from FIFO1 or written to FIFO2. Word- and byte-
size bus selections can utilize the most significant bytes of the bus (Big-Endian)
or least significant bytes of the bus (Little-Endian). Port B bus size can be changed
dynamically and synchronous to CLKB to communicate with peripherals of
various bus widths.
13
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
The order of the bytes are rearranged within the long word, but the bit order
within the bytes remains constant.
Byte arrangement is chosen by the port B Swap select (SW0, SW1) inputs
on a CLKB rising edge that reads a new long word from FIFO1 or writes a new
long word to FIFO2. The byte order chosen on the first byte or first word of a
new long word read from FIFO1 or written to FIFO2 is maintained until the entire
long word is transferred, regardless of the SW0 and SW1 states during
subsequent writes or reads. Figure 4 is an example of the byte-order swapping
available for long words. Performing a byte swap and bus size simultaneously
for a FIFO1 read first rearranges the bytes as shown in Figure 4, then outputs
the bytes as shown in Figure 2. Simultaneous bus-sizing and byte-swapping
operations for FIFO2 writes, first loads the data according to Figure 2, then
swaps the bytes as shown in Figure 4 when the long word is loaded to FIFO2
RAM.
PARITY CHECKING
The port A inputs (A0-A35) and port B inputs (B0-B35) each have four parity
trees to check the parity of incoming (or outgoing) data. A parity failure on one
or more bytes of the port A data bus is reported by a LOW level on the port Parity
Error Flag (
PEFA). A parity failure on one or more bytes of the port B data input
that are valid for the bus-size implementation is reported by a LOW level on the
port B Parity Error Flag (
PEFB). Odd or Even parity checking can be selected,
and the Parity Error Flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the Odd/
Even parity (ODD/
EVEN) select input. A parity error on one or more valid bytes
of a port is reported by a LOW level on the corresponding port Parity Error Flag
(
PEFA, PEFB) output. Port A bytes are arranged as A0-A8, A9-A17, A18-A26,
and A27-A35. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35, and its valid bytes are those used in a port B bus-size implementation.
When Odd/Even parity is selected, a port Parity Error Flag (
PEFA, PEFB) is
LOW if any byte on the port has an odd/even number of LOW levels applied
to the bits.
The four parity trees used to check the A0-A35 inputs are shared by the mail2
register when parity generation is selected for port A reads (PGA = HIGH).
When a port A read from the mail2 register with parity generation is selected with
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A
Parity Error Flag (
PEFA) is held HIGH regardless of the levels applied to the
A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are
shared by the mail1 register when parity generation is selected for port B reads
(PGB = HIGH). When a port B read from the mail1 register with parity generation
is selected with
CSB LOW, ENB HIGH, W/RB LOW, both SIZ0 and SIZ1 HIGH,
and PGB HIGH, the port B Parity Error Flag (
PEFB) is held HIGH regardless
of the levels applied to the B0-B35 inputs (see Figure 24 and 25).
PARITY GENERATION
A HIGH level on the port A Parity Generate select (PGA) or port B Parity
Generate select (PGB) enables the IDT72V3614 to generate parity bits for port
reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8,
A9-A17, A18-26, and A27-A35, with the most significant bit of each byte used
as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35, with the most significant bit of each byte used as the parity bit. A write
to a FIFO or mail register stores the levels applied to all nine inputs of a byte
regardless of the state of the Parity Generate select (PGA, PGB) inputs. When
data is read from a port with parity generation selected, the lower eight bits of
each byte are used to generate a parity bit according to the level on the ODD/
EVEN select. The generated parity bits are substituted for the levels originally
written to the most significant bits of each byte as the word is read to the data
outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and
before the data is written to the output register. Therefore, the port A Parity
Generate select (PGA) and Odd/Even parity select (ODD/
EVEN) have setup
and hold time constraints to the port A Clock (CLKA) and the port B Parity
Generate select (PGB) and ODD/
EVEN have setup and hold-time constraints
to the port B Clock (CLKB). These timing constraints only apply for a rising clock
edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port
B bus (B0-B35) to check parity and the circuit used to generate parity for the
mail2 data is shared by the port A bus (A0-A35) to check parity. The shared
parity trees of a port are used to generate parity bits for the data in a mail register
when the port Chip Select (
CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH,
Write/Read select (W/
RA, W/RB) input is LOW, the Mail register is selected (MBA
is HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity
Generate select (PGA, PGB) is HIGH. Generating parity for mail register data
does not change the contents of the register (see Figure 26 and 27).
14
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Figure 2. Dynamic Bus Sizing
A35
A27 A26A18 A1A9 A8A0
B35
B27 B26B18 B17B9 B8B0
A
A
B
B
C
C
(a) LONG WORD SIZE
(b) WORD SIZE
BIG-ENDIAN
(c) WORD SIZE
LITTLE-ENDIAN
(d) BYTE SIZE
BIG-ENDIAN
Write to FIFO1/
Read From FIFO2
Read from FIFO1/
Write to FIFO2
1st: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
1st: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
1st: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
3rd: Read from FIFO1/
Write to FIFO2
4th: Read from FIFO1/
Write to FIFO2
BE SIZ1 SIZ0
BE SIZ1 SIZ0
BE SIZ1 SIZ0
BE SIZ1 SIZ0
L L H
H L H
L H L
X L L
BYTE ORDER ON PORT A:
4663 drw fig 01
D
D
A
B
C
D
C
D
A
B
A
B
C
D
BYTE ORDER ON PORT B:
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
15
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Figure 2. Dynamic Bus Sizing (Continued)
(1)
Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
Figure 3. Logic Diagrams for SIZ0, SIZ1, and
BE
Register
D
C
(d) BYTE SIZE
LITTLE-ENDIAN
1st: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
A
B
3rd: Read from FIFO1/
Write to FIFO2
4th: Read from FIFO1/
Write to FIFO2
BE SIZ1 SIZ0
H H L
4663 drw fig 01a
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
B35
B27 B26B18 B17B9 B8B0
MUX
G1
1
1
D Q
SIZ0 Q
SIZ1 Q
BE Q
SIZ0
SIZ1
BE
CLKB
4663 drw fig 02
16
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Figure 4. Byte Swapping (Long Word Size Example)
A
A
A
D
A
C
A
B
B
B
C
B
D
B
A
B
C
C
C
B
C
A
C
D
D
D
D
A
D
B
D
C
(a) NO SWAP
(b) BYTE SWAP
(c) WORD SWAP
(d) BYTE-WORD SWAP
L L
SW1 SW0
SW1 SW0
SW1 SW0
SW1 SW0
L L
L H
H L
H H
4663 drw fig 03
A35
A27 A26A18 A17A9 A8A0
B35
B27 B26B18 B17B9 B8B0
A35
A27 A26A18 A17A9 A8A0
B35
B27 B26B18 B17B9 B8B0
A35
A27 A26A18 A17A9 A8A0
B35
B27 B26B18 B17B9 B8B0
A35
A27 A26A18 A17A9 A8A0
B35
B27 B26B18 B17B9 B8B0
17
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Figure 5. Device Reset and Loading the X Register with the Value of Eight
CLKA
RST
FFA
FFB
EFB
AEA
CLKB
EFA
FS1,FS0
4663 drw 05
t
RSTS
t
RSTH
t
FSH
t
FSS
t
WFF
t
WFF
t
WFF
0,1
t
REF
t
REF
AFA
MBF1,
MBF2
t
WFF
t
RSF
t
PAE
AEB
AFB
t
PAF
t
PAE
t
PAF
18
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTE:
1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register
SWAP MODE
DATA WRITTEN TO FIFO2
DATA READ FROM FIFO2
SW1
SW0
B35-27
B26-18
B17-B9
B8-B0
A35-27
A26-A18
A17-A9
A8-A0
L
L
A
B
C
D
A
B
C
D
L
H
D
C
B
A
A
B
C
D
H
L
C
D
A
B
A
B
C
D
H
H
B
A
D
C
A
B
C
D
DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2
Figure 7. Port-B Long-Word Write Cycle Timing for FIFO2
Figure 6. Port-A Write Cycle Timing for FIFO1
CLKB
ENB
SW1,
SW0
FFB
W/
RB
B0-B35
BE
PEFB
ODD/
EVEN
HIGH
4663 drw 07
t
ENS
t
ENS
t
ENS
t
ENH
CSB
SIZ1,
SIZ0
VALID
VALID
t
PDPE
NOT (1,1)
(1)
(0,0)
t
DH
t
DS
t
SZH
t
SZS
t
SZS
t
SZH
t
ENS
t
ENH
t
PPE
(0,0)
t
SWS
t
SWH
4663 drw 06
CLKA
FFA
ENA
A0 - A35
MBA
CSA
W/
RA
t
CLKH
t
CLKL
t
CLK
t
ENS
t
ENS
t
ENS
t
ENS
t
DS
t
ENH
t
ENH
t
ENH
t
ENH
t
DH
W1
(1)
W2
(1)
t
ENS
t
ENH
t
ENH
t
ENS
No Operation
ODD/
EVEN
PEFA
Valid
Valid
t
PDPE
t
PDPE
HIGH
NOTE:
1. Written to FIFO1.
19
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.
2.
PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for Big-Endian bus, and B17-B9 and B-8-B0 for Little-Endian bus.
Figure 8. Port-B Word Write Cycle Timing for FIFO2
DATA WRITTEN TO FIFO2
SWAP
WRITE
DATA READ FROM FIFO2
MODE
NO.
BIG-ENDIAN
LITTLE-ENDIAN
SW1
SW0
B35-27
B26-18
B17-B9
B8-B0
A35-27
A26-A18
A17-A9
A8-A0
L
L
1
A
B
C
D
A
B
C
D
2
C
D
A
B
L
H
1
D
C
B
A
A
B
C
D
2
B
A
D
C
H
L
1
C
D
A
B
A
B
C
D
2
A
B
C
D
H
H
1
B
A
D
C
A
B
C
D
2
D
C
B
A
DATA SWAP TABLE FOR WORD WRITES TO FIFO2
CLKB
SW1, SW0
ENB
FFB
W/
RB
BE
HIGH
4663 drw 08
PEFB
ODD/
EVEN
Big-
Endian
B18-B35
Little-
Endian
B0-B17
SIZ1, SIZ0
CSB
(0, 1)
NOT (1,1)
(1)
t
ENH
t
ENH
t
ENS
t
ENS
t
ENH
t
ENS
t
ENS
t
SWH
t
SZH
t
SZH
t
SZH
t
SZS
t
SZS
t
SZS
t
SZS
t
DS
t
DS
VALID
VALID
t
PDPE
t
PPE
t
DH
t
DH
t
SZH
t
SWS
(0, 1)
20
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.
2.
PEFB indicates parity error for the following bytes: B35--B27 for Big-Endian bus and B8--B0 for Little-Endian bus.
DATA WRITTEN TO FIFO2
SWAP
WRITE
DATA READ FROM FIFO2
MODE
NO.
BIG-ENDIAN LITTLE-ENDIAN
SW1
SW0
B35-B27
B8-80
A35-A27
A26-A18
A17-A9
A8-A0
1
A
D
L
L
2
B
C
A
B
C
D
3
C
B
4
D
A
1
D
A
L
H
2
C
B
A
B
C
D
3
B
C
4
A
D
1
C
B
H
L
2
D
A
A
B
C
D
3
A
D
4
B
C
1
B
C
H
H
2
A
D
A
B
C
D
3
D
A
4
C
B
DATA SWAP TABLE FOR BYTE WRITES TO FIFO2
Figure 9. Port-B Byte Write Cycle Timing for FIFO2
FFB
CSB
W/
RB
SIZ1,
SIZ0
CLKB
4663 drw 09
HIGH
SW1,
SW0
BE
ODD/
EVEN
B0-
B8
(1,0)
(1,0)
Not (1,1)
(1)
t
ENS
t
ENH
t
SWS
t
SZH
t
SZH
t
SZS
ENB
Little-
Endian
Valid
Valid
Valid
Valid
Big-
Endian
B27-
B35
PEFB
t
PPE
t
PDPE
t
PDPE
t
PDPE
t
DS
t
DS
t
DH
t
DH
t
ENS
t
ENS
t
SZH
t
SZS
t
SZS
t
SZS
t
SZH
t
ENH
t
ENH
t
ENS
t
ENH
(1,0)
(1,0)
21
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Data read from FIFO1.
DATA WRITTEN TO FIFO1
SWAP MODE
DATA READ FROM FIFO1
A35-A27
A26-A18
A17-A9
A8-A0
SW1
SW0
B35-B27
B26-B18
B17-B9
B8-B0
A
B
C
D
L
L
A
B
C
D
A
B
C
D
L
H
D
C
B
A
A
B
C
D
H
L
C
D
A
B
A
B
C
D
H
H
B
A
D
C
DATA SWAP TABLE FOR FIFO LONG-WORD READS FROM FIFO1
Figure 10. Port-B Long-Word Read Cycle Timing for FIFO1
CLKB
ENB
SW1,
SW0
EFB
W/
RB
PGB,
BE
ODD/
EVEN
HIGH
4663 drw 10
CSB
SIZ1,
SIZ0
NOT (1,1)
(1)
t
PGH
t
PGS
t
SZH
t
SZS
t
SZS
t
SZH
t
ENH
(0,0)
t
SWS
B0-B35
NOT (1,1)
(1)
Previous Data
W1
(2)
W2
(2)
t
DIS
t
A
t
A
t
EN
t
ENS
t
ENH
t
SWH
t
ENS
No Operation
(0,0)
22
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused word B0-B17 or B18-B35 are indeterminate.
DATA READ FROM FIFO1
DATA WRITTEN TO FIFO1
SWAP MODE
READ NO.
BIG-ENDIAN
LITTLE-ENDIAN
A35-A27
A26-A18
A17-A9
A8-A0
SW1
SW0
B35-B27
B26-B18
B17-B9
B8-B0
1
A
B
C
D
A
B
C
D
L
L
2
C
D
A
B
1
D
C
B
A
A
B
C
D
L
H
2
B
A
D
C
1
C
D
A
B
A
B
C
D
H
L
2
A
B
C
D
1
B
A
D
C
A
B
C
D
H
H
2
D
C
B
A
DATA SWAP TABLE FOR WORD READS FROM FIFO1
Figure 11. Port-B Word Read Cycle Timing for FIFO1
t
DIS
CLKB
ENB
SW1,
SW0
EFB
W/
RB
PGB,
BE
ODD/
EVEN
HIGH
4663 drw 11
CSB
SIZ1,
SIZ0
NOT (1,1)
(1)
t
PGH
t
PGS
t
SZH
t
SZS
t
SZS
t
SZH
(0,1)
t
SWS
B0-B17
NOT (1,1)
(1)
Previous Data
t
DIS
t
A
t
A
t
EN
t
ENS
t
ENH
t
SWH
No Operation
Previous Data
B18-B35
Little-
Endian
Big-
Endian
t
A
t
A
Read 1
Read 1
Read 2
Read 2
(0,1)
(2)
(2)
23
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused bytes B9-B35 or B0-B26 are indeterminate.
Figure 12. Port-B Byte Read Cycle Timing for FIFO1
DATA WRITTEN TO FIFO 1
SWAP MODE
READ
BIG-
LITTLE-
NO.
ENDIAN
ENDIAN
A35-A27
A26-A18
A17-A9
A8-A0
SW1
SW0
B35-B27
B8-B0
1
A
D
2
B
C
A
B
C
D
L
L
3
C
B
4
D
A
1
D
A
2
C
B
A
B
C
D
L
H
3
B
C
4
A
D
1
C
B
2
D
A
A
B
C
D
H
L
3
A
D
4
B
C
1
B
C
2
A
D
A
B
C
D
H
H
3
D
A
4
C
B
DATA READ FROM FIFO 1
DATA SWAP TABLE FOR BYTE READS FROM FIFO1
EFB
CSB
W/
RB
SIZ1,
SIZ0
ENB
CLKB
4663 drw 12
HIGH
SW1,
SW0
BE
PGB,
ODD/
EVEN
B0-B8
B27-B35
Read 4
Read 1
Read 2
Read 4
Read 1
Read 3
Read 3
Previous Data
Previous Data
Read 2
(1,0)
(1,0)
(1,0)
Not (1,1)
(1)
No Operation
t
DIS
t
DIS
t
A
t
A
t
A
t
A
t
A
t
A
t
EN
t
PGH
t
PGS
Not (1,1)
(1)
Not (1,1)
(1)
Not (1,1)
(1)
(1,0)
t
ENS
t
ENH
t
SWS
t
SWH
t
SZH
t
SZH
t
SZS
t
SZS
t
A
t
A
Little-
Endian
Big-
Endian
(2)
(2)
24
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTE:
1. Read from FIFO2.
Figure 13. Port-A Read Cycle Timing for FIFO2
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for
EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than t
SKEW1
, then the transition of
EFB HIGH may occur one CLKB cycle later than shown.
2. Port-B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte,
EFB is set LOW by the last word or byte read from FIFO1, respec-
tively.
Figure14.
EFB
Flag Timing and First Data Read when FIFO1 is Empty
4663 drw 13
CLKA
EFA
ENA
A0 - A35
MBA
CSA
W/
RA
t
CLK
t
CLKH
t
CLKL
t
ENS
t
A
t
MDV
t
EN
t
A
t
ENS
t
ENH
t
ENS
t
ENH
Previous Data
Word 1
Word 2
(1)
(1)
t
ENH
t
DIS
No Operation
PGA,
ODD/
EVEN
HIGH
t
PGH
t
PGS
t
PGH
t
PGS
CSA
W
RA
MBA
FFA
A0 - A35
CLKB
EFB
CSB
W/
RB
SIZ1,
SIZ0
ENA
ENB
B0 -B35
CLKA
1
2
4663 drw 14
t
CLKH
t
CLKL
t
CLK
t
ENS
t
ENS
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
ENS
t
ENH
t
A
W1
FIFO1 Empty
LOW
HIGH
LOW
LOW
LOW
t
CLKH
W1
HIGH
(1)
t
REF
t
REF
25
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for
EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than t
SKEW1
, then the transition of
EFA HIGH may occur one CLKA cycle later than shown.
2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte t
SKEW1
is referenced to the rising CLKB edge that writes the last word or
byte of the long word, respectively.
Figure 15.
EFA
Flag Timing and First Data Read when FIFO2 is Empty
CSB
W
RB
SIZ1,
SIZ0
FFB
B0 - B35
CLKA
EFA
CSA
W/
RA
MBA
ENB
ENA
A0 - A35
CLKB
1
2
4663 drw 15
t
CLKH
t
CLKL
t
CLK
t
ENS
t
ENS
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
ENS
t
ENH
t
A
W1
FIFO2 Empty
LOW
HIGH
LOW
LOW
LOW
t
CLKH
W1
HIGH
(1)
t
REF
t
REF
26
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for
FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than t
SKEW1
, then
FFA may transition HIGH one CLKA cycle later than shown.
2. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, t
SKEW1
is referenced from the rising CLKB edge that reads the last
word or byte of the long word, respectively.
Figure 16.
FFA
Flag Timing and First Available Write when FIFO1 is Full.
CSB
EFB
SIZ1,
SIZ0
ENB
B0 - B35
CLKB
FFA
CLKA
CSA
4663 drw 16
W
RA
1
2
A0 - A35
MBA
ENA
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENS
t
DS
t
ENH
t
ENH
t
DH
To FIFO1
Previous Word in FIFO1 Output Register
Next Word From FIFO1
LOW
W/
RB LOW
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
t
WFF
t
WFF
27
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Figure 17.
FFB
Flag Timing and First Available Write when FIFO2 is Full
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for
AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than t
SKEW2
, then
AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, either SIZ1 = LOW or SIZ0 = LOW).
3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte,
AEB is set LOW by the last word or byte read of the long word,
respectively.
Figure 18. Timing for
AEB
when FIFO1 is Almost-Empty
CSA
EFA
MBA
ENA
A0 - A35
CLKA
FFB
CLKB
CSB
4663 drw 17
W
RB
1
2
B0 - B35
SIZ1,
SIZ0
ENB
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENS
t
DS
t
ENH
t
ENH
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/
RA
LOW
LOW
HIGH
LOW
HIGH
(1)
FIFO2 Full
t
WFF
t
WFF
AEB
CLKA
ENB
4663 drw 18
ENA
CLKB
2
1
t
ENS
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS
t
ENH
X Long Word in FIFO1
(X+1) Long Words in FIFO1
(1)
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for
FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than t
SKEW1
, then
FFB may transition HIGH one CLKB cycle later than shown.
2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte,
FFB is set LOW by the last word or byte write of the long word,
respectively.
28
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKB edge and a rising CLKA edge for
AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than t
SKEW2,
then
AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (
CSB = LOW, W/RB = HIGH, either SIZ0 = LOW or SIZ1 = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, t
SKEW2
is referenced from the rising CLKB edge that writes the last
word or byte of the long word, respectively.
Figure 19. Timing for
AEA
when FIFO2 is Almost-Empty
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for
AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than t
SKEW2
, then
AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, either SIZ0 = LOW or SIZ1 = LOW).
3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, t
SKEW2
is referenced from the last word or byte read of the long word,
respectively.
Figure 20. Timing for
AFA
when FIFO1 is Almost-Full
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKB edge and a rising CLKA edge for
AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than t
SKEW2
, then
AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 Write (
CSB = LOW, W/RB = HIGH, either SIZ0 = LOW or SIZ1 = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte,
AFB is set LOW by the last word or byte read of the long word,
respectively.
Figure 21. Timing for
AFB
when FIFO2 is Almost-Full
AEA
CLKB
ENA
4663 drw 19
ENB
CLKA
2
1
t
ENS
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS
t
ENH
(X+1) Long Words in FIFO2
X Long Words in FIFO2
(1)
AFA
CLKA
ENB
4663 drw 20
ENA
CLKB
1
2
t
SKEW2
t
ENS
t
ENH
t
PAF
t
ENS
t
ENH
t
PAF
[64-(X+1)] Long Words in FIFO1
(64-X) Long Words in FIFO1
(1)
AFB
CLKB
ENA
4663 drw 21
ENB
CLKA
1
2
t
SKEW2
t
ENS
t
ENH
t
ENS
t
ENH
t
PAF
[64-(X+1)] Long Words in FIFO2
(64-X) Long Words in FIFO2
(1)
t
PAF
29
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTE:
1. Port B Parity Generation off (PGB = LOW).
Figure 22. Timing for Mail1 Register and
MBF1
Flag
4663 drw 22
CLKA
ENA
A0 - A35
MBA
CSA
W/
RA
CLKB
MBF1
CSB
SIZ1,
SIZ0
ENB
B0 - B35
W/
RB
W1
t
ENS
t
ENH
t
DS
t
DH
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
W1 (Remains valid in Mail1 Register after read)
FIFO1 Output Register
30
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTE:
1. Port-A Parity Generation off (PGA = LOW).
Figure 24. ODD/
EVEN
. W/
R
A, MBA, and PGA to
PEFA
Timing
Figure 23. Timing for Mail2 Register and
MBF2
Flag
4663 drw 23
CLKB
ENB
B0 - B35
SIZ1,
SIZ0
CSB
W/
RB
CLKA
MBF2
CSA
MBA
ENA
A0 - A35
W/
RA
W1
t
ENS
t
ENH
t
DS
t
DH
t
PMF
t
PMF
t
ENS
t
ENH
t
DIS
t
EN
t
MDV
t
PMR
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
t
SZS
t
SZH
4663 drw 24
ODD/
EVEN
PEFA
PGA
MBA
W/
RA
Valid
Valid
Valid
Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
31
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Figure 25. ODD/
EVEN
. W/
R
B, SIZ1, SIZ0, and PGB to
PEFB
Timing
Figure 27. Parity Generation Timing when Reading from the Mail1 Register
Figure 26. Parity Generation Timing when Reading from the Mail2 Register
NOTE:
1. ENA is HIGH.
NOTE:
1. ENB is HIGH.
4663 drw 25
ODD/
EVEN
PEFB
PGB
SIZ1,
SIZ0
W/
RB
Valid
Valid
Valid
Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
4663 drw 26
ODD/
EVEN
A8, A17,
A26, A35
PGA
MBA
W/
RA
Mail2
Data
Generated Parity
Generated Parity
Mail2 Data
CSA LOW
t
EN
t
PEPB
t
POPB
t
PEPB
t
MDV
4663 drw 27
ODD/
EVEN
B8, B17,
B26, B35
PGB
SIZ1,
SIZ0
W/
RB
Mail1
Data
Generated Parity
Generated Parity
Mail1 Data
CSB LOW
t
EN
t
PEPB
t
POPB
t
PEPB
t
MDV
32
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTE:
1. Includes probe and jig capacitance.
Figure 28. Load Circuit and Voltage Waveforms
4663 drw 28
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
330
3.3V
510
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
3V
1.5 V
1.5 V
1.5 V
1.5 V
OH
OV
GND
OH
OL
1.5 V
1.5 V
1.5 V
1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PD
t
PD
(1)
33
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
408-330-1753
Santa Clara, CA 95054
fax: 408-492-8674
email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
4663 drw 29
BLANK
PF
PQF
12
15
20
L
72V3614
Commercial (0
C to +70C)
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Commercial
Low Power
64 x 36 x 2
3.3V SyncBiFIFO
XXXXXXX
IDT
Device Type
X
XX
X
X
Power
Speed
Package
Process/
Temperature
Range
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
NOTE:
1. Industrial temperature range is available by special order.
DATASHEET DOCUMENT HISTORY
07/10/2000
pg. 1.
05/27/2003
pg. 6.
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