DSC-5714/3

JANUARY 2002

3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
1,024 x 1,024

IDT72V70210

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS

is a trademark of Mitel Corp.

.UNCTIONAL BLOCK DIAGRAM

.EATURES:

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32 serial input and output streams

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1,024 x 1,024 channel non-blocking switching at 2.048 Mb/s

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Per-channel Variable Delay Mode for low-latency applications

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Per-channel Constant Delay Mode for frame integrity applications

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Automatic identification of ST-BUS

and GCI serial streams

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Automatic frame offset delay measurement

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Per-stream frame delay offset programming

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Per-channel high impedance output control

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Per-channel processor mode to allow microprocessor writes to

TX streams

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Direct microprocessor access to all internal memories

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Memory block programming for quick set-up

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IEEE-1149.1 (JTAG) Test Port

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Internal Loopback for testing

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· Available in 144-pin Ball Grid Array (BGA) and 144-pin Thin Quad

Flatpack (TQFP) packages

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Operating Temperature Range -40

°°
°°
°

C to +85

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°

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3.3V I/O with 5V tolerant inputs and TTL compatible outputs

DESCRIPTION:

The IDT72V70210 has a non-blocking switch capacity of 1,024 x 1,024

channels at 2.048 Mb/s. With 32 inputs and 32 outputs, programmable per
stream control, and a variety of operating modes the IDT72V70210 is designed
for the TDM time slot interchange function in either voice or data applications.

Some of the main features of the IDT72V70210 are low power 3.3 Volt

operation, automatic ST-BUS

/GCI sensing, memory block programming,

simple microprocessor interface, one cycle direct internal memory accesses,
JTAG Test Access Port (TAP) and per stream programmable input offset delay,
variable or constant throughput modes, internal loopback, output enable, and
Processor Mode.

Output
MUX

Receive
Serial Data
Streams

RX0
RX1

RX2
RX3
RX4

RX5
RX6

RX7

ODE

F0i

Vcc

A0-A11

GND

DTA

D0-D15

5714 drw01

RX8

RX9
RX10

RX11
RX12

RX13
RX14

RX15

Loopback

Test Port

Data Memory

Internal
Registers

Microprocessor Interface

Timing Unit

TX0

TX1
TX2

TX3
TX4

TX5
TX6

TX7
TX8

TX9
TX10
TX11

TX12
TX13

TX14
TX15

CLK

TDI

TMS

TCK

TDO

TRST

RESET

RX16

RX17
RX18

RX19
RX20
RX21

RX22
RX23

RX24
RX25

RX26
RX27

RX28
RX29

RX30
RX31

TX16
TX17

TX18
TX19

TX20
TX21

TX22
TX23

TX24
TX25
TX26

TX27
TX28

TX29
TX30

TX31

Connection
Memory

Transmit
Serial Data
Streams

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

TX11

TX10

GND

TX9

TX8

RX15

RX14

RX13

RX12

RX11

RX10

RX9

RX8

GND

TX7

TX6

TX5

TX4

GND

TX3

TX2

TX1

TX0

GND

RX7

RX6

RX5

RX4

RX3

RX2

RX1

RX0

RX31

RX30

RX29

RX28

RX27

RX26

RX25

RX24

GND

TX23

TX22

TX21

TX20

GND

TX19

TX18

TX17

TX16

GND

RX23

RX22

RX21

RX20

RX19

RX18

RX17

RX16

TX15

TX14

GND

TX13

TX12

TX24

TX25

GND

TX26

TX27

TX28

TX29

GND

TX30

TX31

GND

D08

D09

GND

D10

D11

D12

D13

GND

D14

D15

DTA

GND

A11

A10

GND

TRST

TCK

TDO

TDI

TMS

F0i

CLK

GND

RESET

ODE

GND

5714 drw 03

108

107

106

105

104

103

102

101

100

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138
139

140

141

142

143

144

43
42

TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA)

TOP VIEW

NOTES:
1. IC - Internal Connection, tie to Ground for normal operation.
2. All I/O pins are 5V tolerant except for TMS, TDI and

TRST.

PIN CON.IGURATIONS (CONTINUED)

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

PIN DESCRIPTION

SYMBOL

NAME

I/O

DESCRIPTION

GND

Ground.

Ground Rail.

+3.3 Volt Power Supply.

TX0-31

TX Output 0 to 31

Serial data output stream. These streams have a data rate of 2.048 Mb/s.

(Three-state Outputs)

RX0-31

RX Input 0 to 31

Serial data input stream. These streams have a data rate of 2.048 Mb/s.

F0i

Frame Pulse

This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUS

and GCI specifications.

Frame Evaluation

This pin is the frame measurement input.

CLK

Clock

Serial clock for shifting data in/out on the serial streams (RX/TX 0-31). This input accepts a 4.096 MHz clock.

TMS

Test Mode Select

JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.

TDI

Test Serial Data In

JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.

TDO

Test Serial Data Out

JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enabled.

TCK

Test Clock

Provides the clock to the JTAG test logic.

TRST

Test Reset

Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V70210 is in the normal functional mode.

RESET

Device Reset

This input (active LOW) puts the IDT72V70210 in its reset state that clears the device internal counters,

(Schmitt Trigger Input)

registers and brings TX0-31 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the

RESET pin must be held LOW for a minimum of 100ns to reset the device.

Data Strobe

This active LOW input works in conjunction with

CS to enable the read and write operations.

Read/Write

This input controls the direction of the data bus lines during a microprocessor access.

Chip Select

Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70210.

A0-11

Address Bus 0 to 11

These pins allow direct access to Connection Memory, Data Memory and internal control registers.

D0-15

Data Bus 0-15

I/O These pins are the data bits of the microprocessor port.

DTA

Data Transfer

This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives

Acknowledgment

HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up
resistor is required to hold a HIGH level when the pin is in high-impedance.

ODE

Output Drive Enable

This is the output enable control for the TX0-31 serial outputs. When ODE input is LOW and the OSB bit of
the CR register is LOW, TX0-31 are in a high-impedance state. If this input is HIGH, the TX0-31 output
drivers are enabled. However, each channel may still be put into a high-impedance state by using the per
channel control bit in the connection memory.

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

DESCRIPTION (CONTINUED):

The IDT72V70210 is capable of switching up to 1,024 x 1,024 channels

without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per channel basis.

The 32 serial input streams (RX) of the IDT72V70210 can be run 2.048 Mb/s

allowing 32 channels per 125

s frame. The data rates on the output streams

(TX) are identical to those on the input stream.

With two main operating modes, Processor Mode and Connection Mode,

the IDT72V70210 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor (Connection Memory). As
control and status information is critical in data transmission, the Processor Mode
is especially useful when there are multiple devices sharing the input and output
streams.

With data coming from multiple sources and through different paths, data

entering the device is often delayed. To handle this problem, the IDT72V70210
has a frame evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +4.5 clock cycles.

The IDT72V70210 also provides a JTAG test access port, an internal

loopback feature, memory block programming, a simple microprocessor
interface and automatic ST-BUS

/GCI sensing to shorten setup time, aid in

debugging and ease use of the device without sacrificing capabilities.

.UNCTIONAL DESCRIPTION

DATA AND CONNECTION MEMORY

All data that comes in through the RX inputs go through a serial-to-

parallel conversion before being stored into internal Data Memory. The 8 KHz
frame pulse (

F0i) is used to mark the 125

s frame boundaries and to sequentially

address the input channels in Data Memory.

Data output on the TX streams may come from either the Serial Input Streams,

RX0-31, (Data Memory) or from the microprocessor (Connection Memory). In
the case that RX input data is to be output, the addresses in connection memory
are used to specify a stream and channel of the input. The connection memory
is setup in such a way that each location corresponds to an output channel for
each particular stream. In that way, more than one channel can output the same
data.

In Processor Mode, the microprocessor writes data to the connection

memory locations corresponding to the stream and channel that is to be
output. The lower half (8 least significant bits) of the connection memory
is output every frame until the microprocessor changes the data or mode
of the channel. By using this Processor Mode capability, the microproces-
sor can access input and output time-slots on a per channel basis.

The four most significant bits of the connection memory are used to control

per channel functions of the out put streams. Specifically, there are bits for
Processor or Connection mode, Constant or Variable delay, enables or
disables of output drivers, and controls for the Loopback function.

If the per channel OE is set to zero, only that particular channel (8-bits) will

be in the high-impedance state. If however, the ODE input pin is low or the Output
Standby Bit (OSB) in the Control Register is low, all of the outputs will be in a
high-impedance state even if a particular channel in connection memory has
enabled the output for that channel. In other words, the ODE pin and OSB control
bit are master output enables for the device (Table 3).

SERIAL DATA INTERFACE TIMING

The master clock frequency must always be twice the data rate. For a serial

data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The
input and output stream data rates will always be identical.

The IDT72V70210 provides two different interface timing modes, ST-BUS

or GCI. The IDT72V70210 automatically detects the presence of an input frame
pulse and identifies it as either ST-BUS

or GCI. In ST-BUS

format, every

second falling edge of the master clock marks a bit boundary and the data is
clocked in on the rising edge of CLK, three quarters of the way into the bit cell.
In GCI format, every second rising edge of the master clock marks the bit
boundary and data is clocked in on the falling edge of CLK at three quarters of
the way into the bit cell.

INPUT FRAME OFFSET SELECTION

Input frame offset selection allows the channel alignment of individual

input streams to be offset with respect to the output stream channel
alignment (i.e.

F0i). Although all input data comes in at the same speed, delays

can be caused by variable path serial backplanes and variable path lengths
which may be implemented in large centralized and distributed switching
systems. Because data is often delayed this feature is useful in compensating
for the skew between clocks.

Each input stream can have its own delay offset value by programming the

frame input offset registers (FOR, Table 8). The maximum allowable skew is +4
master clock (CLK) periods forward with a resolution of 1/2 clock period. The
output frame offset cannot be offset or adjusted.

SERIAL INPUT FRAME ALIGNMENT EVALUATION

The IDT72V70210 provides the frame evaluation (FE) input to deter-

mine different data input delays with respect to the frame pulse

F0i.

A measurement cycle is started by setting the start frame evaluation (SFE)

bit low for at least one frame. When the SFE bit in the Control Register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle is started.

In ST-BUS

mode, the falling edge of the frame measurement signal (FE)

is evaluated against the falling edge of the ST-BUS

frame pulse. In GCI mode,

the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 7 and Figure 1 for the description of the frame alignment register.

MEMORY BLOCK PROGRAMMING

The IDT72V70210 provides users with the capability of initializing the entire

connection memory block in two frames. To set bits 12 to 15 of every connection
memory location, first program the desired pattern in bits 5 to 8 of the Control
Register.

The block programming mode is enabled by setting the memory block

program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the Control Register is set to high, the block programming
data will be loaded into the bits 12 to 15 of every connection memory location.
The other connection memory bits (bit 0 to bit 11) are loaded with zeros. When
the memory block programming is complete, the device resets the BPE bit to zero.

LOOPBACK CONTROL

The loopback control (LPBK) bit of each connection memory location allows

the TX output data to be looped backed internally to the RX input for diagnostic
purposes.

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., data from TXn channel m routes to
the RXn channel m internally); if the LPBK bit is low, the loopback feature is

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.

DELAY THROUGH THE IDT72V70210

The switching of information from the input serial streams to the output

serial streams results in a throughput delay. The device can be pro-
grammed to perform time-slot interchange functions with different through-
put delay capabilities on a per-channel basis. For voice applications,
variable throughput delay is best as it ensure minimum delay between input
and output data. In wideband data applications, constant throughput delay
is best as the frame integrity of the information is maintained through the
switch.

The delay through the device varies according to the type of throughput

delay selected in the

V/C bit of the connection memory.

VARIABLE DELAY MODE (

V/C BIT = 0)

In this mode, the delay is dependent only on the combination of source

and destination channels and is independent of input and output streams.
The minimum delay achievable in the IDT72V70210 is three time-slots. If
the input channel data is switched to the same output channel (channel n,
frame p), it will be output in the following frame (channel n, frame p+1). The
same is true if the input channel n is switched to output channel n+1 or n+2.
If the input channel n is switched to output channel n+3, n+4,..., the new
output data will appear in the same frame. Table 2 shows the possible
delays for the IDT72V70210 in the variable delay mode.

CONSTANT DELAY MODE (

V/C BIT = 1)

In this mode, frame integrity is maintained in all switching configurations by

making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V70210, the minimum throughput delay achievable in the constant
delay mode will be one frame. For example, when input time-slot 31 is switched
to output time-slot 0. The maximum delay of 94 time-slots of delay occurs when
time-slot 0 in a frame is switched to time-slot 31 in the frame.

MICROPROCESSOR INTER.ACE

The IDT72V70210's microprocessor interface looks like a standard RAM

interface to improve integration into a system. With a 12-bit address bus and
a 16-bit data bus, read and writes are mapped directly into Data and Connection
memories and require only one cycle to access. By allowing the internal
memories to be randomly accessed in one cycle, the controlling microprocessor
has more time to manage other peripheral devices and can more easily and
quickly gather information and setup the switch paths.

Table 4 shows the mapping of the addresses into internal memory blocks

and Table 5 shows the Control Register information.

MEMORY MAPPING

The address bus on the microprocessor interface selects the internal

registers and memories of the IDT72V70210.

The two most significant bits of the address select between the registers, Data

Memory, and Connection Memory. If A11 and A10 are HIGH, A9-A0 are used
to address the Data Memory. If A11 is HIGH and A10 is LOW, A9-A0 are used
to address Connection Memory. If A11 is LOW and A10 is HIGH A9-A0 are
used to select the Control Register, Frame Alignment Register, and Frame Offset
Registers. See Table 4 for mappings.

As explained in the Serial Data Interface Timing and Switching Configura-

tions sections, after system power-up, the Control Register should be pro-
grammed immediately to establish the desired switching configuration.

The data in the Control Register consists of the Memory Block Programming

bit (MBP), the Block Programming Data (BPE) bits, the Begin Block Program-
ming Enable (BPE), the Output Stand By, Start Frame Evaluation, and Data Rate
Select bits. As explained in the Memory Block Programming section, the BPE
begins the programming if the MBP bit is enabled. This allows the entire
connection memory block to be programmed with the Block Programming Data
bits. If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all
TX output drivers. If the ODE pin is high, the contents of the OSB bit is ignored
and all TX output drivers are enabled.

CONNECTION MEMORY CONTROL

If the ODE pin or the OSB bit is high, the OE bit of each connection memory

location controls the output drivers-enables (if high) or disables (if low). See
Table 3 for detail.

The Processor Channel (PC) bit of the Connection Memory selects between

Processor Mode and Connection Mode. If high, the contents of the Connection
Memory are output on the TX streams. If low, the Stream Address Bit (SAB)
and the Channel Address Bit (CAB) of the Connection Memory defines the
source information (stream and channel) of the time-slot that will be switched to
the output from Data Memory.

Also in the Connection Memory is the

V/C (Variable/Constant Delay) bit.

Each Connection Memory location allows the per-channel selection between
variable and constant throughput delay modes.

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., RXn channel m data comes from the
TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.

INITIALIZATION O. THE IDT72V70210

After power up, the state of the connection memory is unknown. As such,

the outputs should be put in high impedance by holding the ODE low. While the
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

TABLE 1 CONSTANT THROUGHPUT

DELAY VALUE

Delay for Constant Throughput Delay Mode

Input Rate

(m output channel number)

(n input channel number)

2.048 Mb/s

32 + (32 n) +m time-slots

TABLE 2 VARIABLE THROUGHPUT DELAY VALUE

Delay for Variable Throughput Delay Mode

Input Rate

(m output channel number; n input channel number)

m < n

m = n, n+1, n+2

m > n+2

2.048 Mb/s

32 (n-m) time-slots

(m-n + 32) time slots

(m-n) time-slots

OE bit in Connection

ODE pin

OSB bit in CR

TX Stream Output

Memory

Register

Status

Don't Care

Per Channel

High-Impedance

Enable

TABLE 3 OUTPUT HIGH IMPEDANCE CONTROL

TABLE 4 INTERNAL REGISTER AND ADDRESS MEMORY MAPPING

A11

A10

R/W

Location

STA4

STA3

STA2

STA1

STA0

CH4

CH3

CH2

CH1

CH0

Data Memory

STA4

STA3

STA2

STA1

STA0

CH4

CH3

CH2

CH1

CH0

R/W

Connect. Memory

R/W

Control Register

R/W

Frame Align Register

R/W

FOR0

R/W

FOR1

R/W

FOR2

R/W

FOR3

R/W

FOR4

R/W

FOR5

R/W

FOR6

R/W

FOR7

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

Reset Value:

0000

Bit

Name

Description

15-10

Unused

Must be zero for normal operation.

MBP

When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits,

(Memory Block Program)

bit 11 to bit 15. When 0, this feature is disabled.

8-5

BPD4-0

These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature

(Block Programming Data)

is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD3-0 are

loaded into bit 15 and 12 of the connection memory. Bit 11 to bit 0 of the connection memory are set to 0.

BPE

A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0 bits in the CR

(Begin Block

Programming Enable)

complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the

operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort to ensure proper operation. When
BPE = 1, the other bit in the CR register must not be changed for two frames to ensure proper operation.

OSB

When ODE = 0 and OSB = 0, the output drivers of TX0 to TX31 are in high impedance mode. When ODE = 0 and OSB = 1,

(Output Stand By)

the output driver of TX0 to TX31 function normally. When ODE = 1, TX0 to TX31 output drivers function normally.

SFE

A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from

(Start Frame Evaluation)

zero to one, the evaluation procedure stops. To start another fame evaluation cycle, set this bit to zero for at least one frame.

1-0

Unused

Must be zero for normal operation.

MBP

BPD3

BPD2

BPD1

BPD0

BPE

OSB

SFE

TABLE 5 CONTROL REGISTER (CR) BITS

TABLE 6 CONNECTION MEMORY BITS

Bit

Name

Description

LPBK

When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay

(Per Channel Loopback)

offset register bits OFn[2:0] to zero for the streams which are in the loopback mode.

V/C (Variable/Constant

This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a per-channel basis.

Throughput Delay)

P C

When 1, the contents of the connection memory are output on the corresponding output channel and stream. Only the lower

(Processor Channel)

byte (bit 7 bit 0) will be output to the TX output pins. When 0, the contents of the connection memory are the data memory

address of the switched input channel and stream.

This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions normally. When 0, the output

(Output Enable)

driver is in a high-impedance state.

11-7

SAB4-0 (Source Stream

The binary value is the number of the data stream for the source of the connection.

Address Bits)

6-5

Unused

Must be zero for normal operation.

4-0

CAB4-0 (Source Channel

The binary value is the number of the channel for the source of the connection.

Address Bits)

LPBK

V/C

SAB4

SAB3

SAB2

SAB1

SAB0

CAB4

CAB3

CAB2

CAB1

CAB0

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

ST-BUS

Frame

CLK

Offset Value

FE Input

GCI Frame

CLK

Offset Value

FE Input

(FD[10:0] = 06

)

(FD11 = 0, sample at CLK LOW phase)

(FD[10:0] = 09

)

(FD11 = 1, sample at CLK HIGH phase)

5714 drw 04

Figure 1. Example for Frame Alignment Measurement

Bit

Name

Description

15-13

Unused

Must be zero for normal operation

CFE (Complete

When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to

Frame Evaluation)

zero, when SFE bit in the CR register is changed from 1 to 0.

FD11

The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase

(Frame Delay Bit 11) (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.

10-0

FD10-0

The binary value expressed in these bits refers to the measured input offset value. These bits are rest to zero when the SFE bit of the

(Frame Delay Bits)

CR register changes from 1 to 0. (FD10 MSB, FD0 LSB)

Reset Value:

0000

CFE

FD11

FD10

FD9

FD8

FD7

FD6

FD5

FD4

FD3

FD2

FD1

FD0

TABLE 7 .RAME ALIGNMENT REGISTER (.AR) BITS

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

TABLE 8 .RAME INPUT O..SET REGISTER (.OR) BITS

Reset Value:

0000

for all FOR registers.

OF32

OF31

OF30

DLE3

OF22

OF21

OF20

DLE2

OF12

OF11

OF10

DLE1

OF02

OF01

OF00

DLE0

FOR0 Register

OF72

OF71

OF70

DLE7

OF62

OF61

OF60

DLE6

OF52

OF51

OF50

DLE5

OF42

OF41

OF40

DLE4

FOR1 Register

OF112

OF111

OF110

DLE11

OF102

OF101

OF100

DLE10

OF92

OF91

OF90

DLE9

OF82

OF81

OF80

DLE8

FOR2 Register

OF312

OF311

OF310

DLE31

OF142

OF141

OF140

DLE14

OF132

OF131

OF130

DLE13

OF122

OF121

OF120

DLE12

FOR3 Register

OF192

OF191

OF190

DLE19

OF182

OF181

OF180

DLE18

OF172

OF171

OF170

DLE17

OD162

OD161

OF160

DLE16

FOR4 Register

OF232

OF231

OF230

DLE23

OF222

OF221

OF220

DLE22

OF212

OF211

OF210

DLE21

OF202

OF201

OF200

DLE20

FOR5 Register

OF272

OF271

OF270

DLE27

OF262

OF261

OF260

DLE26

OF252

OF251

OF250

DLE25

OF242

OF241

OF240

DLE24

FOR6 Register

OF312

OF311

OF310

DLE31

OF302

OF301

OF300

DLE30

OF292

OF291

OF290

DLE29

OF282

OF281

OF280

DLE28

FOR7 Register

Name

(1)

Description

OFn2, OFn1, OFn0

These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame.

(Offset Bits 2, 1 & 0)

The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the

F0i

input of the device. See Figure 1.

DLEn

ST-BUS

mode:

DLEn = 0, if clock rising edge is at the ¾ point of the bit cell.

(Data Latch Edge)

DLEn = 1, if when clock falling edge is at the ¾ of the bit cell.

GCI mode:

DLEn = 0, if clock falling edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.

NOTE:
1. n denotes an input stream number from 0 to 31.

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

JTAG SUPPORT

The IDT72V70210 JTAG interface conforms to the Boundary-Scan stan-

dard IEEE-1149.1. This standard specifies a design-for-testability technique
called Boundary-Scan test (BST). The operation of the boundary-scan circuitry
is controlled by an external test access port (TAP) Controller.

TEST ACCESS PORT (TAP)

The Test Access Port (TAP) provides access to the test functions of the

IDT72V70210. It consists of three input pins and one output pin.

·Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere

with any on-chip clock and thus remain independent. The TCK permits
shifting of test data into or out of the Boundary-Scan register cells
concurrently with the operation of the device and without interfering with the
on-chip logic.

·Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP

Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to V

when it is not

driven from an external source.

·Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction

register or into a test data register, depending on the sequence previously
applied to the TMS input. Both registers are described in a subsequent
section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vcc when it is not driven from an external source.

·Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the

contents of either the instruction register or data register are serially shifted out

towards the TDO. The data out of the TDO is clocked on the falling edge of the
TCK pulses. When no data is shifted through the boundary scan cells, the TDO
driver is set to a high impedance state.

·Test Reset (

TRST)

Reset the JTAG scan structure. This pin is internally pulled to V

INSTRUCTION REGISTER

In accordance with the IEEE-1149.1 standard, the IDT72V70210 uses

public instructions. The IDT72V70210 JTAG Interface contains a two-bit
instruction register. Instructions are serially loaded into the instruction register
from the TDI when the TAP Controller is in its shifted-IR state. Subsequently,
the instructions are decoded to achieve two basic functions: to select the test data
register that may operate while the instruction is current, and to define the serial
test data register path, which is used to shift data between TDI and TDO during
data register scanning.

TEST DATA REGISTER

As specified in IEEE-1149.1, the IDT72V70210 JTAG Interface contains

two test data registers:

·The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells

arranged to form a scan path around the boundary of the IDT72V70210 core
logic.

·The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit

path from TDI to its TDO. The IDT72V70210 boundary scan register bits are
shown in Table 10. Bit 0 is the first bit clocked out. All three-state enable bits are
active high.

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

TABLE 10 BOUNDARY SCAN REGISTER BITS

Boundary Scan Bit 0 to bit 167

Device Pin

Three-State

Output

Input

Control

Scan Cell

RX27

RX26

RX25

RX24

TX23

TX22

TX21

100

101

TX20

102

103

TX19

104

105

TX18

106

107

TX17

108

109

TX16

110

111

RX23

112

RX22

113

RX21

114

RX20

115

RX19

116

RX18

117

RX17

118

RX16

119

TX15

120

121

TX14

122

123

TX13

124

125

TX12

126

127

TX11

128

129

TX10

130

131

TX9

132

133

TX8

134

135

RX15

136

RX14

137

RX13

138

RX12

139

RX11

140

RX10

141

RX9

142

RX8

143

TX7

144

145

TX6

146

147

TX5

148

149

TX4

150

151

TX3

152

153

TX2

154

155

TX1

156

157

TX0

158

159

RX7

160

RX6

161

RX5

162

RX4

163

RX3

164

RX2

165

RX1

166

RX0

167

Boundary Scan Bit 0 to bit 167

Device Pin

Three-State

Output

Input

Control

Scan Cell

ODE

RESET

CLK

F0i

A10

A11

DTA

D15

D14

D13

D12

D11

D10

TX31

TX30

TX29

TX28

TX27

TX26

TX25

TX24

RX31

RX30

RX29

RX28

COMMERCIAL TEMPERATURE RANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024

Symbol

Parameter

Min.

Typ.

Max.

Units

(2)

Supply Current @ 2 Mb/s

(3,4)

Input Leakage (input pins)

(3,4)

High-impedance Leakage

(5)

Output HIGH Voltage

2.4

(6)

Output LOW Voltage

0.4

Symbol

Rating

Level

Unit

TTL Threshold

1.5

TTL Rise/Fall Threshold Voltage HIGH

2.0

TTL Rise/Fall Threshold Voltage LOW

0.8

DC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS - TIMING PARAMETER

MEASUREMENT VOLTAGE LEVELS

NOTES:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Outputs unloaded.
3. 0

4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V).
5. IOH = 10 mA.
6. IOL = 10 mA.

Test Point

Output

GND

VCC

GND

5714 drw06

S1 is open circuit except when testing output
levels or high impedance states.

S2 is switched to V

or GND when testing

output levels or high impedance states.

Figure 3. Output Load

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

3.0

3.6

Voltage on Digital Inputs

GND -0.3

5.3

Current at Digital Outputs

-50

Storage Temperature

-55

+125

° C

Package Power Dissapation

NOTE:

1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.

ABSOLUTE MAXIMUM RATINGS

(1)

RECOMMENDED OPERATING

CONDITIONS

(1)

NOTE:
1.Voltages are with respect to Ground unless otherwise stated.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Positive Supply

3.0

3.3

3.6

Input HIGH Voltage

2.0

5.3

Input LOW Voltage

0.8

Operating Temperature

-40

+85

Commercial

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