MAY 2003

PRELIMINARY

IDT72V71650

3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
8,192 x 8,192

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.

DSC-5906/8

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

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8K x 8K non-blocking switching at 16.384Mb/s

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32 serial input and output streams

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Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or

16.384Mb/s

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Per-channel Variable Delay Mode for low-latency applications

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Per-channel Constant Delay Mode for frame integrity applications

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Automatic identification of ST-BUS

and GCI bus interfaces

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Automatic frame offset delay measurement

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Per-stream frame delay offset programming

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Per-channel high-impedance output control

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Direct microprocessor access to all internal memories

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Memory block programming for quick setup

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IEEE-1149.1 (JTAG) Test Port

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3.3V Power Supply

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Available in 144-pin (13mm x 13mm) Plastic Ball Grid Array (PBGA)

and 144-pin (20mm x 20mm) Thin Quad Flatpack (TQFP) packages

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Operating Temperature Range -40

°°
°°
°C to +85°°°°°C

DESCRIPTION:

The IDT72V71650 has a non-blocking switch capacity of 1,024 x 1,024

channels at 2.048Mb/s, 2,048 x 2,048 channels at 4.096Mb/s, and 4,096 x
4,096 channels at 8.192Mb/s and 8,192 x 8,192 channels at 16.384Mb/s. With
32 inputs and 32 outputs, programmable per stream control, and a variety of
operating modes the IDT72V71650 is designed for the TDM time slot inter-
change function in either voice or data applications.

Some of the main features of the IDT72V71650 are low power 3.3 Volt

operation, automatic ST-BUS

/GCI sensing, memory block programming,

simple microprocessor interface, one cycle direct internal memory accesses,
JTAG Test Access Port (TAP) and per stream programmable input offset delay,
variable or constant throughput modes, output enable and processor mode.

The IDT72V71650 is capable of switching up to 8,192 x 8,192 channels

without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per-channel basis.

RX0

RX1

RX31

ODE

GND

DTA

D0-D15

TX0

TX1

TX31/OEI15

CLK

FE/HCLK

RESET

5906 drw01

Receive
Serial Data
Streams

MUX

Data Memory

Internal
Registers

Microprocessor Interface

Timing Unit

Connection
Memory

Transmit
Serial Data
Streams

JTAG Port

WFPS

TDO

TMS TDI TCK

TRST

A0-A14

TX17/OEI1

TX16/OEI0

TX15

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

PIN CONFIGURATIONS (CONTINUED)

TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA)

TOP VIEW

GND

TX15
TX14
TX13
TX12

GND

TX11

TX10

TX9
TX8

GND

TX7
TX6
TX5

GND

TX3
TX2

TX1

GND

RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0

ODE

109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

TX4

TX0

RESET

TX29/OEI13

GND

RX25

RX26

RX27
RX28
RX29

RX31

GND

D0
D1

GND
VCC

D4
D5
D6
D7

GND
V

D8
D9
D10
D11

GND

D12

D13

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

RX24

RX30

TX28/OEI12

TX30/OEI14
TX31/OEI15

D14

D15

GND

DTA

A14

A13

A12

A11

TRST

TCK

TDO

TDI

TMS

WFPS

FE/HCLK

CLK

GND

A10

GND

TX27/OEI11

TX26/OEI10

TX25/OEI9

TX24/OEI8

GND

TX23/OEI7

TX22/OEI6

TX21/OEI5

GND

TX19/OEI3

TX18/OEI2

TX17/OEI1

GND

RX23

RX22

RX21

RX20

RX19

RX18

RX17

RX16

RX15

RX13

RX12

RX11

RX10

RX9

108

107

106

105

104

103

102

101

100

TX20/OEI4

RX14

RX8

5906 drw03

PIN 1

(1)

TX16/OEI0

(1)

NOTE:
1. NC = No Connect

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

PIN DESCRIPTION

SYMBOL

NAME

I/O

DESCRIPTION

A0-14

Address 0 to 14

These address lines access all internal memories.

CLK

Clock

Serial clock for shifting data in/out on the serial data streams. Depending upon the value programmed, this
input accepts a 4.096, 8.192 or 16.384 MHz clock. See the Control Register bits on Table 5 for the values.

Chip Select

This active LOW input is used by a microprocessor to activate the microprocessor port of IDT72V71650.

D0-15

Data Bus 0-15

I/O

These pins are the data bits of the microprocessor port.

Data Strobe

This active LOW input works in conjunction with

CS to enable the read and write operations and enables the

data bus lines (D0-D15).

DTA

Data Transfer

Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes

Acknowledgment

high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required
to hold a HIGH level when the pin is in high-impedance.

FE/HCLK Frame Evaluation/

When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the

HCLK Clock

HCLK (4.096 MHz clock) is required for frame alignment in the wide frame pulse mode (WFPS).

Frame Pulse

When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals
formatted according to ST-BUS

and GCI specifications. When pin WFPS is HIGH, this pin accepts a

negative frame pulse, which conforms to the WFPS format.

GND

Ground

Ground Rail.

ODE

Output Drive Enable

This is the output enable control for the TX serial outputs. When the ODE input is LOW and the Output Stand By

bit of the Control Register is LOW, all TX outputs are in a high-impedance state. If this input is HIGH, the TX output
drivers are enabled. However, each channel may still be put into a high-impedance state by using the per-channel
control bit in the Connection Memory.

RESET

Device Reset

This input puts the IDT72V71650 into a reset state that clears the device internal counters, registers and
brings TX0-31 and D0-D15 into a high-impedance state. The

RESET pin must be held LOW for a

minimum of 20ns to properly reset the device.

Read/Write

This input controls the direction of the data bus lines (D0-D15) during a microprocessor access.

RX0-31

Data Stream

Serial data input stream. These streams may have a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or
16.384Mb/s, depending upon the value programmed in the Control Register.

TCK

Test Clock

Provides the clock to the JTAG test logic.

TDI

Test Serial Data In

JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.

TDO

Test Serial Data Out

JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.

TMS

Test Mode Select

JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal

pull-up when not driven.

TRST

Test Reset

Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
to ensure that the IDT72V71650 is in the normal functional mode.

TX0-15

TX Output 0 to 15

Serial data output stream. These streams may have a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,

(Three-state Outputs)

or 16.384Mb/s, depending upon the value programmed in the Control Register.

TX16-31/ TX Output 16 to 31/

When all 32 outputs streams are selected via Control Register, these pins are the output streams TX16 to TX31

OEI0-15

Output Enable

and may operate at a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or 16.384Mb/s. When output enable

Indication 0 to 15

function is selected, these pins reflect the active or high-impedance status for the corresponding output stream

(Three-State Outputs)

OEI0-31.

+3.3 Volt Power Supply.

WFPS

Wide Frame Pulse Select

When 1, enables the wide frame pulse (WFPS) Frame Alignment interface. When 0, the device operates in

ST-BUS

/GCI mode.

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

DESCRIPTION (CONTINUED)

The 32 serial input streams (RX) of the IDT72V71650 can run up to

16.384Mb/s allowing 256 channels per 125

µs frame. The data rates on the

output streams (TX) are identical to those on the input streams (RX).

With two main operating modes, Processor Mode and Connection Mode, the

IDT72V71650 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor via Connection Memory. As
control and status information is critical in data transmission, the Processor Mode
is especially useful when there are multiple devices sharing the input and output
streams.

With data coming from multiple sources and through different paths, data

entering the device is often delayed. To handle this problem, the IDT72V71650
has a Frame Evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +7.5 clock cycles.

The IDT72V71650 also provides a JTAG test access port, memory block

programming, a simple microprocessor interface and automatic ST-BUS

/GCI

sensing to shorten setup time, aid in debugging and ease use of the device
without sacrificing capabilities.

FUNCTIONAL DESCRIPTION

DATA AND CONNECTION MEMORY

All data that comes in through the RX inputs go through a serial-to-parallel

conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (FP) is used to mark the 125

µs frame boundaries and to sequentially

address the input channels in Data Memory.

Data output on the TX streams may come from either the serial input streams

(Data Memory) or from the microprocessor (Connection Memory). In the case
that RX input data is to be output, the addresses in Connection Memory are used
to specify a stream and channel of the input. The Connection Memory is setup
in such a way that each location corresponds to an output channel for each
particular stream. In that way, more than one channel can output the same data.
In Processor Mode, the microprocessor writes data to the Connection Memory
locations corresponding to the stream and channel that is to be output. The lower
half (8 least significant bits) of the Connection Memory is output every frame until
the microprocessor changes the data or mode of the channel. By using this
Processor Mode capability, the microprocessor can access input and output
time-slots on a per-channel basis.

The two most significant bits of the Connection Memory are used to control

the per-channel mode of the out put streams. Specifically, the MOD1-0 bits are
used to select Processor Mode, Constant or Variable delay Mode, and the high-
impedance state of output drivers. If the MOD1-0 bits are set to 1-1 accordingly,
only that particular output channel (8 bits) will be in the high-impedance state.
If however, the ODE input pin is LOW and the Output Standby Bit in the Control
Register is LOW, all of the outputs will be in a high-impedance state even if a
particular channel in Connection Memory has enabled the output for that
channel. In other words, the ODE pin and Output Stand By control bit are master
output enables for the device (See Table 3).

SERIAL DATA INTERFACE TIMING

When a 16.384Mb/s serial data rate is required, the master clock frequency

will be running at 16.384 MHz resulting in a single-bit per clock. For all other
cases, 2.048Mb/s, 4.096Mb/s, and 8.192Mb/s, the master clock frequency will
be twice the data rate on the serial streams, resulting in two clocks per bit. Use
Table 5 to determine clock speed and the DR1-0 bits in the Control Register to

setup the device. The IDT72V71650 provides two different interface timing
modes, ST-BUS

or GCI. The IDT72V71650 automatically detects the pres-

ence of an input frame pulse and identifies it as either ST-BUS

or GCI.

In ST-BUS

, when running at 16.384 MHz, data is clocked out on the falling

edge and is clocked in on the subsequent rising-edge. At all other data rates,
there are two clock cycles per bit and every second falling edge of the master
clock marks a bit boundary and the data is clocked in on the rising edge of CLK,
three quarters of the way into the bit cell. See Figure 13 for timing.

In GCI format, when running at 16.384 MHz, data is clocked out on the rising

edge and is clocked in on the subsequent falling edge. At all other data rates,
there are two clock cycles per bit and every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell. See Figure 14 for timing.

INPUT FRAME OFFSET SELECTION

Input frame offset selection allows the channel alignment of individual input

streams to be offset with respect to the output stream channel alignment. Although
all input data comes in at the same speed, delays can be caused by variable
path serial backplanes and variable path lengths which may be implemented
in large centralized and distributed switching systems. Because data is often
delayed, this feature is useful in compensating for the skew between input
streams.

Each input stream can have its own delay offset value by programming the

frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5
master clock (CLK) periods forward with a resolution of ½ clock period, see
Table 9. The output frame cannot be adjusted.

SERIAL INPUT FRAME ALIGNMENT EVALUATION

The IDT72V71650 provides the Frame Evaluation input to determine

different data input delays with respect to the frame pulse FP. A measurement
cycle is started by setting the Start Frame Evaluation bit of the Control Register
LOW for at least one frame. When the Start Frame Evaluation bit in the Control
Register is changed from LOW to HIGH, the evaluation starts. Two frames later,
the Complete Frame Evaluation bit of the Frame Alignment Register changes
from LOW to HIGH to signal that a valid offset measurement is ready to be read
from bits 0 to 11 of the Frame Alignment Register. The Start Frame Evaluation
bit must be set to zero before a new measurement cycle is started.

In ST-BUS

mode, the falling edge of the frame measurement signal (Frame

Evaluation) is evaluated against the falling edge of the ST-BUS

frame pulse.

In GCI mode, the rising edge of Frame Evaluation is evaluated against the rising
edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of
the Frame Alignment Register.

MEMORY BLOCK PROGRAMMING

The IDT72V71650 provides users with the capability of initializing the entire

Connection Memory block in two frames. To set bits 14 and 15 of every
Connection Memory location, first program the desired pattern in the Block
Programming Data Bits (BPD 1-0), located in bits 7 and 8 of the Control Register.

The block programming mode is enabled by setting the Memory Block

Program bit of the Control Register HIGH. When the Block Programming Enable
bit of the Control Register is set to HIGH, the Block Programming Data will be
loaded into the bits 14 and 15 of every Connection Memory location. The other
Connection Memory bits (bit 0 to bit 13) are loaded with zeros. When the memory
block programming is complete, the device resets the Block Programming
Enable, Block Programming Data 1-0 and Memory Block Program bits to zero.

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

DELAY THROUGH THE IDT72V71650

The switching of information from the input serial streams to the output serial

streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabili-
ties on a per-channel basis. For voice applications, variable throughput delay
is best as it ensures minimum delay between input and output data. In wideband
data applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.

The delay through the device varies according to the type of throughput delay

selected in the MOD bits of the Connection Memory.

VARIABLE DELAY MODE (MOD1-0 = 0-0)

In this mode, the delay is dependent only on the combination of source and

destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V71650 is three time-slots. If the input
channel data is switched to the same output channel (channel n, frame p), it will
be output in the following frame (channel n, frame p+1). The same is true if the
input channel n is switched to output channel n+1 or n+2. If the input channel
n is switched to output channel n+3, n+4,..., the new output data will appear in
the same frame. Table 2 shows the possible delays for the IDT72V71650 in
Variable Delay mode.

CONSTANT DELAY MODE (MOD1-0 = 0-1)

In this mode, frame integrity is maintained in all switching configurations by

making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V71650, the minimum throughput delay achievable in Constant Delay
mode will be one frame plus one channel. See Table 1.

MICROPROCESSOR INTERFACE

The IDT72V71650's microprocessor interface looks like a standard RAM

interface to improve integration into a system. With a 15-bit address bus and a
16-bit data bus, reads and writes are mapped directly into Data and Connection
Memories and require only one clock cycle to access. By allowing the internal
memories to be randomly accessed in one cycle, the controlling microprocessor
has more time to manage other peripheral devices and can more easily and
quickly gather information and setup the switch paths. Table 4 shows the
mapping of the addresses into internal memory blocks.

MEMORY MAPPING

The address bus on the microprocessor interface selects the internal registers

and memories of the IDT72V71650.

The two most significant bits of the address select between the registers, Data

Memory, and Connection Memory. If A14 and A13 are HIGH, A12-A0 are used
to address the Data Memory. If A14 is HIGH and A13 is LOW, A12-A0 are used
to address Connection Memory. If A14 is LOW and A13 is HIGH A12-A0 are
used to select the Control Register, Frame Alignment Register, and Frame Offset
Registers. See Table 4 for mappings.

As explained in the Serial Data Interface Timing and Switching Configurations

sections, after system power-up, the Control Register should be programmed
immediately to establish the desired switching configuration.

The data in the Control Register consists of the Memory Block Programming

bit, the Block Programming Data bits, the Begin Block Programming Enable,
the Output Stand By, Start Frame Evaluation, Output Enable Indication, and Data
Rate Select bits. As explained in the Memory Block Programming section, the
Block Programming Enable begins the programming if the Memory Block
Program bit is enabled. This allows the entire Connection Memory block to be
programmed with the Block Programming Data bits. If the ODE pin is LOW, the
Output Stand By bit enables (if HIGH) or disables (if LOW) all TX output drivers.
If the ODE pin is HIGH, the Output Stand By bit is ignored and all TX output drivers
are enabled.

SOFTWARE RESET
The Software Reset serves the same function as the hardware reset. As with
the hard reset, the Software Reset must also be set HIGH for 20ns before
bringing the Software Reset LOW again for normal operation. Once the Software
Reset is LOW, internal registers and other memories may be read or written.
During Software Reset, the microprocessor port is still able to read from all
internal memories. The only write operation allowed during a Software Reset
is to the Software Reset bit in the Control Register to complete the Software Reset.

CONNECTION MEMORY CONTROL

If the ODE pin and the Output Stand By bit are LOW, all output channels will

be in three-state. See Table 3 for detail.

If MOD1-0 of the Connection Memory is 1-0 accordingly, the output channel

will be in Processor Mode. In this case the lower eight bits of the Connection
Memory are output each frame until the MOD1-0 bits are changed. If MOD
1-0 of the Connection Memory are 0-1 accordingly, the channel will be in
Constant Delay Mode and bits 12-0 are used to address a location in Data
Memory. If MOD1-0 of the Connection Memory are 0-0, the channel will be in
Variable Delay Mode and bits 12-0 are used to address a location in Data
Memory. If MOD 1-0 of the Connection Memory are 1-1, the channel will be
in High-Impedance mode and that channel will be in three-state.

OUTPUT ENABLE INDICATION

The IDT72V71650 has the capability to indicate the state of the outputs (active)

or three-state) by enabling the Output Enable Indication in the Control Register.
In the Output Enable Indication mode however, only half of the output streams
are available. If this same capability is desired with all 32 streams, this can be
accomplished by using two IDT72V71650 or one IDT72V71660 devices. In
one device, the All Output Enable bit is set to a one while in the other the All Output
Enable is set to zero. In this way, one device acts as the switch and the other
as a three-state control device, see Figure 4. It is important to note if the TSI device
is programmed for All Output Enable and the Output Enable Indication is also
set, the device will be in the All Output Enable mode not Output Enable Indication.

INITIALIZATION OF THE IDT72V71650

After power up, the state of the Connection Memory is unknown. As such,

the outputs should be put in high-impedance by holding the ODE pin LOW. While
the ODE is LOW, the microprocessor can initialize the device by using the Block
Programming feature and program the active paths via the microprocessor bus.
Once the device is configured, the ODE pin (or Output Stand By bit depending
on initialization) can be switched to enable the TSI switch.

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

TABLE 1

-- CONSTANT THROUGHPUT

DELAY VALUE

TABLE 2

-- VARIABLE THROUGHPUT

DELAY VALUE

Delay for Constant Throughput Delay Mode

Input Rate

(m output channel number)

(n input channel number)

2.048Mb/s

32 + (32 n) +m time-slots

4.096Mb/s

64 + (64 n) +m time-slots

8.192Mb/s

128 + (128 n) +m time-slots

16.384Mb/s

256 + (256 n) +m time-slots

Delay for Variable Throughput Delay Mode

Input Rate

(m output channel number; n input channel number)

n+2

m > n+2

2.048Mb/s

32 (n-m) time-slots

(m-n) time-slots

4.096Mb/s

64 (n-m) time-slots

(m-n) time-slots

8.192Mb/s

128 (n-m) time-slots

(m-n) time-slots

16.384Mb/s

256 (n-m) time-slots

(m-n) time-slots

TABLE 4 --

INTERNAL REGISTER AND ADDRESS MEMORY MAPPING

NOTE: Unused STA and CH bits should be set to zero.

A14

A13

A12

A11

A10

R/W

Location

STA4

STA3

STA2

STA1

STA0

CH7

CH6

CH5

CH4

CH3

CH2

CH1 CH0

Data Memory

STA4

STA3

STA2

STA1

STA0

CH7

CH6

CH5

CH4

CH3

CH2

CH1 CH0

R/W

Connection Memory

R/W

Control Register

Frame Align Register

R/W

Frame Offset Register 0

R/W

Frame Offset Register 1

R/W

Frame Offset Register 2

R/W

Frame Offset Register 3

R/W

Frame Offset Register 4

R/W

Frame Offset Register 5

R/W

Frame Offset Register 6

R/W

Frame Offset Register 7

TABLE 3

-- OUTPUT HIGH-IMPEDANCE CONTROL

Bits MOD1-0 Values in

ODE pin

OSB bit in Control

Output Status

Connection Memory

Register

1 and 1

Don't Care

Per-channel

High-Impedance

Any, other than 1 and 1

High-Impedance

Any, other than 1 and 1

Enable

Any, other than 1 and 1

Enable

Any, other than 1 and 1

Enable

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

TABLE 5

-- CONTROL REGISTER (CR) BITS

Reset Value:

0000

BIT

NAME

DESCRIPTION

SRS

A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.

(Software Reset)

OEI

When 1, the TX16-31/OEI0-15 pins will be OEI0-15 and reflect the active or high-impedance state of their corresponding output data

(Output Enable Indication)

streams. When 0, this feature is disabled and these pins are used as output data streams TX16-31.

OEPOL

When 1, a one on an Output Enable Indication pin denotes an active state on the output data stream; zero on an Output Enable Indication

(Output Enable Polarity)

pin denotes high-impedance state. When 0, a one on an Output Enable Indication pin denotes high-impedance and a zero denotes
an active state.

AOE

When 1, TX0-31 will behave as OEI0-31 accordingly. These outputs will reflect the active or high-impedance state of the

(All Output Enables)

corresponding output data streams (TX0-31) in another IDT72V71650 if programmed identically. When 0, the TSI operates in the
normal switch mode.

11-10

Unused

Must be zero for normal operation.

MBP

When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory HIGH bits, bit

(Memory Block Program)

14 to bit 15. When 0, this feature is disabled.

8-7

BPD1-0

These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature

(Block Programming

is activated. After the Memory Block Program bit in the Control Register is set to 1 and the Block Programming Enable is set to 1,

Data)

the contents of the bits Block Programming Data1-0 are loaded into bit 15 and 14 of the Connection Memory. Bit 13 to bit 0 of the
Connection Memory are set to 0.

BPE

A zero to one transition of this bit enables the memory block programming function. The Block Programming Enable and

(Begin Block

Block Programming Data1-0 bits in the Control Register have to be defined in the same write operation. Once the Block

Programming Enable)

Programming Enable bit is set HIGH, the device requires two frames to complete the block programming. After the programming
function has finished, the Block Programming Enable, Memory Block Program and Block Programming Data 1-0 bits will be reset
to zero by the device to indicate the operation is complete.

OSB

When ODE = 0 and Output Stand By = 0, the output drivers of the transmit serial streams are in high-impedance mode. When

(Output Stand By)

either ODE = 1 or Output Stand By =1 the output serial streams drivers function normally.

SFE

A zero to one transition in this bit starts the Frame Evaluation procedure. When the Complete Frame Evaluation bit in the Frame Alignment

(Start Frame Evaluation)

Register changes from zero to one, the evaluation procedure stops. To start another Frame Evaluation cycle, set this bit to zero for

at least one frame.

3-2

Unused

Must be zero for normal operation.

1-0

DR1-0

DR1

DR0

Data Rate

Master Clock

2.048Mb/s

4.096 MHz

4.096Mb/s

8.192 MHz

8.192Mb/s

16.384 MHz

16.384Mb/s

16.384 MHz

SRS

OEI

OEPOL

AOE

MBP

BPD1

BPD0

BPE

OSB

SFE

DR1

DR0

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

Figure 1. Example for Frame Alignment Measurement

TABLE 7

-- FRAME ALIGNMENT REGISTER (FAR) BITS

ST-BUS

Frame

CLK

Offset Value

FE Input

GCI Frame

CLK

Offset Value

FE Input

(FD[10:0] = 06

)

(FD11 = 0, sample at CLK LOW phase)

(FD[10:0] = 09

)

(FD11 = 1, sample at CLK HIGH phase)

5906 drw04

Bit

Name

Description

15-13

Unused

Must be zero for normal operation.

CFE (Complete

When Complete Frame Evaluation = 1, the Frame Evaluation is completed and bits FD11 to FD0 bits contains a valid frame alignment offset.

Frame Evaluation)

This bit is reset to zero, when Start Frame Evaluation bit in the Control Register is changed from 1 to 0.

FD11

The falling edge of Frame Evaluation (or rising edge for GCI mode) is sampled during the CLK-HIGH phase (FD11 = 1) or during the CLK-LOW

(Frame Delay Bit 11) phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle. This bit is reset to zero when the Start Frame Evaluation bit

of the Control Register changes from 1 to 0.

10-0

FD10-0

The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the Start Frame Evaluation

(Frame Delay Bits)

bit of the Control Register changes from 1 to 0. (FD10 MSB, FD0 LSB)

Reset Value:

0000

CFE

FD11

FD10

FD9

FD8

FD7

FD6

FD5

FD4

FD3

FD2

FD1

FD0

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

TABLE 8

-- FRAME INPUT OFFSET REGISTER (FOR) BITS

NOTE:
1. n denotes an input stream number from 0 to 31.

FOR0 Register

OF32

OF31

OF30

DLE3

OF22

OF21

OF20

DLE2

OF12

OF11

OF10

DLE1

OF02

OF01

OF00

DLE0

FOR1 Register

OF72

OF71

OF70

DLE7

OF62

OF61

OF60

DLE6

OF52

OF51

OF50

DLE5

OF42

OF41

OF40

DLE4

FOR2 Register

OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10

OF92

OF91

OF90

DLE9

OF82

OF81

OF80

DLE8

FOR3 Register

OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130

DLE13 OF122 OF121 OF120 DLE12

FOR4 Register

OF192 OF191 OF190 DLE19 OF182 OF181 OF180 DLE18 OF172 OF171 OF170

DLE17 OD162 OD161 OF160 DLE16

FOR5 Register

OF232 OF231 OF230 DLE23 OF222 OF221 OF220 DLE22 OF212 OF211 OF210

DLE21 OF202 OF201 OF200 DLE20

FOR6 Register

OF272 OF271 OF270 DLE27 OF262 OF261 OF260 DLE26 OF252 OF251 OF250

DLE25 OF242 OF241 OF240 DLE24

FOR7 Register

OF312 OF311 OF310 DLE31 OF302 OF301 OF300 DLE30 OF292 OF291 OF290

DLE29 OF280 OF281 OF280 DLE28

Name

(1)

Description

OFn2, OFn1, OFn0

These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame.

(Offset Bits 2, 1 & 0)

The input frame offset can be selected to +7.5 clock periods from the point where the external frame pulse input signal is applied to the FP
input of the device. See Figure 2.

DLEn

ST-BUS

and

DLEn = 0, offset is on the clock boundary

GCI mode:

DLEn = 1, offset is a half clock cycle off of the clock boundary.

Reset Value:0000

H for all FOR registers.

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

Measurement Result from

Corresponding

Input Stream

Frame Delay Bits

Offset Bits

Offset

FD11

FD2

FD1

FD0

OFn2

OFn1

OFn0

DLEn

No clock period shift (Default)

+ 0.5 clock period shift

+ 1.0 clock period shift

+ 1.5 clock period shift

+ 2.0 clock period shift

+ 2.5 clock period shift

+ 3.0 clock period shift

+ 3.5 clock period shift

+ 4.0 clock period shift

+ 4.5 clock period shift

+5.0 clock period shift

+5.5 clock period shift

+6.0 clock period shift

+6.5 clock period shift

+7.0 clock period shift

+7.5 clock period shift

TABLE 9

-- OFFSET BITS (OFn2, OFn1, OFn0, DLEn) & FRAME DELAY BITS

(FD11, FD2-0)

Figure 2. Examples for Input Offset Delay Timing in 16.384Mb/s mode

FP (ST-BUS

)

RX Stream
(16.384 Mb/s)

5906 drw05

Bit 7

Bit 6

offset = 0, DLE = 0

offset = 1, DLE = 0

offset = 0, DLE = 1

FP (GCI)

Bit 0

offset = 0, DLE = 0

offset = 1, DLE = 0

offset = 0, DLE = 1

Bit 1

Bit 0

Bit 2

Bit 1

Bit 2

Bit 1

Bit 2

RX Stream
(16.384 Mb/s)

Bit 6

Bit 5

Bit 4

Bit 5

Bit 6

Bit 7

Bit 5

Bit 4

RX Stream
(16.384 Mb/s)

CLK

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

TABLE 10

-- IDENTIFICATION REGISTER DEFINITIONS

INSTRUCTION FIELD

VALUE

DESCRIPTION

Revision Number (31:28)

0x0

Reserved for version number

IDT Device ID (27:12)

0x435

Defines IDT part number

IDT JEDEC ID (11:1)

0x33

Allows unique identification of device vendor as IDT

ID Register Indicator Bit (Bit 0)

Indicates the presence of an ID register

REGISTER NAME

BIT SIZE

Instruction (IR)

Bypass (BYR)

Identification (IDR)

Boundary Scan (BSR)

Note(1)

TABLE 11

-- SCAN REGISTER SIZES

NOTES:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on

the IDT website (www.idt.com), or by contacting your local IDT sales representative.

JTAG SUPPORT

The IDT72V71650 JTAG interface conforms to the Boundary-Scan standard

IEEE-1149.1. This standard specifies a design-for-testability technique called
Boundary-Scan test (BST). The operation of the boundary-scan circuitry is
controlled by an external test access port (TAP) Controller.

TEST ACCESS PORT (TAP)

The Test Access Port (TAP) provides access to the test functions of the

IDT72V71650. It consists of three input pins and one output pin.

·Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with

any on-chip clock and thus remains independent. The TCK permits shifting of
test data into or out of the Boundary-Scan register cells concurrently with the
operation of the device and without interfering with the on-chip logic.

·Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP

Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to V

when it is not

driven from an external source.

·Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register

or into a test data register, depending on the sequence previously applied to
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.

·Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the

contents of either the instruction register or data register are serially shifted out
through the TDO pin on the falling edge of each TCK pulse. When no data
is shifted through the boundary scan cells, the TDO driver is set to a
high-impedance state.

·Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to V

when it

is not driven from an external source.

INSTRUCTION REGISTER

In accordance with the IEEE-1149.1 standard, the IDT72V71650 uses public

instructions. The IDT72V71650 JTAG interface contains a four-bit instruction
register. Instructions are serially loaded into the instruction register from the TDI
when the TAP Controller is in its shift-IR state. Subsequently, the instructions are
decoded to achieve two basic functions: to select the test data register that may
operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register
scanning. See Table 12 below for Instruction decoding.

TEST DATA REGISTER

As specified in IEEE-1149.1, the IDT72V71650 JTAG Interface contains two

test data registers:

·The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells

arranged to form a scan path around the boundary of the IDT72V71650 core
logic.

·The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path

from TDI to TDO. The IDT72V71650 boundary scan register bits are shown
in Table 14. Bit 0 is the first bit clocked out. All three-state enable bits are active
HIGH.

ID CODE REGISTER
As specified in IEEE-1149.1, this instruction loads the IDR with the Revision
Number, Device ID, and ID Register Indicator Bit. See Table 10.

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

TABLE 12

-- SYSTEM INTERFACE PARAMETERS

NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS and

TRST.

INSTRUCTION

CODE

DESCRIPTION

EXTEST

0000

Forces contents of the boundary scan cells onto the device outputs

(1)

. Places the boundary scan register (BSR) between TDI and TDO.

BYPASS

1111

Places the bypass register (BYR) between TDI and TDO.

IDCODE

0010

Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO.

HIGH-Z

0100

Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state.

CLAMP

0011

Places the bypass register (BYR) between TDI and TDO. Forces contents of the boundary scan cells onto the device outputs.

SAMPLE/PRELOAD

0001

Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs

(2)

and outputs

(1)

to be

captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary
scan cells via the TDI.

RESERVED

All other codes Several combinations are reserved. Do not use other codes than those identified above.

SYMBOL

PARAMETER

MIN.

MAX.

UNITS

JCYC

JTAG Clock Input Period

100

JCH

JTAG Clock High

JCL

JTAG Clock Low

JTAG Clock Rise Time

(1)

JTAG Clock Fall Time

(1)

JRST

JTAG Reset

JRSR

JTAG Reset Recovery

JCD

JTAG Data Output

JDC

JTAG Data Output Hold

JTAG Setup

JTAG Hold

TABLE 13 -- JTAG AC ELECTRICAL CHARACTERISTICS

(1,2,3,4)

NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

TCK

Device Inputs

(1)

TDI/TMS

JDC

JRSR

JCL

JCYC

JCH

JCD

JRST

Device Outputs

(2)

TDO

TRST

5906 drw07

Figure 3. JTAG Timing Specifications

NOTES:
1. Device inputs = All device inputs except TDI, TMS and

TRST.

2. Device outputs = All device outputs except TDO.

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

TABLE 14 -- BOUNDARY SCAN REGISTER BITS

TX28/OEI12

TX27/OEI11

TX26/OEI10

TX25/OEI9

TX24/OEI8

TX23/OEI7

TX22/OEI6

100

TX21/OEI5

101

102

TX20/OEI4

103

104

TX19/OEI3

105

106

TX18/OEI2

107

108

TX17/OEI1

109

110

TX16/OEI0

111

112

RX23

113

RX22

114

RX21

115

RX20

116

RX19

117

RX18

118

RX17

119

RX16

120

RX15

121

RX14

122

RX13

123

RX12

124

RX11

125

RX10

126

RX9

127

RX8

128

TX15

129

130

TX14

131

132

TX13

133

134

TX12

135

136

TX11

137

138

TX10

139

140

TX9

141

142

TX8

143

144

TX7

145

146

TX6

147

148

TX5

149

150

TX4

151

152

TX3

153

154

TX2

155

156

TX1

157

158

TX0

159

160

RX7

161

RX6

162

RX5

163

RX4

164

RX3

165

RX2

166

RX1

167

RX0

168

ODE

RESET

CLK

FE(HCLK)

WFPS

A10

A11

A12

A13

A14

DTA

D15

D14

D13

D12

D11

D10

RX31

RX30

RX29

RX28

RX27

RX26

RX25

RX24

TX31/OEI15

TX30/OEI14

TX29/OEI13

Boundary Scan Bit 0 to bit 168

Device Pin

Input

Output

Three-State

Scan Cell

Control

Boundary Scan Bit 0 to bit 168

Device Pin

Input

Output

Three-State

Scan Cell

Control

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

Symbol

Parameter

Min.

Typ.

Max.

Units

(2)

Supply Current

@ 2.048Mb/s

@ 4.096Mb/s

@ 8.192Mb/s

@ 16.384Mb/s

(3,4)

Input Leakage (input pins)

µA

(3,4)

High-impedance Leakage

µA

(5)

Output HIGH Voltage

2.4

(6)

Output LOW Voltage

0.4

DC ELECTRICAL CHARACTERISTICS

NOTES:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Outputs unloaded.
3. 0

V V

4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V).
5. IOH = 10 mA.
6. IOL = 10 mA.

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

-0.5

+4.0

Voltage on Digital Inputs

GND -0.3

+0.3

Current at Digital Outputs

-50

Storage Temperature

-55

+125

° C

Package Power Dissapation

NOTE:
1. Exceeding these values may cause permanent damage. Functional operation

under these conditions is not implied.

ABSOLUTE MAXIMUM RATINGS

(1)

RECOMMENDED OPERATING
CONDITIONS

(1)

NOTE:
1. Voltages are with respect to Ground unless otherwise stated.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Positive Supply

3.0

3.3

3.6

Input HIGH Voltage

2.0

Input LOW Voltage

-0.3

0.8

Operating Temperature

-40

+85

°C

Industrial

INDUSTRIAL TEMPERATURE RANGE

IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192

AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLOCK

Symbol

Parameter

Min.

Typ.

Max.

Units

FPW

Frame Pulse Width (ST-BUS

, GCI)

Bit rate = 2.048Mb/s

295

Bit rate = 4.096Mb/s

145

Bit rate = 8.192Mb/s or 16.384Mb/s

FPS

Frame Pulse Setup time before CLK falling (ST-BUS

or GCI)

FPH

Frame Pulse Hold Time from CLK falling (ST-BUS

or GCI)

CLK Period
Bit rate = 2.048Mb/s

190

244

300

Bit rate = 4.096Mb/s

110

122

150

Bit rate = 8.192Mb/s or 16.384Mb/s

CLK Pulse Width HIGH
Bit rate = 2.048Mb/s

122

150

Bit rate = 4.096Mb/s

Bit rate = 8.192Mb/s or 16.384Mb/s

CLK Pulse Width LOW
Bit rate = 2.048Mb/s

122

150

Bit rate = 4.096Mb/s

Bit rate = 8.192Mb/s or 16.384Mb/s

HFPW

Wide Frame Pulse Width
HCLK = 4.096Mb/s

244

HFPS

Frame Pulse Setup Time before HCLK @ 4.096 MHz falling

150

HFPH

Frame Pulse Hold Time from HCLK @ 4.096 MHz falling

150

HCP

HCLK Period
@ 4.096 MHz

190

244

300

HCH

HCLK Pulse Width HIGH
@ 4.096Mb/s

110

122

150

HCL

HCLK Pulse Width LOW
@ 4.096Mb/s

110

122

150

, t

HCLK Rise/Fall Time

DIF

Delay between falling edge of HCLK and falling edge of CLK

-10

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