MAY 2003

3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256

IDT72V8985

DSC-5707/4

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS

is a trademark of Mitel Corp.

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

256 x 256 channel non-blocking switch

Automatic signal identification (ST-BUS

, GCI)

8 RX inputs--32 channels at 64 Kbit/s per serial line

8 TX outputs--32 channels at 64 Kbit/s per serial line

Three-state serial outputs

Microprocessor Interface (8-bit data bus)

Frame Integrity for data applications

3.3V Power Supply

Available in 44-pin Plastic Leaded Chip Carrier (PLCC),
48-pin Small Shrink Outline Package (SSOP), and 44-pin Plastic
Quad Flatpack (PQFP)

·
·
·
·
·

Operating Temperature Range -40

°°
°°
°C to +85°°°°°C

·
·
·
·
·

3.3V I/O with 5V Tolerant Inputs

DESCRIPTION:

The IDT72V8985 is a ST-BUS

/GCI compatible digital switch controlled by

a microprocessor. The IDT72V8985 can handle as many as 256, 64 Kbit/s input
and output channels. Those 256 channels are divided into 8 serial inputs and
outputs, each of which consists of 32 channels. The IDT72V8985 provides per-
channel variable or constant throughput delay modes and microprocessor read

and write access to individual channels. As an important function of a digital
switch is to maintain sequence integrity and minimize throughput delay, the
IDT72V8985 is an ideal solution for most switching needs.

FUNCTIONAL DESCRIPTION

Frame sequence, constant throughput delay, and guaranteed minimum

delay are high priority requirements in today's integrated data and multimedia
networks. The IDT72V8985 provides these functions on a per-channel basis
using a standard microprocessor control interface. Each of the eight serial lines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.

In Processor Mode, the microprocessor can access the input and output time

slots to control other devices such as ISDN transceivers and trunk interfaces.
Supporting both GCI and ST-BUS

formats, IDT72V8985 has incorporated an

internal circuit to automatically identify the polarity and format of the frame
synchronization.

A functional block diagram of the IDT72V8985 device is shown on page 1.

The serial streams operate continuously at 2.048 Mb/s and are arranged in
125

µs wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and

eight output (TX0-7) serial streams are provided in the IDT72V8985 device
allowing a complete 256 x 256 channel non-blocking switch matrix to be
constructed. The serial interface clock for the device is 4.096 MHz.

Microprocessor Interface

Control Register

Timing
Unit

RX0

RX1

RX2

RX3

RX4

RX5

RX6

RX7

TX0

TX1

TX2

TX3

TX4

TX5

TX6

TX7

ODE

F0i

C4i

W A0/

GND

CCO

DTA D0/

5707 drw01

Receive
Serial Data
Streams

Data
Memory

Output MUX

Connection
Memory

Transmit
Serial Data
Streams

RESET

(1)

NOTE:

1. The

RESET Input is only provided on the SSOP package.

Commercial Temperature Range

IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256

5707 drw02

INDEX

RX2

RX1

RX0

DTA

TX0

TX1

TX2

DNC

(1)

CCO

ODE

TX3

TX4

TX5

TX6

TX7

GND

RX3

RX4

RX5

RX6

RX7

F0i

C4i

DNC

(1)

DNC

(1)

DNC

(1)

PIN CONFIGURATION

PLCC: 0.05in. pitch, 0.65in. x 0.65in

(J44-1, order code: J)

TOP VIEW

DTA

CCO

ODE

TX0

TX1

TX2

TX3

TX4

TX5

TX6

TX7

GND

RX1

RX2

RX3

RX4

RX5

RX6

F0i

C4i

RX7

RX0

2
4

GND

RESET

(2)

GND

5707 drw04

DNC

(1)

DNC

(1)

DNC

(1)

DNC

(1)

NOTES:
1. DNC - Do Not Connect
2. The

RESET Input is only provided on the SSOP package.

PQFP: 0.80mm pitch, 10mm x 10mm

(DB44-1, order code: DB)

TOP VIEW

5707 drw03

INDEX

RX2

RX1

RX0

DTA

TX0

TX1

TX2

DNC

(1)

CCO

ODE

TX3

TX4

TX5

TX6

TX7

GND

RX3

RX4

RX5

RX6

RX7

F0i

C4i

DNC

(1)

DNC

(1)

DNC

(1)

Package Type

Reference Identifier

Order Code

SSOP: 0.025in. pitch, 0.625in. x 0.295in.

SO48-1

Commercial Temperature Range

IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256

PIN DESCRIPTIONS

SYMBOL

NAME

I/O

DESCRIPTION

GND

Ground.

Ground Rail.

+3.3 Volt Power Supply.

DTA

Data Acknowledgment

This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this

(Open Drain)

output.

RX0-7

RX Input 0 to 7

Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.

F0i

Frame Pulse

This input accepts and automatically identifies frame synchronization signals formatted according to different
backplane specifications such as ST-BUS

and

GCI.

C4i

Clock

4.096 MHz serial clock for shifting data in and out of the data streams.

A0-A5

Address 0 to 5

These lines provide the address to IDT72V8985 internal registers.

Data Strobe

This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.

Read/Write

This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.

Chip Select

Active LOW input enabling a microprocessor read or write of control register or internal memories.

D0-D7

Data Bus 0 to 7

I/O

These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.

TX0-7

TX Outputs 0 to 7

Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.

(Three-state Outputs)

ODE

Output Drive Enable

This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.

CCO

Control Channel Output

This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the
contents of the CCO bit in the Connection Memory HIGH locations.

RESET

Device Reset

This input (active LOW) puts the IDT72V8985 in its reset state that clears the device internal counters,

(Schmitt Trigger Input)

registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the

RESET pin must be held LOW for a minimum of 100ns to reset the device.

Commercial Temperature Range

IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256

The received serial data is internally converted to parallel by the on chip

serial-to-parallel converters and stored sequentially in a 256-position Data
Memory. By using an internal counter that is reset by the input 8 KHz frame pulse,
F0i, the incoming serial data streams can be framed and sequentially addressed.

Depending on the type of information to be switched, the IDT72V8985 device

can be programmed to perform time slot interchange functions with different
throughput delay capabilities on a per-channel basis. The Variable Delay
mode, most commonly used for voice applications, can be selected ensuring
minimum throughput delay between input and output data. In Constant Delay
mode, used in multiple or grouped channel data applications, the integrity of the
information through the switch is maintained.

CONNECTION MEMORY

Data to be output on the serial streams may come from two sources: Data

Memory or Connection Memory. The Connection Memory is split into HIGH
and LOW parts and is associated with particular TX output streams. In Processor
Mode, data output on the TX streams is taken from the Connection Memory Low
and originates from the microprocessor (Figure 2). Where as in Connection
Mode (Figure 1), data is read from Data Memory and originated from the
incoming RX streams. Data destined for a particular channel on the serial output
stream is read internally during the previous channel time slot to allow time for
memory access and internal parallel-to-serial conversion.

CONNECTION MODE

In Connection Mode, the addresses of input source for all output channels

are stored in the Connection Memory Low. The Connection Memory Low
locations are mapped to corresponding 8-bit x 32-channel output. The contents
of the Data Memory at the selected address are then transferred to the parallel-
to-serial converters before being output. By having the output channel to specify
the input channel through the Connection Memory, input channels can be
broadcast to several output channels.

PROCESSOR MODE

In Processor Mode the CPU writes data to the Connection Memory Low

locations which correspond to the output link and channel number. The contents
of the Connection Memory Low are transferred to the parallel-to-serial
converter one channel before it is to be output and are transmitted each frame
to the output until it is changed by the CPU.

CONTROL

The Connection Memory High bits (Table 4) control the per-channel

functions available in the IDT72V8985. Output channels are selected into
specific modes such as: Processor Mode or Connection mode, Variable or
Constant throughput delay modes, Output Drivers Enabled or in three-state
condition. There is also one bit to control the state of the CCO output pin.

OUTPUT DRIVE ENABLE (ODE)

The ODE pin is the master output three-state control pin. If the ODE input

is held LOW all TDM (Time Division Multiplexed) outputs will be placed in high
impedance regardless Connection Memory High programming. However, if
ODE is HIGH, the contents of Connection Memory High control the output state
on a per-channel basis.

SERIAL INTERFACE TIMING

The IDT72V8985 master clock (

C4i) is 4.096 MHz signal allowing serial data

link configuration at 2.048 Mb/s to be implemented. The IDT72V8985 can
automatically detect the presence of an input frame pulse, identify the type of
backplane present on the serial interface, and format the synchronization pulse
according to ST-BUS

or GCI interface specifications (active HIGH in GCI or

active LOW in ST-BUS

). Upon determining the correct interface Connected

to the serial port, the internal timing unit establishes the appropriate serial data
bit transmit and sampling edges. In ST-BUS

mode, every second falling edge

of the 4.096 MHz clock marks a boundary and the input data is clocked in by
the rising edge, three quarters of the way into the bit cell. In GCI mode every
second rising edge of the 4.096 MHz clock marks the bit boundary while data
sampling is performed during the falling edge, at three quarters of the bit
boundaries.

DELAY THROUGH THE IDT72V8985

The transfer of information from the input serial streams to the output serial

streams results in a delay through the device. The delay through the
IDT72V8985 device varies according to the mode selected in the

V/C bit of the

Connection Memory High.

VARIABLE DELAY MODE

The delay in Variable Delay Mode is dependent only on the combination

of source and destination on the input and output streams. The minimum delay
achievable in the IDT72V8985 device is three time slots. In the IDT72V8985
device, the information that is to be output in the same channel position as the
information is input (position n), relative to frame pulse, will be output in the
following frame (channel n, frame n+1). The same occurs if the input channels
succeeding (n+1, n+2) the channel position as the information is input.

The information switched to the third time slot after the input has entered the

device (for instance, input channel 0 to output channel 3 or input channel 30 to
output channel 1), is always output three channels later.

Any switching configuration that provides three or more time slots between

input and output channels, will have a throughput delay equal to the difference
between the output and input channels; i.e., the throughput delay will be less
than one frame. Table 1 shows the possible delays for the IDT72V8985 device
in Variable Delay Mode. An example is shown in Figure 3.

CONSTANT DELAY MODE

In this mode frame integrity is maintained in all switching configurations by

Figure 2. Processor Mode

Figure 1. Connection Mode

Receive

Serial Data

Streams

5707 drw05

Transmit

Serial Data

Streams

Data
Memory

Connection
Memory

5707 drw06

Microprocessor

Receive

Serial Data

Streams

Transmit

Serial Data

Streams

Data
Memory

Connection
Memory

FUNCTIONAL DESCRIPTION (Cont'd)

Commercial Temperature Range

IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256

making use of a multiple Data Memory buffer technique where input channels
written in any of the buffers during frame N will be read out during frame N+2.
In the IDT72V8985, the minimum throughput delay achievable in Constant
Delay mode will be 32 time slots; for example, when input time slot 32 (channel
31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay
is achieved when the first time slot in a frame (channel 0) is switched to the last
time slot in the frame (channel 31), resulting in 94 time slots of delay (see
Figure 4).

To summarize, any input time slot from input frame N will be always switched

to the destination time slot on output frame N+2. In Constant Delay mode the
device throughput delay is calculated according to the following formula:

DELAY=[32+(32-IN)+(OUT-1)]

IN =the number of the input time slot (from 1 to 32)
OUT = the number of the output time slot (from 1 to 32).

MICROPROCESSOR PORT

The IDT72V8985 microprocessor port is a non-multiplexed bus architec-

ture. The parallel port consists of an 8-bit parallel data bus (D0-D7), six address
input lines (A0-A5) and four control lines (

CS, DS, R/W and DTA). This parallel

microport allows the access to the Control Registers, Connection Memory Low,
Connection Memory High, and the Data Memory. All locations are read/written
except for the Data Memory, which can be read only.

Accesses from the microport to the Connection Memory and the Data

Memory are multiplexed with accesses from the input and output TDM ports.
This can cause variable Data Acknowledge delays (

DTA). In the IDT72V8985

device, the

DTA output provides a maximum acknowledgment delay of 800ns

for read/write operations in the Connection Memory. However, for operations
in the Data Memory (Processor Mode), the maximum acknowledgment delay
can be 1220ns.

SOFTWARE CONTROL

If the A5, A1, A0 address line inputs are LOW then the IDT72V8985 Internal

Control Register is addressed (see Table 2). If A5 input line is high, then the
remaining address input lines are used to select the 32 possible channels per
input or output stream. As explained in the Control Register description, the
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT72V8985 Data and
Connect memories. See Figure 5 for accessing internal memories.

The data in the control register consists of Memory Select and Stream

Address bits, Split Memory and Processor Enable bits (Table 3). In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory LOW. The Memory Select bits allow the
Connection Memory High or LOW or the Data Memory to be chosen, and the
Stream Address bits define internal memory subsections corresponding to input
or output streams.

The Processor Enable bit (bit 6) places every output channel on every

output stream in Processor Mode; i.e., the contents of the Connection Memory
LOW (CML, see Table 5) are output on the output streams once every frame
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8985
behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every
Connection Memory High (CMH, see Table 4) locations were set to HIGH,
regardless of the actual value. If PE is LOW, then bit 2 and 0 of each Connection
Memory High location operates normally. In this case, if bit 2 of the CMH is HIGH,
the associated TX output channel is in Processor Mode. If bit 2 of the CMH is
LOW, then the contents of the CML define the source information (stream and
channel) of the time slot that is to be switched to an output.

If the ODE input pin is LOW, then all the serial outputs are high-impedance.

If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) for that particular channel.

The contents of bit 1 (CCO) of each Connection Memory High Location (see

Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/
s output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit
on CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on
the CCO output is transmitted LOW. The contents of the 256 CCO bits of the CMH
are transmitted sequentially on to the CCO output pin and are synchronous to
the TX streams. To allow for delay in any external control circuitry the contents
of the CCO bit is output one channel before the corresponding channel on the
TX streams. For example, the contents of CCO bit in position 0 (corresponding
to TX0, CH0), is transmitted synchronously with the TX channel 31, bit 7. Bit 1's
of CMH for channel 1 of streams 0-7 are output synchronously with TX channel
0 bits 7-0.

INITIALIZATION

During the microprocessor initialization routine, the microprocessor should

program the desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two Connected TX
outputs drive the bus simultaneously. With the CMH setup, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.

The reset pin is designed to be used with board reset circuitry. During reset

the TX serial streams will be put into high-impedance and the state of internal
registers and counters will be reset. As the connection memory can be in any
state after a power up, the ODE pin should be used to hold the TX streams in
high-impedance until the per-channel output enable control in the connection
memory high is appropriately programmed. The main difference between ODE
and reset is, reset alters the state of the registers and counters where as ODE
controls only the high-impedance state of the TX streams.

RESET input is only

provided on the SSOP packages.

TABLE 1

VARIABLE DELAY MODE

Input Channel

Output Channel

Throughput Delay

m=n, n+1 or n+2

m-n+32 time slot

m>n+2

m-n time slot

m<n

32-(n-m) time slot

TABLE 2

ADDRESS MAPPING

LOCATION

Control Register

Channel 0

Channel 1

Channel 31

Commercial Temperature Range

IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256

TABLE 4

CONNECTION MEMORY HIGH

TABLE 5

CONNECTION MEMORY LOW

TABLE 3

CONTROL REGISTER

Bit

Name

Description

SM (Split Memory)

When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory, except when
the Control Register is accessed again. The Memory Select bits need to specify the memory for the operations.

PE (Processor Mode)

When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when in high-
impedance. When 0, the Connection Memory bits for each channel determine what is output.

unused

4-3

MS1-MS0

0-0 - Not to be used.

(Memory Select Bits)

0-1 - Data Memory (read only from the CPU)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH

2-0

STA2-0

The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the

(Stream Address Bits)

subsection of memory made accessible for subsequent operations.

MS1

MS0

STA2

STA1

STA0

x = don't care

Bit

Name

Description

7,5,4,3

unused

V/C (Variable/Constant

This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes on a per-channel basis.

Throughput Delay Mode)

When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel

(Channel Source)

and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the

Data Memory and determine the source of the connection to the location's channel and stream.

CCO (CCO Bit)

This bit drives a bit time on the CCO output pin.

OE (Output Enable)

This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to
be made high-impedance, allowing switch matrices to be constructed. A HIGH enables the driver and a LOW disables it.

V/C

CCO

x = don't care

Bit

Name

Description

7-5

SAB2-0

(1)

These three bits are used to select eight source streams for the Connection.

(Source Stream Address Bits)

4-0

(1)

CAB2-0

(1)

These five bits are used to select 32 different source channels for the Connection (the stream where the channel

(Source Channel Address Bits) is present is defined by bits SAB2-0). Bit 4 is the most significant bit.

SAB2

SAB1

SAB0

CAB4

CAB3

CAB2

CAB1

CAB0

NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with

this location. Otherwise, the bits are used as indicated to define the source of the Connection which is output on the channel and stream associated with this location.

Commercial Temperature Range

IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256

Test Point

Output

GND

VCC

GND

5707 drw09

S1 is open circuit except when testing output
levels or high impedance states.

S2 is switched to V

or GND when testing

output levels or high impedance states.

Figure 6. Output Load

RECOMMENDED OPERATING
CONDITIONS

DC ELECTRICAL CHARACTERISTICS

NOTE:
1. Typical figures are at 25

°C and are for design aid only; not guaranteed and not subject

to production testing.

NOTE:
1. Typical figures are at 25

°C and are for design aid only; not guaranteed and not subject to production testing.

Symbol

Parameter

Min.

Max.

Unit

- GND

-0.3

5.0

Voltage on Digital Inputs

GND - 0.3

+0.3

Voltage on Digital Outputs

GND - 0.3

+0.3

Current at Digital Outputs

Storage Temperature

-55

+125

° C

Package Power Dissapation

Symbol

Parameter

Min.

Typ.

(1)

Max.

Unit

Positive Supply

3.0

3.3

3.6

Input Voltage

Operating Temperature

-40

+85

°C

Commercial

Symbol

Parameter

Min.

Typ.

(1)

Max.

Units

Test Conditions

Supply Current

Outputs Unloaded

Input High Voltage

2.0

Input Low Voltage

0.8

Input Leakage (Inputs)

µA

between GND and V

Input Capacitance

Output High Voltage

2.4

= 10mA

Output High Current

Sourcing. V

= 0.8V

Output Low Voltage

0.4

= 5mA

Output Low Current

Sinking. V

= 0.4V

High Impedance Leakage

µA

between GND and V

Output Pin Capacitance

NOTE:
1. Exceeding these values may cause permanent damage. Functional operation under

these conditions is not implied.

ABSOLUTE MAXIMUM RATINGS

(1)

Commercial Temperature Range

IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256

C4i

TX0-7

CCO

5707 drw12

TX0-7

(GCI)

(ST-BUS

)

Bit Cell Boundary

TAZ

XCD

TZA

Figure 9. Serial Outputs and External Control

Figure 10. Output Driver Enable

OED

ODE

TX0-7

5707 drw13

OED

Figure 11. Reset

5707 drw14

ZDO

ZRS

RSZ

RPW

AC ELECTRICAL CHARACTERISTICS

(1)

SERIAL STREAM TIMING

Symbol

Characteristics

Min.

Typ.

(2)

Max.

Unit

Test Conditions

TAZ

TX0-7 Delay - Active to High Z

= 1K

(3)

, C

= 150pF

TZA

TX0-7 Delay - High Z to Active

= 150pF

OED

Output Driver Enable Delay

= 1K

(3)

, C

= 150pF

XCD

CCO Output Delay

= 150pF

RSZ

Reset to High Z

ZRS

High Z to Reset

ZDO

High Z to Valid Data

cycles

C4i cycles

RPW

Reset Pulse Width

100

= 1K

(3)

, C

= 150pF

NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25

°C and are for design aid only; not guaranteed and not subject to production testing.

3. High Impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to discharge C

Commercial Temperature Range

IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256

Figure 12. Motorola Non-Multiplexed Bus Timing

D0-D7

WRITE

5707 drw15

A0-A5

D0-D7

READ

DTA

VALID DATA

CSS

RWS

ADS

CSH

RWH

ADH

DHR

DSW

SWD

DDR

AKD

DHW

AKH

AC ELECTRICAL CHARACTERISTICS

(1)

MICROPROCESSOR TIMING

Symbol

Characteristics

Min.

Typ.

(2)

Max.

Unit

Test Conditions

CSS

CS Setup from DS Rising

RWS

W Setup from DS Rising

ADS

Add Setup from DS Rising

CSH

CS Hold after DS Falling

RWH

W Hold after DS Falling

ADH

Add Hold after DS Falling

DDR

Data Setup from

DTA Low on Read

= 150pF

DHR

Data Hold on Read

= 1K

(3)

, C

= 150pF

DSW

Data Setup on Write (Fast Write)

SWD

Valid Data Delay on Write (Slow Write)

122

DHW

Data Hold on Write

AKD

Acknowledgment Delay:

= 150pF

Reading Data Memory

560

1220

Reading/Writing Connection Memory

300/370

730/800

Writing to Control Register

Reading to Control Register

AKH

Acknowledgment Hold Time

= 1K

(3)

, C

= 150pF

NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25

°C and are for design aid only; not guaranteed and not subject to production testing.

3. High Impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to discharge C

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