INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
1
AUGUST 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4550/1
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: 24mA (A port)
Balanced Output Drivers: 12mA (B port)
IDT74ALVC162268
3.3V CMOS 12-BIT TO
24-BIT REGISTERED BUS
EXCHANGER WITH
3-STATE OUTPUTS
DESCRIPTION:
This registered bus exchanger is built using advanced dual metal CMOS
technology. This device is used for applications in which data must be
transferred from a narrow high-speed bus to a wide, lower-frequency bus.
The ALVC162268 device provides synchronous data exchange be-
tween the two ports. Data is stored in the internal registers on the low-to-
high transition of the clock (CLK) input when the appropriate clock-enable
(CLKEN) inputs are low. The select (SEL) line is synchronous with CLK
and selects 1B or 2B input data for the A outputs. For data transfer in the
A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with
a single storage register in the A-to-2B path. Proper control of these inputs
allows two sequential 12-bit words to be presented synchronously as a 24-
bit word on the B-port. Data flow is controlled by the active-low output
enables (OEA and OEB). These control terminals are registered to
synchronize the bus-direction changes with CLK.
The ALVC162268 has series resistors in the device output structure of
the "B" port which will significantly reduce line noise when used with light
loads. This driver has been designed to drive 12mA at the designated
threshold levels. The "A" port has a 24mA driver.
CLK EN2B
CLK
CLKE NA1
O EA
1
B
1
SE L
CLK ENA 2
C 1
1D
C1
1D
CE
1D
C1
A1
2
B
1
1 of 12 Channels
CLK EN1B
1
28
56
55
30
27
2
29
OEB
CE
1D
C1
CE
1D
C1
CE
1D
C1
CE
1D
C1
23
6
8
C1
1D
0
1
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN CONFIGURATION
FUNCTION TABLES
(1)
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
7
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
9
pF
C
OUT
I/O Port Capacitance
V
IN
= 0V
7
9
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
V
I
< 0 or V
I
> V
CC
I
OK
Continuous Clamp Current, V
O
< 0
50
mA
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
O EA
2
B
3
G ND
2
B
2
2
B
1
V
CC
A
1
A
2
G ND
A
3
A
4
A
5
A
6
A
8
A
9
G ND
A
10
A
11
A
12
V
CC
1
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
OE B
2
B
4
G ND
2
B
5
2
B
6
V
CC
2
B
7
2
B
8
2
B
9
2
B
10
2
B
11
2
B
12
G ND
1
B
11
1
B
10
1
B
9
1
B
8
G ND
1
B
7
1
B
6
1
B
5
G ND
1
B
3
S EL
25
26
27
28
32
31
30
29
GN D
1
B
4
CLKENA 1
CLK
A
7
1
B
2
V
CC
1
B
12
CLKE NA2
C LKE N2B
CLKEN1B
Inputs
Outputs
CLKENA1
CLKENA2
CLK
Ax
1Bx
2Bx
H
H
X
X
1B
0
(2)
2B
0
(2)
L
L
L
L
(3)
L
L
L
H
H
(3)
H
X
L
L
X
L
X
L
H
X
H
Inputs
Outputs
CLK
OEA
OEB
Ax
1Bx, 2Bx
H
H
Z
Z
H
L
Z
Active
L
H
Active
Z
L
L
Active
Active
OUTPUT ENABLE
A-TO-B STORAGE (OEB = L AND OEA = H)
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
3
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
= LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
3. Two CLK edges are needed to propagate data.
Pin Names
I/O
Description
Ax
(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU's address/data bus.
1Bx
(1:12)
I/O
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
2Bx
(1:12)
I/O
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
CLK
I
Clock Input
CLKENA1
I
Clock Enable Input for the A-1B Register. If CLKENA1 is LOW during the rising edge of CLK, data will be clocked into register A-1B
(Active LOW).
CLKENA2
I
Clock Enable Input for the A-1B Register. If CLKENA2 is LOW during the rising edge of CLK, data will be clocked into register A-2B
(Active LOW).
CLKEN1B
I
Clock Enable Input for the A-1B Register. If CLKEN1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A
(Active LOW).
CLKEN2B
I
Clock Enable Input for the A-1B Register. If CLKEN2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A
(Active LOW).
SEL
I
1B or 2B Port Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW
during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port (Active LOW).
OEA
I
Synchronous Output Enable for A Port (Active LOW)
OEB
I
Synchronous Output Enable for A Port (Active LOW)
PIN DESCRIPTION
Inputs
Output
CLKEN1B
CLKEN2B
CLK
SEL
1Bx
2Bx
Ax
H
X
X
H
X
X
A
0
(2)
X
H
X
L
X
X
A
0
(2)
L
X
H
L
X
L
L
X
H
H
X
H
X
L
L
X
L
L
X
L
L
X
H
H
B-TO-A STORAGE (OEA = L AND OEA = H)
FUNCTION TABLES
(CONTINUED)
(1)
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input HIGH Current
V
CC
= 3.6V
V
I
= V
CC
--
--
5
A
I
IL
Input LOW Current
V
CC
= 3.6V
V
I
= GND
--
--
5
A
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= V
CC
--
--
10
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
--
0.1
40
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
750
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTE:
1. Typical values are at V
CC
= 3.3V, +25C ambient.
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS (A PORT)
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 6mA
2
--
V
CC
= 2.3V
I
OH
= 12mA
1.7
--
V
CC
= 2.7V
2.2
--
V
CC
= 3V
2.4
--
V
CC
= 3V
I
OH
= 24mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 6mA
--
0.4
I
OL
= 12mA
--
0.7
V
CC
= 2.7V
I
OL
= 12mA
--
0.4
V
CC
= 3V
I
OL
= 24mA
--
0.55
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
5
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS (B PORT)
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 4mA
1.9
--
I
OH
= 6mA
1.7
--
V
CC
= 2.7V
I
OH
= 4mA
2.2
--
I
OH
= 8mA
2
--
V
CC
= 3V
I
OH
= 6mA
2.4
--
I
OH
= 12mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 4mA
--
0.4
I
OL
= 6mA
--
0.55
V
CC
= 2.7V
I
OL
= 4mA
--
0.4
I
OL
= 8mA
--
0.6
V
CC
= 3V
I
OL
= 6mA
--
0.55
I
OL
= 12mA
--
0.8
OPERATING CHARACTERISTICS, T
A
= 25C
V
CC
= 2.5V 0.2V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
C
PD
Power Dissipation Capacitance Outputs enabled
C
L
= 0pF, f = 10Mhz
87
120
pF
C
PD
Power Dissipation Capacitance Outputs disabled
80
118
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
SWITCHING CHARACTERISTICS (A PORT)
(1)
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
120
--
125
--
150
--
MHz
t
PLH
Propagation Delay
1.6
5.8
--
5.4
1.7
4.8
ns
t
PHL
CLK to Ax (1B)
t
PLH
Propagation Delay
1.6
5.8
--
5.3
1.8
4.8
ns
t
PHL
CLK to Ax (2B)
t
PLH
Propagation Delay
2.5
7.3
--
6.5
2.4
5.8
ns
t
PHL
CLK to Ax (SEL)
t
PZH
Output Enable Time
2
6.2
--
5.6
1.8
5.1
ns
t
PZL
CLK to Ax
t
PHZ
Output Disable Time
2
6.5
--
5.4
2.1
5
ns
t
PLZ
CLK to Ax
t
SU
Set-up Time, Ax data before CLK
4.5
--
4
--
3.4
--
ns
t
SU
Set-up Time, SEL before CLK
1.4
--
1.6
--
1.3
--
ns
t
SU
Set-up Time, CLKENA1 or CLKENA2 before CLK
3.6
--
3.4
--
2.8
--
ns
t
SU
Set-up Time, OEA before CLK
4.2
--
3.9
--
3.2
--
ns
t
H
Hold Time, Ax data after CLK
0
--
0
--
0.2
--
ns
t
H
Hold Time, SEL after CLK
1
--
1
--
1
--
ns
t
H
Hold Time, CLKENA1 or CLKENA2 after CLK
0.1
--
0.1
--
0.4
--
ns
t
H
Hold Time, OEA after CLK
0
--
0
--
0.2
--
ns
t
W
Pulse Width, CLK HIGH or LOW
3.3
--
3.3
--
3.3
--
ns
t
SK(O)
Output Skew
(2)
--
--
--
--
--
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS (B PORT)
(1)
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
120
--
125
--
150
--
MHz
t
PLH
Propagation Delay
1.6
6.1
--
5.9
1.8
5.4
ns
t
PHL
CLK to 1Bx, 2Bx
t
PZH
Output Enable Time
2.7
7.2
--
6.8
2.6
6.1
ns
t
PZL
CLK to 1Bx, 2Bx
t
PHZ
Output Disable Time
2.8
7.2
--
6.1
2.5
5.9
ns
t
PLZ
CLK to 1Bx, 2Bx
t
SU
Set-up Time, Bx data before CLK
0.8
--
1.2
--
1
--
ns
t
SU
Set-up Time, CLKEN1B or CLKEN2B before CLK
3.2
--
3
--
2.5
--
ns
t
SU
Set-up Time, OEB before CLK
4.2
--
3.9
--
3.2
--
ns
t
H
Hold Time, Bx data after CLK
1.3
--
1.2
--
1.3
--
ns
t
H
Hold Time, CLKEN1B or CLKEN2B after CLK
0.1
--
0
--
0.5
--
ns
t
H
Hold Time, OEB after CLK
0
--
0
--
0.2
--
ns
t
SK(O)
Output Skew
(2)
--
--
--
--
--
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2. Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
7
Open
V
LOAD
GND
V
CC
P ulse
Generator
D .U .T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPU T
V
IH
0V
V
OH
V
OL
t
PLH1
t
S K
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
P LH1
or
t
PH L2
-
t
PHL1
ALVC Link
S AM E P HAS E
INPU T TRAN SITION
O PP OS ITE P HAS E
INPU T TRAN SITION
0V
0V
V
OH
V
O L
t
PLH
t
PHL
t
PHL
t
PLH
OU TPUT
V
IH
V
T
V
T
V
IH
V
T
ALV C Link
DATA
INP UT
0V
0V
0V
0V
t
R EM
TIM ING
INPU T
SYNC HRON OU S
CON TROL
t
S U
t
H
t
S U
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
A SYNC HRON OU S
CON TROL
LOW -H IGH -LOW
PULS E
HIGH-LOW -HIGH
PULS E
V
T
t
W
V
T
ALVC Link
CON TROL
IN PUT
t
PLZ
0V
OUTPU T
NOR M ALLY
LOW
t
PZ H
0V
SW ITCH
CLO SED
OU TPUT
NORM ALLY
H IGH
ENAB LE
DISAB LE
SW ITCH
O PE N
t
PHZ
0V
V
OL
+ V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
OH -
V
HZ
ALV C L ink
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol V
CC(1)
= 3.3V0.3V V
CC(1)
= 2.7V
V
CC(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
8
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
ORDERING INFORMATION
ID T
XX
ALVC
XXX
XX
Package
D evice Type
Temp. R ange
PV
PA
PF
162
74
Shrink Small Outline P ackage
Thin Shrink Small Outline Package
Thin Very Sm all Outline Package
12-Bit to 24-Bit R egistered Bus Exchanger w ith 3-State Outputs
40C to +85C
X
XX
Fam ily
Bus-H old
268
No Bus-Hold
D ouble-Density, 24m A (A port)
12m A (B port)
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CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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