INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC16836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
1
AUGUST 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4543/2
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: 24mA
Suitable for heavy loads
APPLICATIONS:
SDRAM Modules
PC Motherboards
Workstations
IDT74ALVC16836
3.3V CMOS 20-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
LE
A
1
T O 19 O T H E R C H A N N E LS
O E
C LK
1
5 5
2 9
5 6
1
D
C
1
C L K
2
Y
1
DESCRIPTION:
This 20-bit universal bus driver is built using advanced dual metal CMOS
technology. Data flow from A to Y is controlled by the output-enable (OE) input.
The device operates in the transparent mode when the latch-enable (LE) input
is low. The A data is latched if the clock (CLK) input is held at a high or low logic
level. If LE is high, the A data is stored in the latch flip-flop on the low-to-high
transition of CLK. When OE is high, the outputs are in the high-impedance state.
The ALVC16836 has been designed with a 24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVC16836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
PIN CONFIGURATION
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
7
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
9
pF
C
OUT
I/O Port Capacitance
V
IN
= 0V
7
9
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
V
I
< 0 or V
I
> V
CC
I
OK
Continuous Clamp Current, V
O
< 0
50
mA
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
Pin Names
Description
OE
3-State Output Enable Inputs (Active LOW)
CLK
Register Input Clock
LE
Latch Enable (Active LOW)
A x
Data Inputs
Y x
3-State Outputs
N C
No Internal Connection
PIN DESCRIPTION
SSOP/ TSSOP/ TVSOP
TOP VIEW
FUNCTION TABLE
(1)
Inputs
Outputs
OE
LE
CLK
Ax
Yx
H
X
X
X
Z
L
L
X
L
L
L
L
X
H
H
L
H
L
L
L
H
H
H
L
H
H
X
Y
0
(2)
L
H
L
X
Y
0
(2)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
= LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
OE
GND
V
CC
GND
GND
V
CC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
CLK
GND
NC
25
26
27
28
32
31
30
29
LE
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
Y
13
Y
14
Y
15
Y
16
Y
17
Y
18
Y
19
Y
20
GND
V
CC
GND
GND
V
CC
GND
A
5
A
8
A
9
A
19
A
20
A
17
A
18
A
14
A
15
A
16
A
10
A
11
A
12
A
13
A
1
A
2
A
3
A
4
A
6
A
7
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC16836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
3
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input HIGH Current
V
CC
= 3.6V
V
I
= V
CC
--
--
5
A
I
IL
Input LOW Current
V
CC
= 3.6V
V
I
= GND
--
--
5
A
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= V
CC
--
--
10
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
--
0.1
40
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
750
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTE:
1. Typical values are at V
CC
= 3.3V, +25C ambient.
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 6mA
2
--
V
CC
= 2.3V
I
OH
= 12mA
1.7
--
V
CC
= 2.7V
2.2
--
V
CC
= 3V
2.4
--
V
CC
= 3V
I
OH
= 24mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 6mA
--
0.4
I
OL
= 12mA
--
0.7
V
CC
= 2.7V
I
OL
= 12mA
--
0.4
V
CC
= 3V
I
OL
= 24mA
--
0.55
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVC16836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
OPERATING CHARACTERISTICS, T
A
= 25C
V
CC
= 2.5V 0.2V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
C
PD
Power Dissipation Capacitance Outputs enabled
C
L
= 0pF, f = 10Mhz
--
--
pF
C
PD
Power Dissipation Capacitance Outputs disabled
--
--
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
150
--
150
--
150
--
MHz
t
PLH
Propagation Delay
1
4.2
--
4.2
1
3.6
ns
t
PHL
Ax to Yx
t
PLH
Propagation Delay
1.3
5
--
4.9
1.3
4.2
ns
t
PHL
LE to Yx
t
PLH
Propagation Delay
1.4
5.5
--
5.2
1.4
4.5
ns
t
PHL
CLK to Yx
t
PZH
Output Enable Time
1.4
5.5
--
5.6
1.1
4.6
ns
t
PZL
OE to Yx
t
PHZ
Output Disable Time
1
4.5
--
4.3
1.3
3.9
ns
t
PLZ
OE to Yx
t
W
Pulse Duration, LE LOW
3.3
--
3.3
--
3.3
--
ns
t
W
Pulse Duration, CLK HIGH or LOW
3.3
--
3.3
--
3.3
--
ns
t
SU
Set-up Time, data before CLK
1.4
--
1.7
--
1.5
--
ns
t
SU
Set-up Time, data before LE
, CLK HIGH
1.2
--
1.6
--
1.3
--
ns
t
SU
Set-up Time, data before LE
, CLK LOW
1.4
--
1.5
--
1.2
--
ns
t
H
Hold Time, data after CLK
0.9
--
0.9
--
0.9
--
ns
t
H
Hold Time, data after LE
, CLK HIGH or LOW
1.1
--
1.1
--
1.1
--
ns
t
SK(O)
Output Skew
(2)
--
--
--
--
--
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS FROM 0C TO 65C, C
L
= 50pF
V
CC
= 3.3V 0.15V
Symbol
Parameter
Min.
Max.
Unit
t
PLH
Propagation Delay
--
--
ns
t
PHL
CLK to xYx
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC16836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
5
Open
V
LOAD
GND
V
CC
P ulse
Generator
D .U .T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPU T
V
IH
0V
V
OH
V
OL
t
PLH1
t
S K
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
P LH1
or
t
PH L2
-
t
PHL1
ALVC Link
S AM E P HAS E
INPU T TRAN SITION
O PP OS ITE P HAS E
INPU T TRAN SITION
0V
0V
V
OH
V
O L
t
PLH
t
PHL
t
PHL
t
PLH
OU TPUT
V
IH
V
T
V
T
V
IH
V
T
ALV C Link
DATA
INP UT
0V
0V
0V
0V
t
R EM
TIM ING
INPU T
SYNC HRON OU S
CON TROL
t
S U
t
H
t
S U
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
A SYNC HRON OU S
CON TROL
LOW -H IGH -LOW
PULS E
HIGH-LOW -HIGH
PULS E
V
T
t
W
V
T
ALVC Link
CON TROL
IN PUT
t
PLZ
0V
OUTPU T
NOR M ALLY
LOW
t
PZ H
0V
SW ITCH
CLO SED
OU TPUT
NORM ALLY
H IGH
ENAB LE
DISAB LE
SW ITCH
O PE N
t
PHZ
0V
V
OL
+ V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
OH -
V
HZ
ALV C L ink
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol V
CC(1)
= 3.3V0.3V V
CC(1)
= 2.7V
V
CC(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVC16836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
ORDERING INFORMATION
IDT
XX
ALVC
XXX
XX
Package
Device Type
Temp. Range
PV
PA
PF
16
74
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
20-Bit Universal Bus Driver with 3-State Outputs
40C to +85C
X
XX
Family
Bus-Hold
836
No Bus-Hold
Double-Density, 24mA
Blank
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
PDF 
ZIP