INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16270
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
1
AUGUST 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4475/1
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: 24mA
Suitable for heavy loads
CLKEN2B
C LK
CLKENA1
OEA
1
B
1
SEL
CLKENA2
C1
1D
C1
1D
C E
1D
C1
A1
2
B
1
1 of 12 Channels
CLKEN1B
1
28
56
55
30
27
2
29
OEB
CE
1D
C 1
CE
1D
C 1
CE
1D
C 1
CE
1D
C 1
23
6
8
0
1
IDT74ALVCH16270
3.3V CMOS 12-BIT TO
24-BIT REGISTERED BUS
EXCHANGER WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This registered bus exchanger is built using advanced dual metal CMOS
technology. The ALVCH16270 is used in applications in which data must be
transferred from a narrow high-speed bus to a wide lower-frequency bus.
This device provides synchronous data exchange between the two ports.
Data is stored in the internal registers on the low-to-high transition of the clock
(CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The
select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the
A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single
storage register in the A-to-2B path. Proper control of the CLKENA input allows
two sequential 12-bit words to be presented synchronously as a 24-bit word on
the B-port. Data flow is controlled by the active-low output enables (OEA and
OEB). The control terminals are registered to synchronize the bus-direction
changes with CLK.
The ALVCH16270 has been designed with a
24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16270 has "bus-hold" which retains the inputs' last state when-
ever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistors.
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCH16270
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN CONFIGURATION
OEA
2
B
3
GND
2
B
2
2
B
1
V
CC
A
1
A
2
GND
A
3
A
4
A
5
A
6
A
8
A
9
GND
A
10
A
11
A
12
V
CC
1
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
OEB
2
B
4
GND
2
B
5
2
B
6
V
CC
2
B
7
2
B
8
2
B
9
2
B
10
2
B
11
2
B
12
GND
1
B
11
1
B
10
1
B
9
1
B
8
GND
1
B
7
1
B
6
1
B
5
GND
1
B
3
SEL
25
26
27
28
32
31
30
29
GND
1
B
4
CLKENA1
CLK
A
7
1
B
2
V
CC
1
B
12
CLKENA2
CLKEN2B
CLKEN1B
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
V
I
< 0 or V
I
> V
CC
I
OK
Continuous Clamp Current, V
O
< 0
50
mA
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
= LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
3. Two CLK edges are needed to propagate data.
4. Data present at the output of the first register.
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
7
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
9
pF
C
I/O
I/O Port Capacitance
V
IN
= 0V
7
9
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
FUNCTION TABLES
(1)
Inputs
Outputs
CLKENB1 CLKENB2
CLK
SEL
1
Bx
2
Bx
Ax
H
X
X
H
X
X
A
0
(2)
X
H
X
L
X
X
A
0
(2)
L
X
H
L
X
L
L
X
H
H
X
H
X
L
L
X
L
L
X
L
L
X
H
H
B-TO-A STORAGE (OEA = L AND OEB = H)
Inputs
Outputs
CLKENA1
CLKENA2
CLK
Ax
1
Bx
2
Bx
L
H
L
1
B
0
(2)
2
B
0
(2)
L
H
H
1
B
0
(2)
2
B
0
(2)
L
L
L
L
(3)
L
L
L
H
H
(3)
H
H
L
L
1
B
0
(4)
L
H
L
H
1
B
0
(4)
H
H
H
X or
X
1
B
0
(2)
2
B
0
(2)
A-TO-B STORAGE (OEB = L AND OEA = H)
Inputs
Outputs
CLK
OEA
OEB
Ax
1
Bx,
2
Bx
H
H
Z
Z
H
L
Z
Active
L
H
Active
Z
L
L
Active
Active
OUTPUT ENABLE
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16270
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
3
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
PIN DESCRIPTION
Pin Names I/O
Description
Ax
(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
(1)
1Bx
(1:12)
I/O
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
(1)
2Bx
(1:12)
I/O
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
(1)
CLK
I
Clock Input
CLKENA1
I
Clock Enable Input for the A-1B Register. If CLKENA1 is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW).
CLKENA2
I
Clock Enable Input for the A-2B Register. If CLKENA2 is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW).
CLKEN1B
I
Clock Enable Input for the 1B-A Register. If CLKEN1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW).
CLKEN2B
I
Clock Enable Input for the 2B-A Register. If CLKEN2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW).
SEL
I
1B or 2B Port Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising
edge of CLK, SEL enables data transfer from 2B Port to A Port.
OEA
I
Synchronous Output Enable for A Port (Active LOW)
OEB
I
Synchronous Output Enable for B Port (Active LOW)
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input HIGH Current
V
CC
= 3.6V
V
I
= V
CC
--
--
5
A
I
IL
Input LOW Current
V
CC
= 3.6V
V
I
= GND
--
--
5
A
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= V
CC
--
--
10
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
--
0.1
40
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
750
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTE:
1. Typical values are at V
CC
= 3.3V, +25C ambient.
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH16270
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
OPERATING CHARACTERISTICS, T
A
= 25C
V
CC
= 2.5V 0.2V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
C
PD
Power Dissipation Capacitance Outputs enabled
C
L
= 0pF, f = 10Mhz
87
120
pF
C
PD
Power Dissipation Capacitance Outputs disabled
80.5
118
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 6mA
2
--
V
CC
= 2.3V
I
OH
= 12mA
1.7
--
V
CC
= 2.7V
2.2
--
V
CC
= 3V
2.4
--
V
CC
= 3V
I
OH
= 24mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 6mA
--
0.4
I
OL
= 12mA
--
0.7
V
CC
= 2.7V
I
OL
= 12mA
--
0.4
V
CC
= 3V
I
OL
= 24mA
--
0.55
BUS-HOLD CHARACTERISTICS
Symbol
Parameter
(1)
Test Conditions
Min.
Typ.
(2)
Max.
Unit
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 3V
V
I
= 2V
75
--
--
A
I
BHL
V
I
= 0.8V
75
--
--
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 2.3V
V
I
= 1.7V
45
--
--
A
I
BHL
V
I
= 0.7V
45
--
--
I
BHHO
Bus-Hold Input Overdrive Current
V
CC
= 3.6V
V
I
= 0 to 3.6V
--
--
500
A
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25C ambient.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16270
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
5
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
150
--
150
--
150
--
MHz
t
PLH
Propagation Delay
1.5
5.9
--
5.8
1.1
5.1
ns
t
PHL
CLK to xBx
t
PLH
Propagation Delay
1.2
5.4
--
5.4
1
4.7
ns
t
PHL
CLK to Ax
t
PLH
Propagation Delay
1.4
6.2
--
6.4
1
5.5
ns
t
PHL
SEL to Ax
t
PZH
Output Enable Time
1.5
7
--
6.8
1
6
ns
t
PZL
CLK to xBx
t
PZH
Output Enable Time
1.5
7
--
6.8
1
6
ns
t
PZL
CLK to Ax
t
PHZ
Output Disable Time
1.9
7.2
--
6.5
1.1
5.8
ns
t
PLZ
CLK to xBx
t
PHZ
Output Disable Time
1.9
7.2
--
6.5
1.1
5.8
ns
t
PLZ
CLK to Ax
t
SU
Set-up Time, Ax data before CLK
4.1
--
3.8
--
3.1
--
ns
t
SU
Set-up Time, Bx data before CLK
0.9
--
1.2
--
0.9
--
ns
t
SU
Set-up Time, CLKENA1 or CLKENA2 before CLK
3.5
--
3.2
--
2.7
--
ns
t
SU
Set-up Time, CLKEN1B or CLKEN2B before CLK
3.4
--
3
--
2.6
--
ns
t
SU
Set-up Time, OEB or OEA before CLK
4.4
--
3.9
--
3.2
--
ns
t
H
Hold Time, Ax data after CLK
0
--
0
--
0.2
--
ns
t
H
Hold Time, Bx data after CLK
1.4
--
1
--
1.7
--
ns
t
H
Hold Time, CLKENA1 or CLKENA2 after CLK
0
--
0.1
--
0.3
--
ns
t
H
Hold Time, CLKEN1B or CLKEN2B after CLK
0
--
0
--
0.6
--
ns
t
H
Hold Time, OEB or OEA after CLK
0
--
0
--
0.1
--
ns
t
W
Pulse Width, CLK HIGH or LOW
3.3
--
3.3
--
3.3
--
ns
t
SK(O)
Output Skew
(2)
--
--
--
--
--
500
ps
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH16270
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALV C Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
ALVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW -HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SW ITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SW ITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol V
CC(1)
= 3.3V0.3V V
CC(1)
= 2.7V
V
CC(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16270
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
7
ORDERING INFORMATION
IDT
XX
ALVC
XXX
XX
Package
Device Type
Temp. Range
PV
PA
PF
16
74
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
12-Bit to 24-Bit Registered Bus Exchanger with
3-State Outputs
40C to +85C
X
XX
Family
Bus-Hold
270
Bus-hold
Double-Density, 24mA
H
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
PDF 
ZIP