INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16276
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4213/2
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: 24mA
Suitable for heavy loads
CE1B
C LK
C EA1B
SEL
OEB
CEA2B
A
1:12
C E2B
A-1B
R EGISTER
1B-A
R EGISTER
M
U
X
1
0
12
12
12
12
12
12
1
B
1:12
2
B
1:12
12
OEA
C E
D
C E
Q
Q
D
CO NTR OL
R EGISTER
2B-A
R EGISTER
C E
Q
D
A-2B
R EGISTER
C E
D
Q
12
12
1
29
56
28
30
27
55
2
IDT74ALVCH16276
3.3V CMOS 12-BIT
SYNCHRONOUS BUS
EXCHANGER WITH
BUS-HOLD
DESCRIPTION:
This 12-bit synchronous bus exchanger is built using dual metal CMOS
technology. The ALVCH16276 device is a high-speed, bidirectional, 12-bit,
registered, bus multiplexer for use in synchronous memory interleaving
applications. All registers have a common clock and use a clock enable (CExxx)
on each data register to control data sequencing. The output enables and mux
select (OEA, OEB and SEL) are also under synchronous control allowing
direction changes to be edge triggered events.
The ALVCH16276 has three 12-bit ports. Data may be transferred between
the A port and either/both of the B ports. The clock enable (CE1B, CE2B, CEA1B
and CEA2B) inputs control data storage. Both B ports have a common output
enable (OEB) to aid in synchronously loading the B registers from the B port.
The ALVCH16276 has been designed with a 24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16276 has "bus-hold" which retains the inputs' last state when-
ever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistors.
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCH16276
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN CONFIGURATION
CEA1B
2
B
3
GND
2
B
2
2
B
1
V
CC
A
1
A
2
GND
A
3
A
4
A
5
A
6
A
8
A
9
GND
A
10
A
11
A
12
V
CC
1
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
CE1B
2
B
4
GND
2
B
5
2
B
6
V
CC
2
B
7
2
B
8
2
B
9
2
B
10
2
B
11
2
B
12
GND
1
B
11
1
B
10
1
B
9
1
B
8
GND
1
B
7
1
B
6
1
B
5
GND
1
B
3
OEA
SEL
25
26
27
28
32
31
30
29
GND
1
B
4
OEB
CLK
A
7
1
B
2
V
CC
1
B
12
CEA2B
CE2B
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
V
I
< 0 or V
I
> V
CC
I
OK
Continuous Clamp Current, V
O
< 0
50
mA
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
7
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
9
pF
C
I/O
I/O Port Capacitance
V
IN
= 0V
7
9
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16276
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD
3
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
2. Output level before the indicated steady-state input conditions were established.
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
PIN DESCRIPTION
Pin Names I/O
Description
Ax
(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
(1)
1Bx
(1:12)
I/O
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
(1)
2Bx
(1:12)
I/O
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
(1)
CLK
I
Clock Input
CEA1B
I
Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW).
CEA2B
I
Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW).
CE1B
I
Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW).
CE2B
I
Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW).
SEL
I
1B or 2B Port Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising
edge of CLK, SEL enables data transfer from 2B Port to A Port.
OEA
I
Synchronous Output Enable for A Port (Active LOW)
OEB
I
Synchronous Output Enable for 1B Port and 2B Port (Active LOW)
Inputs
Outputs
Ax
CEA1B
CEA2B
OEB
CLK
1
Bx
2
Bx
H
L
L
L
--
H
H
L
L
L
L
--
L
L
H
L
H
L
--
H
B
0
(2)
L
L
H
L
--
L
B
0
(2)
H
H
L
L
--
B
0
(2)
H
L
H
L
L
--
B
0
(2)
L
X
H
H
L
--
B
0
(2)
B
0
(2)
X
X
X
H
--
Z
Z
X
X
X
L
--
Active
Active
Inputs
Output
1
Bx
2
Bx
SEL
CE1B
CE2B
OEA
CLK
Ax
H
X
H
L
X
L
--
H
L
X
H
L
X
L
--
L
X
X
H
H
X
L
--
A
0
(2)
X
H
L
X
L
L
--
H
X
L
L
X
L
L
--
L
X
X
L
X
H
L
--
A
0
(2)
X
X
X
X
X
H
--
Z
FUNCTION TABLES
(1)
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH16276
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD
BUS-HOLD CHARACTERISTICS
Symbol
Parameter
(1)
Test Conditions
Min.
Typ.
(2)
Max.
Unit
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 3V
V
I
= 2V
75
--
--
A
I
BHL
V
I
= 0.8V
75
--
--
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 2.3V
V
I
= 1.7V
45
--
--
A
I
BHL
V
I
= 0.7V
45
--
--
I
BHHO
Bus-Hold Input Overdrive Current
V
CC
= 3.6V
V
I
= 0 to 3.6V
--
--
500
A
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25C ambient.
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input HIGH Current
V
CC
= 3.6V
V
I
= V
CC
--
--
5
A
I
IL
Input LOW Current
V
CC
= 3.6V
V
I
= GND
--
--
5
A
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= V
CC
--
--
10
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
--
0.1
40
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
750
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTE:
1. Typical values are at V
CC
= 3.3V, +25C ambient.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16276
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD
5
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 6mA
2
--
V
CC
= 2.3V
I
OH
= 12mA
1.7
--
V
CC
= 2.7V
2.2
--
V
CC
= 3V
2.4
--
V
CC
= 3V
I
OH
= 24mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 6mA
--
0.4
I
OL
= 12mA
--
0.7
V
CC
= 2.7V
I
OL
= 12mA
--
0.4
V
CC
= 3V
I
OL
= 24mA
--
0.55
OPERATING CHARACTERISTICS, T
A
= 25C
V
CC
= 2.5V 0.2V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
C
PD
Power Dissipation Capacitance Outputs enabled
C
L
= 0pF, f = 10Mhz
55
59
pF
C
PD
Power Dissipation Capacitance Outputs disabled
46
49
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH16276
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
PLH
Propagation Delay
1.5
5
1.5
4.7
1.5
4.3
ns
t
PHL
CLK to 1Bx or CLK to 2Bx
t
PLH
Propagation Delay
1.5
5.3
1.5
5
1.5
4.6
ns
t
PHL
CLK to Ax, SEL stable and CExB enabled
t
PLH
Propagation Delay
1.5
5.7
1.5
5.3
1.5
5.1
ns
t
PHL
SEL changing and CExB disabled
t
PLH
Propagation Delay
1.5
5.8
1.5
5.4
1.5
5.1
ns
t
PHL
SEL changing and CExB enabled
t
PZH
Output Enable Time
1.5
5.6
1.5
5.2
1.5
5
ns
t
PZL
CLK to Ax, CLK to 1Bx, or CLK to 2Bx
t
PHZ
Output Disable Time
1.3
4.7
1.5
5.2
1.5
5
ns
t
PLZ
CLK to Ax, CLK to 1Bx, or CLK to 2Bx
t
SU
Set-up Time, data to CLK, HIGH or LOW
1
--
1
--
1
--
ns
t
SU
Set-up Time, OEA to CLK, OEB to CLK
1
--
1
--
1
--
ns
t
SU
Set-up Time, SEL to CLK
1
--
1
--
1
--
ns
t
SU
Set-up Time, CEA1B to CLK, CE1B to CLK
1
--
1
--
1
--
ns
CE2B to CLK, or CEA2B to CLK
t
H
Hold Time, CLK to data
1
--
1
--
1
--
ns
t
H
Hold Time, CLK to OEA, CLK to OEB, CLK to SEL
1
--
1
--
1
--
ns
t
H
Hold Time, CLK to CEA1B, CLK to CE1B,
1
--
1
--
1
--
ns
CLK to CE2B, or CLK to CEA2B
t
W
Pulse Width, CLK HIGH
2.5
--
2.5
--
2.5
--
ns
t
SK(O)
Output Skew
(2)
--
--
--
--
--
500
ps
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16276
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD
7
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALV C Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
ALVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW -HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SW ITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SW ITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol V
CC(1)
= 3.3V0.3V V
CC(1)
= 2.7V
V
CC(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
8
IDT74ALVCH16276
3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD
ORDERING INFORMATION
IDT
XX
ALVC
XXX
XX
Package
Device Type
Temp. Range
PV
PA
PF
16
74
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
12-Bit Synchronous Bus Exchanger
40C to +85C
X
XXX
Family
Bus-Hold
276
Bus-Hold
H
Double-Density, 24mA
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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