INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH374
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4473/1
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in QSOP, SOIC, SSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: 24mA
Suitable for Heavy Loads
IDT74ALVCH374
3.3V CMOS OCTAL POSITIVE
EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DESCRIPTION:
This octal postive edge-triggered D-type flip-flop is built using advanced
dual metal CMOS technology. The ALVCH374 device is particularly
suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. On the positive transition of the clock (CLK) input, the
Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components. OE
does not affect internal operations of the latch. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
The ALVCH374 has been designed with a 24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH374 has a "bus-hold" which retains the inputs' last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
1
Q
11
2
OE
TO SEVEN OTHER CHANNELS
1
CLK
1
D
C1
1
D
3
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCH374
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
V
I
< 0 or V
I
> V
CC
I
OK
Continuous Clamp Current, V
O
< 0
50
mA
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
7
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
9
pF
C
I/O
I/O Port Capacitance
V
IN
= 0V
7
9
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
QSOP/ SOIC/ SSOP/ TSSOP
TOPVIEW
PIN CONFIGURATION
Pin Names
Description
OE
3-State Output Enable Input (Active LOW)
CLK
Clock Input
xD
Data Inputs
(1)
xQ
3-State Outputs
PIN DESCRIPTION
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE
(1)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
= LOW-to-HIGH Transition
2. Output level of Q before the indicated steady-state conditions were established.
Inputs
Output
OE
CLK
xD
xQ
L
H
H
L
L
L
L
H or L
X
Q
(2)
H
X
X
Z
V
CC
OE
8
D
7
D
7
Q
6
Q
6
D
5
D
5
Q
1
Q
1
D
2
D
2
Q
3
Q
3
D
4
D
4
Q
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
CLK
8
Q
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH374
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
3
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input HIGH Current
V
CC
= 3.6V
V
I
= V
CC
--
--
5
A
I
IL
Input LOW Current
V
CC
= 3.6V
V
I
= GND
--
--
5
A
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= V
CC
--
--
10
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
--
0.1
40
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
750
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTE:
1. Typical values are at V
CC
= 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter
(1)
Test Conditions
Min.
Typ.
(2)
Max.
Unit
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 3V
V
I
= 2V
75
--
--
A
I
BHL
V
I
= 0.8V
75
--
--
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 2.3V
V
I
= 1.7V
45
--
--
A
I
BHL
V
I
= 0.7V
45
--
--
I
BHHO
Bus-Hold Input Overdrive Current
V
CC
= 3.6V
V
I
= 0 to 3.6V
--
--
500
A
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25C ambient.
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH374
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
OPERATING CHARACTERISTICS, T
A
= 25C
V
CC
= 2.5V 0.2V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
C
PD
Power Dissipation Capacitance Outputs enabled
C
L
= 0pF, f = 10Mhz
pF
C
PD
Power Dissipation Capacitance Outputs disabled
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2
Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
PLH
Propagation Delay
--
8
--
7
2.2
6
ns
t
PHL
CLK to xQ
t
PZH
Output Enable Time
--
8.5
--
7.5
1.5
6.5
ns
t
PZL
OE to xQ
t
PHZ
Output Disable Time
--
9.5
--
6.5
1.5
5.5
ns
t
PLZ
OE to xQ
t
W
Pulse Duration, CLK HIGH or LOW
3.3
--
3.3
--
3.3
--
ns
t
SU
Setup Time, data before CLK
2
--
2
--
2
--
ns
t
H
Hold Time, data after CLK
1.5
--
1.5
--
1.5
--
ns
t
SK(O)
Output Skew
(2)
--
--
--
--
--
500
ps
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 6mA
2
--
V
CC
= 2.3V
I
OH
= 12mA
1.7
--
V
CC
= 2.7V
2.2
--
V
CC
= 3V
2.4
--
V
CC
= 3V
I
OH
= 24mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 6mA
--
0.4
I
OL
= 12mA
--
0.7
V
CC
= 2.7V
I
OL
= 12mA
--
0.4
V
CC
= 3V
I
OL
= 24mA
--
0.55
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH374
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
5
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
T
V
IH
V
T
V
T
V
IH
V
T
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
ALVC Link
ALVC Link
ALVC Link
ALVC Link
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
10MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
10MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
Symbol V
CC(1)
= 3.3V0.3V V
CC(1)
= 2.7V
V
CC(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH374
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
IDT
XX
ALVC
XXX
XX
Package
Device Type
Temp. Range
SO
PY
Q
PG
74
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
Thin Shrink Small Outline Package
Octal Positive Edge-Triggered D-Type Flip-Flop
with 3-State Outputs, 24mA
40C to +85C
X
Bus-Hold
374
Bus-Hold
H
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