MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT646T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
1
JUNE 2002
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5505/3
FEATURES:
Std., A, and C grades
Low input and output leakage
1A (max.)
CMOS power levels
True TTL input and output compatibility:
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 64mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
Industrial: SOIC, SSOP, QSOP, TSSOP
Military: CERDIP, LCC
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT646T/AT/CT
FAST CMOS OCTAL
TRANSCEIVER/
REGISTER (3-STATE)
DESCRIPTION:
The FCT646T consists of a bus transceiver with 3-state D-type flip-flops
and control circuitry arranged for multiplexed transmission of data directly
from the data bus or from the internal storage registers. The FCT646T
utilizes the enable control (G) and direction (DIR) pins to control the
transceiver functions.
SAB and SBA control pins are provided to select either real- time or stored
data transfer. The circuitry used for select control will eliminate the typical
decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. A low input level selects real-time data and a high
selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock pins (CPAB or
CPBA), regardless of the select or enable control pins.
A1
G
DIR
CPB A
SBA
CPA B
SAB
O NE OF EIG HT CHANNELS
B REG
A REG
B1
1D
C1
C1
1D
TO SEVE N O THER CHANN ELS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
2
IDT54/74FCT646T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
CERDIP/ SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
2
3
1
20
19
18
15
16
9
10
A
6
A
7
A
1
A
2
A
5
A
3
A
4
A
8
B
6
B
7
23
22
24
21
17
5
6
7
4
8
SAB
V
CC
CPBA
B
2
B
8
B
1
B
3
B
4
B
5
CPAB
13
14
11
12
DIR
GND
SBA
G
1
2
3
4
5
7
8
6
9
10
11
12
13
14
15
16
17
18
19
20
INDEX
A
1
21
22
23
24
25
26
27
28
A
2
A
3
A
4
A
5
A
6
A
7
A
8
NC
G
N
D
N
C
NC
N
C
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
G
D
I
R
S
A
B
C
P
A
B
V
c
c
C
P
B
A
S
B
A
LCC
TOP VIEW
PIN DESCRIPTION
Pin Names
Description
A
1
- A
8
Data Register A Inputs
Data Register B Outputs
B
1
- B
8
Data Register B Inputs
Data Register A Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Output Data Source Select Inputs
DIR, G
Output Enable Inputs
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT646T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
3
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
IL
Input LOW Current
(4)
V
CC
= Max.
V
I
= 0.5V
--
--
1
A
I
OZH
High Impedance Output Current
V
CC
= Max
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State output pins)
(4)
V
O
= 0.5V
--
--
1
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min, I
IN
= -18mA
--
0.7
1.2
V
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
0.01
1
A
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 5.0V 5%; Military: T
A
= 55C to +125C, V
CC
= 5.0V 10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is 5A at T
A
= 55C.
5. This parameter is guaranteed but not tested.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min
I
OH
= 6mA MIL
2.4
3.3
--
V
IN
= V
IH
or V
IL
I
OH
= 8mA IND
V
I
OH
= 12mA MIL
2
3
--
I
OH
= 15mA IND
V
OL
Output LOW Voltage
V
CC
= Min
I
OL
= 48mA MIL
--
0.3
0.55
V
V
IN
= V
IH
or V
IL
I
OL
= 64mA IND
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
60
120
225
mA
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
OUTPUT DRIVE CHARACTERISTICS
NOTES:
1. H = HIGH
L = LOW
X = Don't Care
= LOW-to-HIGH transition.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
2. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e. data at the bus pins will be
stored on every LOW-to-HIGH transition on the clock inputs.
3. A in B Register.
4. B in A Register.
FUNCTION TABLE
(1)
Inputs
Data I/O
(2)
G
DIR
CPAB
CPBA
SAB
SBA
A
1
- A
8
B
1
- B
8
Operation or Function
H
X
H or L
H or L
X
X
Input
Input
Isolation
H
X
X
X
Store A and B Data
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H or L
X
H
Stored B Data to A Bus
L
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
L
H
H or L
X
H
X
Stored A Data to B Bus
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
4
IDT54/74FCT646T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
D IR
G
C PAB
C PBA
SAB
SBA
L
L
X
X
X
L
BU S
B
BU S
A
BU S
A
BU S
B
D IR
G
C PAB
C PBA
SAB
SBA
H
L
X
X
L
X
BU S
A
BU S
B
D IR
G
C PAB
C PBA
SAB
SBA
H
L
X
X
X
L
L
X
X
X
X
H
X
X
BU S
A
BU S
B
D IR
G
C PAB
C PBA
SAB
SBA
L
L
X
X
H
H
L
H or L
X
H
X
H or L
Real-Time Transfer
Bus B to A
Real-Time Transfer
Bus A to B
Transfer Stores
(1)
Data to A and/or B
Storage From
A and/or B
NOTE:
1. Cannot transfer data to A bus and B bus simultaneously.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT646T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
5
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
2
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
= V
CC
--
0.15
0.25
mA/
Current
(4)
Outputs Open
V
IN
= GND
MHz
G = DIR = GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
--
1.5
3.5
mA
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
G = DIR = GND
V
IN
= 3.4V
--
2
5.5
One Bit Toggling
V
IN
= GND
at fi = 5MHz
V
CC
= Max.
V
IN
= V
CC
--
3.8
7.3
(5)
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
G = DIR = GND
V
IN
= 3.4V
--
6
16.3
(5)
Eight Bits Toggling
V
IN
= GND
at fi = 2.5MHz
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
6
IDT54/74FCT646T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
54FCT646T
54/74FCT646AT
54/74FCT646CT
Mil.
Ind.
Mil.
Ind.
Mil.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max. Min.
(2)
Max. Unit
t
PLH
Propagation Delay,
C
L
= 50pF
2
11
2
6.3
2
7.7
1.5
5.4
1.5
6
ns
t
PHL
Bus to Bus
R
L
= 500
t
PZH
Output Enable Time,
2
15
2
9.8
2
10.5
1.5
7.8
1.5
8.9
ns
t
PZL
G, DIR to Bus
t
PHZ
Output Disable Time,
2
11
2
6.3
2
7.7
1.5
6.3
1.5
7.7
ns
t
PLZ
G, DIR to Bus
t
PLH
Propagation Delay,
2
10
2
6.3
2
7
1.5
5.7
1.5
6.3
ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay,
2
12
2
7.7
2
8.4
1.5
6.2
1.5
7
ns
t
PHL
SBA or SAB to Bus
t
SU
Set-up Time HIGH or LOW,
4.5
--
2
--
2
--
2
--
2
--
ns
Bus to Clock
t
H
Hold Time HIGH or LOW,
2
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Bus to Clock
t
W
Clock Pulse Width,
6
--
5
--
5
--
5
--
5
--
ns
HIGH or LOW
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT646T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
7
Pulse
Generator
R
T
D.U.T
.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
8
IDT54/74FCT646T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
ORDERING INFORMATION
IDT XX
Temp. Range
FCT
XXXX
Device Type
XX
Package
X
Process
Fast CMOS Octal Transceiver/Register (3-State)
646T
646AT
646CT
SO
PY
Q
PG
Industrial Options
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
Thin Shrink Small Outline Package
D
L
Military Options
CERDIP
Leadless Chip Carrier
Blank
B
Industrial
MIL-STD-883, Class B
54
74
55C to +125C
40C to +85C
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
PDF 
ZIP