INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH2573A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
1
FEBRUARY 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
DSC-4942/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-rail output swing for increased noise margin
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SOIC, SSOP, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIVE FEATURES:
Balanced Output Drivers: 12mA
Low switching noise
IDT74LVCH2573A
DESCRIPTION:
The LVCH2573A octal transparent D-type latch is built using advanced
dual metal CMOS technology. The device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads,
and is particularly suitable for implementing buffer registers, input-output (I/
O) ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D)
inputs. When LE is taken low, the Q outputs are latched at the logic levels
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components. OE
does not affect the internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high-impedance state.
The LVCH2573A has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver has
been developed to drive
12mA at the designated thresholds.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
The LVCH2573A has "bus-hold" which retains the inputs' last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS OCTAL
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS, 5 VOLT
TOLERANT I/O AND BUS-HOLD
OE
C
1
LE
1
D
TO SEVEN OTHER CHANNELS
1
11
2
19
1
D
1
Q
INDUSTRIAL TEMPERATURE RANGE
2
IDT74LVCH2573A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
4.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8
pF
C
I/O
I/O Port Capacitance
V
IN
= 0V
6.5
8
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
Symbol
Description
Max
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +6.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
I
OK
V
I
< 0 or V
O
< 0
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN CONFIGURATION
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
3
1
1
D
V
CC
16
15
14
5
Q
4
Q
6
Q
2
Q
1
Q
3
Q
11
8
Q
7
Q
LE
19
18
20
17
13
12
OE
5
6
6
D
7
4
D
5
D
4
2
D
3
D
8
9
GND
10
7
D
8
D
NOTES:
1. H = HIGH Voltage Level
X = Don't Care
L = LOW Voltage Level
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
Inputs
Outputs
xD
LE
OE
xQ
H
H
L
H
L
H
L
L
X
L
L
Q
(2)
X
X
H
Z
FUNCTION TABLE
(EACH LATCH)
(1)
Pin Names
Description
OE
Output Enable Inputs (Active LOW)
LE
Latch Enable Input
xD
Data Inputs
(1)
xQ
3-State Data Outputs
PIN DESCRIPTION
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH2573A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
3
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input Leakage Current
V
CC
= 3.6V
V
I
= 0 to 5.5V
--
--
5
A
I
IL
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= 0 to 5.5V
--
--
10
A
I
OZL
(3-State Output pins)
I
OFF
Input/Output Power Off Leakage
V
CC
= 0V, V
IN
or V
O
5.5V
--
--
50
A
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
V
IN
= GND or V
CC
--
--
10
A
I
CCH
I
CCZ
3.6
V
IN
5.5V
(2)
--
--
10
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
500
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTES:
1. Typical values are at V
CC
= 3.3V, +25C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter
(1)
Test Conditions
Min.
Typ.
(2)
Max.
Unit
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 3V
V
I
= 2V
75
--
--
A
I
BHL
V
I
= 0.8V
75
--
--
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 2.3V
V
I
= 1.7V
--
--
--
A
I
BHL
V
I
= 0.7V
--
--
--
I
BHHO
Bus-Hold Input Overdrive Current
V
CC
= 3.6V
V
I
= 0 to 3.6V
--
--
500
A
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25C ambient.
INDUSTRIAL TEMPERATURE RANGE
4
IDT74LVCH2573A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
PLH
Propagation Delay
1.5
9
1.5
8
ns
t
PHL
xD to xQ
t
PLH
Propagation Delay
1.5
9.5
1.5
8.5
ns
t
PHL
LE to xQ
t
PZH
Output Enable Time
1.5
9.5
1.5
8.5
ns
t
PZL
OEx to xQ
t
PHZ
Output Disable Time
1.5
7
1.5
6.5
ns
t
PLZ
OEx to xQ
t
W
Pulse Duration, LE HIGH
3.3
--
3.3
--
ns
t
SU
Setup Time, data before LE
2.5
--
2.5
--
ns
t
H
Hold Time, data after LE
1.5
--
1.5
--
ns
t
SK
(o)
Output Skew
(2)
--
--
--
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2. Skew between any two outputs of the same package and switching in the same direction.
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 4mA
1.9
--
I
OH
= 6mA
1.7
--
V
CC
= 2.7V
I
OH
= 4mA
2.2
--
I
OH
= 8mA
2
--
V
CC
= 3V
I
OH
= 6mA
2.4
--
I
OH
= 12mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 4mA
--
0.4
I
OL
= 6mA
--
0.55
V
CC
= 2.7V
I
OL
= 4mA
--
0.4
I
OL
= 8mA
--
0.6
V
CC
= 3V
I
OL
= 6mA
--
0.55
I
OL
= 12mA
--
0.8
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH2573A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
5
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
LVC Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
LVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
LVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
LVC Link
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
LVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SWITCH
V
LOAD
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
GND
t
PHZ
0V
V
OL+
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
OH-
V
HZ
LVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
10MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
10MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol V
CC(1)
= 3.3V0.3V V
CC(1)
= 2.7V
V
CC(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74LVCH2573A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
IDT
LVC
XXXX
XX
Package
Device Type
Temp. Range
SO
PY
Q
PG
74
Small Outline IC (gull wing)
Shrink Small Outline Package
Quarter Size Small Outline Package
Thin Shrink Small Outline Package
Octal Transparent D-Type Latch with 3-State Outputs, 12mA
40C to +85C
X
Bus-Hold
2573A
Bus-hold
H
XX
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