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September 21, 2001

2001 Integrated Device Technology, Inc.

DSC 5360/2

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

3.3V ATM PHY
for 25.6 and 51.2 Mbps

Features

Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions of the
Physical Layer

Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6Mbps physical interface

Also operates at 51.2Mbps data rate

8-bit UTOPIA Level 1 Interface

3-Cell Transmit & Receive FIFOs

Receiver Auto-Synchronization and Good Signal Indication

LED Interface for status signalling

Supports UTP Category 3 and 5 physical media

Interfaces to standard magnetics

Low-Power CMOS

3.3V supply with 5V tolerant inputs

64-lead TQFP Package (10 x 10 mm)

Commercial and Industrial Temperature Ranges

Description

The IDT77V106L25 is a member of IDT's family of products

supporting Asynchronous Transfer Mode (ATM) data communications
and networking. The IDT77V106L25 implements the physical layer for
25.6 Mbps ATM, connecting a serial copper link (UTP Category 3 and 5)
to an ATM layer device such as a SAR or a switch ASIC. The
IDT77V106L25 also operates at 51.2 Mbps and is well suited to back-
plane driving applications. The 77V106L25 utilizes an 8-bit UTOPIA
interface on the cell side.

The IDT77V106L25 is fabricated using IDT's state-of-the-art CMOS

technology, providing the highest levels of integration, performance and
reliability, with the low-power consumption characteristics of CMOS.

Applications

Up to 51.2Mbps backplane transmission

Rack-to-rack short links

ATM Switches

Block Diagram

TXREF

TXDATA

TXSOC

TXEN

ALE

RXCLAV

AD[7:0]

INT

RXDATA

RXSOC

RXEN

TXCLAV

RXREF

3 CELL FIFO

UTILITY
BUS
CONTROLLER

3 CELL FIFO

SCRAMBLER

PRNG

DESCRAMBLER

5B/4B

DECODER

S/P

DNRZI

4B/5B

ENCODER

P/S

NRZI

CLK
REC

TXD+

Line

Driver

TXD-

Line

RXVR

RXD+
RXD-

LOOP BACK

RESET

RxLED

OSC

77V106

77v106 drw 01

TXLED

RESET

TXCLK

RXCLK

Pseudo Random
Nibble Genera-
tor

IDT77V106L25

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IDT77V106L25

Figure 1 Pin Assignments

2
3
4
5

7
8

10
11
12

13
14

15
16

RXREF

TXREF

TXLED

TXDATA0
TXDATA1

TXDATA2
TXDATA3

TXDATA4
TXDATA5

TXDATA6
TXDATA7

TXEN

TXSOC

VDD

TXCLAV

X
E
N

I
T

17 18 19

21 22 23 24 25 26 27 28 29 30

AD7
AD6

AD5
AD4

GND
AD3
AD2
AD1

AD0
ALE
CS
RD
WR
RST
INT
RXLED

77v106 drw 02

TXPARITY

77v106 drw 02

Pin 1 Index

IDT77V106

77V106L25 Overview

The 77V106L25 is a physical layer interface chip for 25.6Mbps ATM

network communications as defined by ATM Forum document af-phy-
040.000 and ITU-T I.432.5. The physical layer is divided into a Physical
Media Dependent sub layer (PMD) and Transmission Convergence (TC)
sub layer. The PMD sub layer includes the functions for the transmitter,
receiver and clock recovery for operation across 100 meters of category
3 and 5 unshielded twisted pair (UTP) cable. This is referred to as the
Line Side Interface. The TC sub layer defines the line coding, scram-
bling, data framing and synchronization.

On the cell side, the 77V106L25 connects to an ATM layer device

(such as a switch core or SAR) through an 8-bit Utopia Level 1 interface.

The 77V106L25 is based on the 77105 and maintains significant

Access to these status and control registers is through the utility bus.

This is an 8-bit muxed address and data bus, controlled by a conven-
tional asynchronous read/write handshake.

Additional pins permit insertion and extraction of an 8kHz timing

marker, and provide LED indication of receive and transmit status.

OPERATION AT 51.2 Mbps

In addition to operation at the standard rate of 25.6 Mbps, the

77V106L25 is also specified to operate at 51.2 Mbps. Except for the
doubled bit rate, all other aspects of operation are identical to the 25.6
Mbps mode.

The rate is determined by the frequency of the clock applied to the

OSC input pin. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz
for the 51.2 Mbps line rate.

See Figure 16 for recommended line magnetics. Magnetics for 51.2

Mbps operation have a higher bandwidth than magnetics optimized for
25.6 Mbps.

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IDT77V106L25

Signal Descriptions

Line Side Signals

Signal Name

Pin Number

I/O

Signal Description

RXD+, RXD-

58, 57

Positive and negative receive differential input pair.

TXD+, TXD-

62, 61

Out

Positive and negative transmit differential output pair.

Utility Bus Signals

Signal Name

Pin Number

I/O

Signal Description

AD[7:0]

48, 47, 46,
45, 43, 42,
41, 40

In/
Out

Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this bus when a read
is performed. Input data is sampled at the completion of a write operation.

ALE

Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling edge of ALE. ALE
must be low when the AD bus is being used for data.

Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain asserted at all
times if desired.

Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by deasserting WR
and asserting RD and CS.

Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by deasserting RD,
placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is deasserted.

Utopia Bus Signals

Signal Name

Pin Number

I/O

Signal Description

RXCLAV

Out

Utopia Receive Cell Available. "1" indicates that the receive FIFO contains a complete cell. "0" indicates that it does not.

RXCLK

Utopia Receive Clock. This is a free running clock input.

RXDATA[7:0]

24, 25, 26,
27, 29, 30,
31, 32

Out

Utopia Receive Data. When one of the four ports is selected, the 77V106L25 transfers received cells to an ATM device
across this bus. Also see RXPARITY.

RXEN

Utopia Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA bus.

RXPARITY

Out

Utopia Receive Data Parity. Odd parity over RXDATA[7:0].

RXSOC

Out

Utopia Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.

TXCLAV

Out

Utopia Transmit Cell Available. "1" indicates that the transmit FIFO has room available for at least one complete cell. "0" indi-
cates that it does not.

TXCLK

Utopia Transmit Clock. This is a free running clock input.

TXDATA[7:0]

11, 10, 9, 8,
7, 6, 5, 4

Utopia Transmit Data. An ATM device transfers cells across this bus to the 77V106L25 for transmission. Also see TXPAR-
ITY.

TXEN

Utopia Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA bus.

TXPARITY

Utopia Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated in the Interrupt Sta-
tus Registers, as enabled in the Master Control Register. No other action is taken in the event of an error. Tie high or low if
unused.

TXSOC

Utopia Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.

Table 1 Signal Descriptions (Part 1 of 2)

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IDT77V106L25

Miscellaneous Signals

Signal Name

Pin Number

I/O

Signal Description

INT

Out

Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the interrupt status
in the appropriate interrupt Status Register is read. Interrupt sources are programmable via the interrupt Mask Registers.

OSC

TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz for 25.6 Mbps; 64 MHz for 51.2 Mbps.

RST

Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be performed after power up
prior to normal operation of the part.

RXLED

Out

Receive LED driver. Driven low for 223 cycles of OSC, beginning with RXSOC when a good (non-null and non-errored) cell
is received. Drives 8 mA both high and low.

RXREF

Out

Receive Reference. Active low. RXREF pulses low for a programmable number of clock cycles when an X_8 command byte
is received.

Reserved signal. This input must be connected to logic low.

TXLED

Out

Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when a cell is received for transmission. 8 mA
drive current both high and low

TXREF

Transmit Reference. At the falling edge of TXREF, an X_8 command byte is inserted into the transmit data stream. Typical
application is WAN timing.

Power Supply Signals

Signal Name

Pin Number

I/O

Signal Description

AGND

50, 53, 55

Analog ground. AGND is ground the analog portion of the ship, which sources a more constant current than the digital por-
tion.

AVDO

51, 54, 56,
59

Analog power supply. AVDD supplies power to the analog portion of the chip, which draws a more constant current than the
digital portion. 3.3 + 0.3V

GND

22, 44, 60

Digital Ground.

VDD

15, 28, 63

Digital power supply. 3.3 + 0.3V.

Table 1 Signal Descriptions (Part 2 of 2)

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IDT77V106L25

Functional Description

Transmission Convergence (TC) Sub Layer

Introduction
The TC sub layer defines the line coding, scrambling, data framing

and synchronization. Under control of a switch interface or Segmenta-
tion and Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a 53-
byte ATM cell, scrambles the data, appends a command byte to the
beginning of the cell, and encodes the entire 53 bytes before transmis-
sion. These data transformations ensure that the signal is evenly distrib-
uted across the frequency spectrum. In addition, the serialized bit
stream is NRZI coded. An 8kHz timing sync pulse may be used for
isochronous communications.

Data Structure and Framing
Each 53-byte ATM cell is preceded with a command byte. This byte

is distinguished by an escape symbol followed by one of 17 encoded
symbols. Together, this byte forms one of seventeen possible command
bytes. Three command bytes are defined:

1. X_X (read: 'escape' symbol followed by another 'escape'): Start-

of-cell with scrambler/descrambler reset.

2. X_4 ('escape' followed by '4'): Start-of-cell without scrambler/

descrambler reset.

3. X_8 ('escape' followed by '8'): 8kHz timing marker. This

command byte is generated when the 8kHz sync pulse is
detected, and has priority over all line activity (data or command
bytes). It is transmitted immediately when the sync pulse is
detected. When this occurs during a cell transmission, the data
transfer is temporarily interrupted on an octet boundary, and the
X_8 command byte is inserted. This condition is the only allowed
interrupt in an otherwise contiguous transfer.

Below is an illustration of the cell structure and command byte usage:

{X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell}...

In the above example, the first ATM cell is preceded by the X_X start-

of-cell command byte which resets both the transmitter-scrambler and
receiver-descrambler pseudo-random nibble generators (PRNG) to their
initial states. The following cell illustrates the insertion of a start-of-cell
command without scrambler/descrambler reset. During this cell's trans-
mission, an 8kHz timing sync pulse triggers insertion of the X_8 8kHz
timing marker command byte.

Transmission Description
Refer to Figure 2. Cell transmission begins with the PHY-ATM Inter-

face. An ATM layer device transfers a cell into the 77V106L25 across
the Utopia transmit bus. This cell enters a 3-cell deep transmit FIFO.
Once a complete cell is in the FIFO, transmission begins by passing the
cell, four bits (MSB first) at a time to the 'Scrambler'.

The `Scrambler' takes each nibble of data and exclusive-ORs them

against the 4 high order bits (X(t), X(t-1), X(t-3)) of a 10 bit pseudo-
random nibble generator (PRING). Its function is to provide the appro-
priate frequency distribution for the signal across the line.

The PRNG is clocked every time a nibble is processed, regardless of

whether the processed nibble is part of a data or command byte. Note
however that only data nibbles are scrambled. The entire command byte
(X _C) is NOT scrambled before it's encoded (see diagram for
illustration).

The PRNG is based upon the following polynomial:

+ X

+ 1

With this polynomial, the four output data bits (D3, D2, D1, D0) will be

generated from the following equations:

D3 = d3 xor X(t-3)
D2 = d2 xor X(t-2)
D1 = d1 xor X(t-1)
D0 = d0 xor X(t)

The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and

X(t+1).

A scrambler lock between the transmitter and receiver occurs each

time an X_X command is sent. An X_X command is initiated only at the
beginning of a cell transfer after the PRNG has cycled through all of its
states (2

- 1 = 1023 states). The first valid ATM data cell transmitted

after power on will also be accompanied with an X_X command byte.
Each time an X_X command byte is sent, the first nibble after the last
escape (X) nibble is XOR'd with 1111b (PRNG = 3FFx).

Because a timing marker command (X_8) may occur at any time, the

possibility of a reset PRNG start-of-cell command and a timing marker
command occurring consecutively does exist (e.g. X_X_X_8). In this
case, the detection of the last two consecutive escape (X) nibbles will
cause the PRNG to reset to its initial 3FFx state. Therefore, the PRNG is
clocked only after the first nibble of the second consecutive escape pair.

Once the data nibbles have been scrambled using the PRNG, the

nibbles are further encoded using a 4b/5b process. The 4b/5b scheme
ensures that an appropriate number of signal transitions occur on the
line. A total of seventeen 5-bit symbols are used to represent the sixteen
4-bit data nibbles and the one escape (X) nibble. The table below lists
the 4-bit data with their corresponding 5-bit symbols:

Data

0000
0100
1000
1100

Symbol

10101
00111
10010
10111

Symbol

01001
01101
11001
11101

Data

0001
0101
1001
1101

Symbol

01010
01110
11010
11110

Data

0010
0110
1010
1110

Data

0011
0111
1011
1111

ESC(X) = 00010

3505 drw 05a

Symbol

01011
01111
11011
11111

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IDT77V106L25

This encode/decode implementation has several very desirable prop-

erties. Among them is the fact that the output data bits can be repre-
sented by a set of relatively simple symbols;

Run length is limited to <= 5;

Disparity never exceeds +/- 1.

On the receiver, the decoder determines from the received symbols

whether a timing marker command (X_8) or a start-of-cell command was
sent (X_X or X_4). If a start-of-cell command is detected, the next 53
bytes received are decoded and forwarded to the descrambler. (See the
TC Receive Block Diagram).

The output of the 4b/5b encoder provides serial data to the NRZI

encoder. The NRZI code transitions the wire voltage each time a '1' bit is
sent. This, together with the previous encoding schemes guarantees
that long run lengths of either '0' or '1's are prevented. Each symbol is
shifted out with its most significant bit sent first.

When no cells are available to transmit, the 77V106L25 keeps the

line active by continuing to transmit valid symbols. But it does not
transmit another start-of-cell command until it has another cell for trans-
mission. The 77V106L25 never generates idle cells.

Transmit HEC Byte Calculation/Insertion
Byte #5 of each ATM cell, the HEC (Header Error Control) is calcu-

lated automatically across the first 4 bytes of the cell header, depending
upon the setting of bit 5 of the LED Driver and HEC Status/Control
Register (0x03). This byte is then either inserted as a replacement of the
fifth byte transferred to the PHY by the external system, or the cell is
transmitted as received. A third operating mode provides for insertion of
"Bad" HEC codes which may aid in communication diagnostics. These
modes are controlled by the LED Driver and HEC Status/Control Regis-
ters.

Receiver Description
The receiver side of the TC sublayer operates like the transmitter, but

in reverse. The data is NRZI decoded before each symbol is reassem-
bled. The symbols are then sent to the 5b/4b decoder, followed by the
Command Byte Interpreter, De-Scrambler, and finally through a FIFO to
the UTOPIA interface to an ATM Layer device.

ATM Cell Format

Note that although the IDT77V106L25 can detect symbol and HEC

errors, it does not attempt to correct them.

Bit 7

Bit 0

Header Byte 1

Header Byte 2

Header Byte 3

Header Byte 4

UDF

Payload Byte 1

�

�
�

Payload Byte 48

3505 drw 52

UDF = User Defined Field (or HEC)

Good Signal Bit: Upon resetting the device or re-establishing a

serial link, logic in front of the 4b/5b decoder uses feedback from the 4b/
5b decoder to determine if it is not properly "framed" on the 5-bit
symbols being received. If not properly framed, it will shift its framing,
one bit at a time, until it achieves proper symbol framing. Receipt of an
Escape (X) symbol will also force proper symbol framing.

The IDT77V106L25 monitors line conditions and can provide an

interrupt if the line is deemed 'bad'. The Interrupt Status Register
contains a Good Signal Bit (bit 6, set to 0 = Bad signal initially) which
shows the status of the line per the following algorithm:

To declare 'Good Signal' (from "Bad" to "Good")
There is an up-down counter that counts from 7 to 0 and is initially

set to 7. When the clock ticks for 1,024 cycles (32MHz clock, 1,024
cycles = 204.8 symbols) and no "bad symbol" has been received, the
counter decreases by one. However, if at least one "bad symbol" is
detected during these 1,024 clocks, the counter is increased by one, to a
maximum of 7. The Good Signal Bit is set to 1 when this counter
reaches 0. The Good Signal Bit could be set to 1 as quickly as 1,433
symbols (204.8 x 7) if no bad symbols have been received.

To declare 'Bad Signal' (from "Good" to "Bad")
The same up-down counter counts from 0 to 7 (being at 0 to provide

a "Good" status). When the clock ticks for 1,024 cycles (32MHz clock,
1,024 cycles = 204.8 symbols) and there is at least one "bad symbol",
the counter increases by one. If it detects all "good symbols" and no
"bad symbols" in the next time period, the counter decreases by one.
The "Bad Signal" is declared when the counter reaches 7. The Good
Signal Bit could be set to 0 as quickly as 1,433 symbols (204.8 x 7) if at
least one "bad symbol" is detected in each of seven consecutive groups
of 204.8 symbols.

8kHz Timing Marker

The 8kHz timing marker, described earlier, is a completely optional

feature which is essential for some applications requiring synchroniza-
tion for voice or video, and unnecessary for other applications. When
unused, TXREF should be tied high. Also note that it is not limited to
8kHz, should a different frequency be desired. When looped, a received
X_8 command byte causes one to be generated on the transmit side.

A received X_8 command byte causes the 77V106L25 to issue a

negative pulse on RXREF.

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IDT77V106L25

PHY-ATM Interface

UTOPIA Level 1 is a Physical (PHY) Layer to ATM Layer interface standardized by the ATM Forum. It is used for transferring ATM cells and has

separate transmit and receive channels and specific handshaking protocols. It is defined in ATM Forum documents af-phy-0017 and af-phy-0039.

There is a single 8-bit data bus in the transmit (ATM-to-PHY) direction, and a single 8-bit data bus in the receive (PHY-to-ATM) direction. In addi-

tion to the data bus, each direction also includes a single optional parity bit and several handshaking signals. Please note that the transmit bus and the
receive bus operate completely independently.

Figure 3 Receive Block Diagram

The Utopia signals are summarized below:

Transmit and receive both utilize free running clocks, which are inputs to the 77V106. All Utopia signals are timed to these clocks.

TXDATA[7:0]

ATM to PHY

TXPARITY

ATM to PHY

TXSOC

ATM to PHY

TXEN

ATM to PHY

TXCLAV

PHY to ATM

TXCLK

ATM to PHY

RXDATA[7:0]

PHY to ATM

RXPARITY

PHY to ATM

RXSOC

PHY to ATM

RXEN

ATM to PHY

RXCLAV

PHY to ATM

RXCLK

ATM to PHY

PHY-ATM

Interface
Control -

RECV

NRZI

Decoding

RX +

PRNG

Scramble

Nibble

Reset

RXRef

32.0MHz

Clock

Synthesizer

& PLL

5b/4b

Decoding

Command

Byte

Detection,

Removal,

& Decode

De-

Scrambler

3505 drw 06

OSC

3 Cells

Start of Cell

UTOPIA
Interface

Clock Recovery

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IDT77V106L25

In the transmit direction, the PHY first asserts TXCLAV (transmit cell available) to indicate that it has room in its transmit FIFO to accept at least

one 53-byte ATM cell. When the ATM layer device is ready to begin passing the cell, it asserts TXEN (transmit enable) and TXSOC (start of cell), coin-
cident with the first byte of the cell on TXDATA. TXEN can remain asserted for the duration of the cell transfer, or the ATM device may deassert TXEN
at any time once the cell transfer has begun; data is transferred only when TXEN is asserted.

In the receive direction, RXEN indicates when the ATM device is prepared to receive data. As with transmit, it may be asserted or deasserted at

any time.

Note that this Utopia interface can be operated in either cell-mode or in byte-mode as determined by bit 1 in the Master Control Register. In cell-

mode, which is the default, the 77V106L25 does not assert TXCLAV until it has enough room in it's transmit FIFO to accept a complete cell, and
doesn't assert RXCLAV until it has a complete cell in the receive FIFO. It will not deassert TXCLAV or RXCLAV until at or near the end of the transfer
of a cell.

In byte-mode, the phy can assert TXCLAV before it has room for a complete cell. It will modulate TXCLAV to prevent the FIFO from overflowing.

Likewise, it may assert RXCLAV before a complete cell has been received, and will modulate RXCLAV to prevent the FIFO from underflowing. There
is generally little advantage to the byte-mode, so most users will leave the 77V106L25 in the default cell-mode.

In both transmit and receive, TXSOC and RXSOC (start of cell) is asserted for one clock, coincident with the first byte of each cell. Odd parity is

utilized across each 8-bit data field, which means that for an all-zero pattern. the corresponding parity bit is one.

The following figures show examples of the Utopia Level 1 handshake.

Figure 4 Utopia Transmit Handshake - Single Cell

Figure 5 Utopia Transmit Handshake - Back to Back Cells and TXEN Suspended Transmission

TXCLK

TXSOC

TXCLAV

TXEN

TXDATA[7:0],
TXPARITY

P44

P45

P46

P47

P48

77v106drw16

TXCLK

TXSOC

TXCLAV

TXEN

TXDATA[7:0],
TXPARITY

P46

P47

P48

77v106 drw

77v106drw17

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September 21, 2001

IDT77V106L25

Control and Status Interface

Utility Bus

The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V106. These registers are used to select desired oper-

ating characteristics and functions, and to communicate status to external systems.

The Utility Bus is implemented using a multiplexed address and data bus (AD[7:0]) where the register address is latched via the Address Latch

Enable (ALE) signal.

The Utility Bus interface is comprised of the following pins:

AD[7:0], ALE, CS, RD, WR

Read Operation
Refer to the Utility Bus timing waveforms. A register read is performed as follows:
1. Initial condition:

�

RD, WR, CS not asserted (logic 1)

�

ALE not asserted (logic 0)

2. Set up register address:

�

place desired register address on AD[7:0]

�

set ALE to logic 1;

�

latch this address by setting ALE to logic 0.

3. Read register data:

�

Remove register address data from AD[7:0]

�

assert CS by setting to logic 0;

�

assert RD by setting to logic 0

�

wait minimum pulse width time (see AC specifications)

Write Operation
A register write is performed as described below:
1. Initial condition:

�

RD, WR, CS not asserted (logic 1)

�

ALE not asserted (logic 0)

2. Set up register address:

�

place desired register address on AD[7:0]

�

set ALE to logic 1;

�

latch this address by setting ALE to logic 0.

3. Write data:

�

place data on AD[7:0]

�

assert CS by setting to logic 0;

�

assert WR (logic 0) for minimum time (according to timing specification); reset WR or CS to logic 1 to complete register write cycle.

Interrupt Operations

A variety of selectable interrupt and signalling conditions are provided. They are useful both during `normal' operation, and as diagnostic aids.

Refer to the Status and Control Register List section.

Overall interrupt control is provided via bit 0 of the Master Control Register. When this bit is cleared (set to 0), interrupt signalling is prevented. The

Interrupt Mask Register allows individual masking of different interrupt sources. Additional interrupt signal control is provided by bit 5 of the Master
Control Register. When this bit is set (=1), receive cell errors will be flagged via interrupt signalling and all other interrupt conditions are masked.
These errors include:

Bad receive HEC

Short (fewer than 53 bytes) cells

Received cell symbol error

Normal interrupt operations are performed by setting bit 0 and clearing bit 5 in the Master Control Register. INT (pin 34) will go to a low state

when an interrupt condition is detected. The external system should then interrogate the 77V106L25 to determine which one (or more) conditions
caused this flag, and reset the interrupt for further occurrences. This is accomplished by reading the Interrupt Status Register. Decoding the bits in this
byte will tell which error condition caused the interrupt. Reading this register also:

clears the (sticky) interrupt status bits in the registers that are read

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September 21, 2001

IDT77V106L25

resets INT

This leaves the interrupt system ready to signal an alarm for further problems.

LED Control and Signaling

The LED outputs provide bi-directional LED drive capability of 8 mA. As an example, the RxLED outputs are described in the truth table:

As illustrated in Figure 11, this could be connected to provide for a two-LED condition indicator. These could also be different colors toprovide

simple status indication at a glance. (The minimum value for R should be 330

Figure 10 Utopia Receive Handshake - RXCLAV Suspended Transfer (Octet Mode Only)

TxLED Truth Table

Diagnostic Functions

Figure 11 LED Indicator

Loopback

There are two loopback modes supported by the 77V106. The loopback mode is controlled via bits 1 and 0 of the Diagnostic Control Register.

State

Pin Voltage

Cells being received

Low

Cells not being received

High

State

Pin Voltage

Cells being transmitted

Low

Cells not being transmitted

High

RXCLK

RXSOC

RXCLAV

RXEN

RXDATA[7:0],
RXPARITY

High-Z

77v106drw22

RXLED

TXLED

3.3V

(Indicates: Cells

being received or

transmitted)

(Indicates: Cells are

not being received or

transmitted)

3505 drw 32

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September 21, 2001

IDT77V106L25

Normal Mode
Figure 12 shows normal operating conditions: data to be transmitted is transferred to the TC, where it is queued and formatted for transmission by

the PMD. Receive data from the PMD is decoded along with its clock for transfer to the receiving "upstream system".

PHY Loopback

As Figure 13 illustrates below, this loopback mode provides a connection within the PHY from the transmit PHY-ATM interface to the PHY-ATM

receive interface. Note that while this mode is operating, no data is forwarded to or received from the line interface.

Line Loopback
Figure 14 might also be called "remote loopback" since it provides for a means to test the overall system, including the line. Since this mode will

probably be entered under direction from another system (at a remote location), receive data is also decoded and transferred to the upstream system
to allow it to listen for commands. A common example would be a command asking the upstream system to direct the TC to leave this loopback state
and resume normal operations.

Figure 12 Normal Mode

Figure 13 PHY Loopback

Figure 14 Line Loopback

Counters

Several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions. It is anticipated

Bit 1 Bit 2

Mode

Normal operating mode

PHY Loopback

Line Loopback

TC sublayer

PMD sublayer

Line

Interface

ATM Layer

Device

77v1054 drw 33

Utopia

Interface

ATM Layer

Device

TC sublayer

PMD sublayer

Line

Interface

77v1054 drw 34

Utopia

Interface

ATM Layer

Device

TC sublayer

PMD

sublayer

Line

Interface

77v1054 drw 35

Utopia

Interface

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September 21, 2001

IDT77V106L25

that these counters will be polled from time to time (user selectable) to evaluate performance.

Symbol Error Counters

�

8 bits

�

counts all invalid 5-bit symbols received

Transmit Cell Counters

�

16 bits

�

counts all transmitted cells

Receive Cell Counters

�

16 bits

�

counts all received cells, excluding idle cells and HEC errored cells

Receive HEC Error Counters

�

5 bits

�

counts all HEC errors received

The TxCell and RxCell counters are sized (16 bits) to provide a full cell count (without roll over) if the counter is read once/second. The Symbol

Error counter and HEC Error counter were given sufficient size to indicate exact counts for low error-rate conditions. If these counters overflow, a
gross condition is occurring, where additional counter resolution does not provide additional diagnostic benefit.

Reading Counters
1. Decide which counter value is desired. Write to the Counter Select Register to the bit location corresponding to the desired counter. This loads

the High and Low Byte Counter Registers with the selected counter's value, and resets this counter to zero.

Note: Only one counter may be enabled at any time in each of the Counter Select Registers.

2. Read the Counter Registers (low byte and high byte) to get the value.

Further reads may be accomplished in the same manner by writing to the Counter Select Registers.

Note: The PHY takes some time to set up the low and high byte counters after a specific counter has been selected in the Counter Selector
register. This time delay (in � S) varies with the line rate and can be calculated as follows:

Time delay (� S) = 12.5___

line rate (Mbps)

Loop Timing Feature

The 77V106L25 also offers a loop timing feature for specific applications where data needs to be repeated / transmitted using the recovered clock.

If the loop timing mode is enabled in the Enhanced Control Register 1 bit 6, the recovered receive clock is used as to clock out data on transmit side.
In normal mode, the transmitter transmits data using the multiplied oscillator clock.

Jitter in Loop Timing Mode

One of the primary concerns when using loop timing mode is the amount of jitter that gets added each time data is transmitted. Table 2 shows the

jitter measured at various data rates. The set-up shown in Figure 15 was used to perform these tests. The maximum jitter seen was at TX point 5 and
the minimum jitter was at point 2. The loop timing jitter is defined as the amount of jitter generated by each TX node. In other words, the loop timing
jitter or the jitter added by a loop-timed port in the set-up below is the difference between the Total Output Jitter and the Total Input Jitter.

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September 21, 2001

IDT77V106L25

From the above measurements taken, the amount of jitter being added at each TX point is not significant. These tests were also run for extended

periods of time (64 hours) and no bit errors were seen.

Line Side (Serial) Interface

PHY to Magnetics Interface

A standard connection to 100

and 120 unshielded twisted pair cabling is shown in Figure 16. Note that the transmit signal is somewhat attenu-

ated in order to meet the launch amplitude specified by the standards. The external receive circuitry is designed to attenuate low frequencies in order
to compensate for the high frequency attenuation of the cable.

Also, the receive circuitry biases the positive and negative RX inputs to slightly different voltages. This is done so that the receiver does not receive

false signals in the absence of a real signal. This can be important because the 77V106L25 does not disable error detection or interrupts when an
input signal is not present.

When connecting to UTP at 51.2 Mbps, it is necessary to use magnetics with sufficient bandwidth. Refer to Table 4 for the recommended

magnetics.

Jitter at 25.6Mbps at point 4 with respect to point 1

Jitter at 25.6Mbps at point 5 with respect to point 1

Jitter at 51.2Mbps at point 4 with respect to point 1

Jitter at 51.2Mbps at point 5 with respect to point 1

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September 21, 2001

IDT77V106L25

Status and Control Register List

Master Control Register

Address: 0x00

Interrupt Status Register

Address: 0x01

Bit

Type

Initial State

Function

R/W

0 = OSC
multiplied by one

Clock Multiplier Controls whether or not the OSC reference clock input is multiplied by two to generate the line clock.
Cleared (0) = OSC is multiplied by 1 to generate line clock
Set (1) = OSC is multiplied by 2 to generate line clock

R/W

1 = discard
errored cells

Discard Receive Error Cells
On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive HEC error (if enabled)), this
cell will be discarded and will not enter the receive FIFO.

R/W

0 = all interrupts Enable Cell Error Interrupts Only

If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only "Received Cell Error" (as defined in bit
6) to trigger interrupt line."

R/W

0 = disabled

Transmit Data Parity Check
Directs TC to check parity of TxDATA against parity bit located in TXPARITY.

R/W

1 = discard
idle cells

Discard Received Idle Cells
Directs TC to discard received idle (VPI/VCI = 0 and GFC = 0) cells from PMD without signalling external systems.

R/W

0 = not halted

Halt Tx
Halts transmission of data from TC to PMD and forces the TxD outputs to the "0" state."

R/W

0 = cell mode

UTOPIA Mode Select:
0 = cell mode, 1 = byte mode.

R/W

1 = enable
interrupts

Enable Interrupt Pin (Interrupt Mask Bit)
Enables the INT output pin. If cleared, pin is always high and interrupt is masked. If set, an interrupt will be signaled
by setting the interrupt pin to "0". It doesn't affect the Interrupt Status Registers."

Nomenclature
"Reserved" register bits, if written, should always be written "0"
R/W = register may be read and written via the utility bus
R-only or W-only = register is read-only or write-only
sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only
"0" = `cleared' or `not set'
"1" = `set'

Bit

Type

Initial State

Function

Reserved

0 = Bad Signal Good Signal Bit See definitions earlier in this data sheet.

1 - Good Signal
0 - Bad Signal

sticky 0

HEC error cell received Set when a HEC error is detected on received cell.

sticky 0

"Short Cel" Received
Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected when receiving Start-of-Cell
command bytes with fewer than 53 bytes between them."

sticky 0

Transmit Parity Error
If Bit 4 of the Master Control Register (Transmit Data Parity Check) is set, this interrupt flags a transmit data parity error con-
dition. Odd parity is used.

sticky 0

Receive Signal Condition change This interrupt is set when the received 'signal' changes either from 'bad to good' or from
'good to bad'.

sticky 0

Received Symbol Error Set when an undefined 5-bit symbol is received.

sticky 0

Receive FIFO Overflow Interrupt which indicates when the receive FIFO has filled and cannot accept additional data.

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IDT77V106L25

Diagnostic Control Register

Address: 0x02

Bit

Type

Initial State

Function

R/W

0 = normal

Force TxCLAV Deassert
This feature can be used during line loopback mode to prevent cells from being passed across the Utopia bus for transmission.

R/W

0 = UTOPIA RxCLAV Operation Select

The UTOPIA standard dictates that during cell mode operation, if the receive FIFO no longer has a complete cell available for
transfer from PHY, RxCLAV is deasserted following transfer of the last byte out of the PHY
to the upstream system. With this bit set, early deassertion of this signal will occur coincident with the end of Payload byte 44
(as in octet mode for TxCLAV). This provides early indication to the upstream system of this impending condition.
0 = "Standard UTOPIA RxCLAV"
1 = "Cell mode = Byte mode"

R/W

1 = tri-state

Single/Multi-PHY Configuration Select
0 = single: Never tri-state RxDATA, RxPARITY and RxSOC
1 = Multi-PHY mode: Tri-state RxDATA, RxPARITY and RxSOC when RxEN = 1

R/W

0 = normal

RFLUSH = Clear Receive FIFO
This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC signals this completion by clearing this bit.

R/W

0 = normal

Insert Transmit Payload Error
Tells TC to insert cell payload errors in transmitted cells. This can be used to test error detection and recovery systems at des-
tination station, or, under loopback control, at the local receiving station. This payload error is accomplished by flipping bit 0 of
the last cell payload byte.

R/W

0 = normal

Insert Transmit HEC Error
Tells TC to insert HEC error in Byte 5 of transmitted cells. This can be used to test error detection and recovery systems in
downstream switches, or, under loopback control, the local receiving station. The HEC error is accomplished by flipping bit 0 of
the HEC byte.

1, 0 R/W

00 = normal

Loopback Control
bit # 1 0
0 0 Normal mode (receive from network)
1 0 PHY Loopback
1 1 Line Loopback

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IDT77V106L25

LED Driver and HEC Status/Control Register

Address: 0x03

Low Byte Counter Register [7:0]

Address: 0x04

High Byte Counter Register [15:8]

Address: 0x05

Counter Select Register

Address: 0x06

Note: For proper operation, only one bit may be set in the Counter Selected Register at any time.

Bit

Type

Initial State

Function

Reserved

R/W

0 = enable
checking

Disable Receive HEC Checking (HEC Enable)
When not set, the HEC is calculated on first 4 bytes of received cell, and compared against the 5th byte. When set (=
1), the HEC byte is not checked.

R/W

0 = enable calcu-
late & replace

Disable Transmit HEC Calculate & Replace
When set, the 5th header byte of cells queued for transmit is not replaced with the HEC calculated across the first four
bytes of that cell.

4,3

R/W

00 = 1 cycle

RxREF Pulse Width Select
bit # 4 3
0 0 RxREF active for 1 cycle of the recovered clock
0 1 RxREF active for 2 cycles of the recovered clock
1 0 RxREF active for 4 cycles of the recovered clock
1 1 RxREF active for 8 cycles of the recovered clock

1 = empty

Transmit FIFO Status 1 = TxFIFO empty 0 = TxFIFO not empty

TxLED Status 0 = Cell Transmitted 1 = Cell Not Transmitted

RxLED Status 0 = Cell Received 1 = Cell Not Received

Bit

Type

Initial State

Function

[7:0] R

0x00

Provides low-byte of counter value selected via the Counter Select Register.

Bit

Type

Initial State

Function

[7:0] R

0x00

Provides high-byte of counter value selected via the Counter Select Register.

Bit

Type

Initial State

Function

Reserved

Symbol Error Counter

Tx Cell Counter

Rx Cell Counter Does not count HEC errored cells. even when bit 6 of the Master Control Register is Cleared.

Receive Hec Error Counter

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September 21, 2001

IDT77V106L25

Interrupt Mask Register

Address: 0x07

Note: When set to "1", these bits mask the corresponding interrupt pin (INT). When set to "0", the interrupts are unmasked. These interrupts
correspond to the interrupt status bits in the interrupt Status Registers.

Enhanced Control Register

Address: 0x08

Absolute Maximum Ratings

Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating Conditions

Bit

Type

Initial State

Function

Reserved

R/W

0 = interrupt enabled

HEC Error Cell

R/W

0 = interrupt enabled

Short Cell Error

R/W

0 = interrupt enabled

Transmit Parity Error

R/W

0 = interrupt enabled

Receive Signal Condition Change

R/W

0 = interrupt enabled

Received Cell Symbol Error

R/W

0 = interrupt enabled

Receive FIFO Overflow

Bit

Type

Initial State

Function

0 = not reset

Software Reset
1 = Reset. This bit is self-clearing; it isn't necessary to write "0" to exit reset.

R/W

0 = OSC

Transmit Line Clock (or Loop Timing Mode)
When set to 0, the OSC input is used as the transmit line clock. When set to 1, the recovered receive clock is used as
the transmit line clock.

5-0

R/W

Reserved

Symbol

Rating

Value

Unit

TERM

Terminal Voltage with Respect to GND

-0.5 to +5.5

BIAS

Temperature Under Bias

-55 to +125

� C

STG

Storage Temperature

-55 to +120

� C

OUT

DC Output Current

Symbol

Parameter

Min

Typ

Max

Unit

VDD

Digital Supply Voltage

3.0

3.3

3.6

GND

Digital Ground Voltage

VIH

Input High Voltage

2.0

5.25

VIL

Input Low Voltage

-0.3

0.8

AVDO

Analog Supply Voltage

3.0

3.3

3.6

AGND

Analog Ground Voltage

VDIF

VDD - AVDD

-0.5

0.5

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IDT77V106L25

Recommended Operating Temperature and Supply Voltage

Capacitance (TA = +25� C, F = 1MHz)

DC Electrical Characteristics (All pins except TXD+/- and RXD+/-)

DC Electrical Characteristics (TXD+/- and Output Pins Only)

DC Electrical Characteristics (RXD+/- Output Pins Only)

Note: Differential signal amplitude is twice the amplitude of the individual signals that make up the differential signal.

Grade

Ambient

Temperature

GND, AGND

VDD, ADD

Commercial

� C to +70� C

3.3V � 0.3V

Industrial

-40

� C to +85� C

3.3V � 0.3V

Symbol

Parameter

Conditions

Max

Unit

Input Capacitance

IN =

I/O Capacitance

OUT =

Symbol

Parameter

Test Conditions

Min Max Unit

Input Leakage Current

Gnd

VIN VDD

-5

礎

I/O (as input) Leakage Current

Gnd

VIN VDD

-10

礎

OH1

For AD[7:0] pins only.

Output Logic "1" Voltage

= -2mA, VDD = min

2.4

OH2

For all output pins except AD[7:0], INT and TXD=/-.

Output Logic "1" Voltage

= -8mA, VDD = min

2.4

For all output pins except TXD=/-.

Output Logic "0" Voltage

= 8mA, VDD = min

0.4

DD1

Add 15mA when TXD+/- is a driving load.

Total supply current is the sum of IDD1 and IDD2.

Digital Power Supply Current (VDD pins)

OSC = 32 MHz, all outputs unloaded --

OSC = 64 MHz, all outputs unloaded --

DD2

Analog Power Supply Current (AVDD pins)

OSC = 32 MHz, all outputs unloaded --

OSC = 64 MHz, all outputs unloaded --

Symbol

Parameter

Test Conditions

Min

Max Unit

Output Logic High Voltage

= -20mA

VDD - 0.5V

Output Logic Low Voltage

= 20mA

0.5

Symbol

Parameter

Min

Typ

Max

Unit

RXD+/- input voltage range

VDD

IPP

RXD+/- input peak-to-peak differential voltage

0.6

2*VDD

ICM

RXD+/- input common mode voltage

1.0

VDD/2

VDD-0.5

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IDT77V106L25

UTOPIA Bus Timing Parameters

Figure 17 UTOPIA Transmit Timing Waveforms

Figure 18 UTOPIA Receive Timing Waveforms

Symbol

Parameter

Min

Max Unit

t31

TxCLK Frequency

0.2

MHz

t32

TxCLK Duty Cycle (% of t31)

t33

TxDATA[7:0], TxPARITY Setup Time to TxCLK

t34

TxDATA[7:0], TxPARITY Hold Time to TxCLK

1.5

t35

TxSOC, TxEN Setup Time to TxCLK

t36

TxSOC, TxEN Hold Time to TxCLK

1.5

t37

TxCLK to TxCLAV Invalid (min) and Valid (max)

t39

RxCLK Frequency

0.2

MHz

t40

RxCLK Duty Cycle (% of t39)

t41

RxEN Setup Time to RxCLK

t42

RxEN Hold Time to RxCLK

1.5

t43

RxCLK to RxCLAV Invalid (min) and Valid (max)

t44

RxCLK to RxSOC High-Z

t45

RxCLK to RxSOC Low-Z (min) and Valid (max)

t46

RxCLK to RxDATA, RxPARITY High-Z

t47

RxCLK to RxDATA, RxPARITY Low-Z (min) and Valid (max)

77v106 drw 39

TXEN

TXCLAV

TXDATA[7:0],

TXPARITY

TXSOC

TXCLK

Octet 1

Octet 2

77v106 drw 40

RXEN

RXCLAV

RXDATA[7:0],

RXPARITY

RXSOC

RXCLK

High-Z

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IDT77V106L25

Utility Bus Read Cycle

Utility Bus Write Cycle

Figure 19 Utility Bus Read Cycle

Figure 20 Utility Bus Write Cycle

Name Min

Max Unit

Description

Name Min

Max Unit

Description

Tas

Address setup to ALE

Tapw

ALE min pulse width

Tcsrd

Chip select to read enable

Tas

Address set up to ALE

Tah

Address hold to ALE

Tah

Address hold time to ALE

Tapw

ALE min pulse width

Tcswr

CS Assert to WR

Ttria

Address tri-state to RD assert

Twrpw

Min. WR pulse width

Trdpw

Min. RD pulse width

Tdws

Write Data set up

Tdh

Data Valid hold time

Tdwh

Write Data hold time

Tch

RD deassert to CS deassert

Tch

WR deassert to CS deassert

Ttrid

RD deassert to data tri-state

Taw

ALE low to end of write

Trd

Read Data access

Tar

ALE low to start of read

Trdd

Start of read to Data low-Z

3505 drw 43

ALE

Tah

Tas

Tapw

Tch

Trdd

Trdpw

AD[7:0]

(output)

Tdh

Trd

Ttrid

Tcsrd

Address

Data

Tar

AD[7:0]

(input)

3505 drw 44

ALE

AD[7:0]

Tah

Tas

Tapw

Tch

Tdwh

Tdws

Twrpw

Address

Data (input)

Taw

Tcswr

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IDT77V106L25

OSC, TXREF and Reset Timing

Note: The minimum RESET Pulse Width is either two RxCLK cycles, two TxCLK cycles, or two OSC cycles, whichever is greater (and
applicable).

Figure 21 OSC, TXREF and Reset Timing

AC Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Tcyc

OSC cycle period (25.6 Mbps)
(51.2 Mbps)

30
15

31.25
15.625

33
16.5

ns
ns

Tckh

OSC high time

Tckl

OSC low time

Tcc

OSC cycle to cycle period variation

Ttrh

TXREF High Time

Ttrl

TXREF Low Time

Trspw

Minimum RST Pulse Width

two OSC cycles

Trrpw

RXREF Pulse Width (For default setting in register 0x03 and 25.6
Mbps. Can be programmed for multiples of this amount.)

0.9

1
(31.25ns)

1.1

Receive
Data Bit
Period

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 22

Figure 22 Output Load

* Includes jig and scope capacitances.

3505 drw 45

OSC

RST

Trspw

TXREF

Ttrl

Ttrh

Tcyc

Tckh

Tckl

RXREF

Trrpw

900

1.2K

3.3V

30pF*

D.U.T.

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IDT77V106L25

CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054

for SALES:
800-345-7015 or 408-727-6116
fax: 408-330-1748
www.idt.com

for Tech Support:
email: phyhelp@idt.com
phone: 408-330-1752

Ordering Information

Note: Refer to the 77V106L25 Device Errata for an explanation of how to identify revisions and changes to revisions.

Revision History

4/29/99:

PRELIMINARY. Initial release.

3/23/2000

PRELIMINARY. Various minor corrections.

1/4/2001

Change from PRELIMINARY to FINAL. TXREF, RXCLAV and TXCLAV description update. RXREF description updated, including
LED register and OSC/RXREF timing. Good signal bit improvement (Y step). Added DC electrical characteristics for RXD+/-. Power
supply current values updated. Utility bus timing updated. Utopia bus timing updated. Resistor value change (R5 and R6) in Table 3
on page 17. Master Control Register, Bit 7 function change.

3/8/2001

Changed Package Name from STQFP to TQFP.

3/28/2001

Added RXREF waveform and pulse width information in Figure 21 and minor corrections.

9/21/2001

In Table 1, under Utopia Signals: deleted "When in multi-PHY mode xxCLAV is high impedance when xxEN is high" in the Signal
Description column for both RXCLAV and TXCLAV signals. Added Loop Timing Feature section.

Package

IDT

NNNNN

Device Type

Power

NNN

Speed

Process/

Temp. Range

Blank

Speed in Mb/s

77V106

25Mbps ATM PHY 3.3V

Commercial (0癈 to +70癈)

77v106 drw 50

64-Lead TQFP (PP64-1)

Industrial (-40癈 to +85癈)

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: 77V106

Document Outline

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: 77V106

Document Outline

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: 77V106