1 of 13

November 13, 2000

2000 Integrated Device Technology, Inc.

DSC-7101-1

Gigabit SERDES Transceiver

)

)
)

H
H

D
D

DWX

WXUUUUHV

IEEE 802.3z Gigabit Ethernet compatible

ANSI X3T11 Fibre Channel compatible

1.25 Gbps full duplex transmission and reception in a single
IC

Optical interface through fiber module

10-bit parallel TX and RX interfaces based on EIA/TIA X3T11

Signal Detect, internal or external

Code Group Realignment with Disable

Internal Loopback mode

62.5MHz recovered clock

Low power 3.3V CMOS

Few external components required

64-pin 10mm and 14mm packages

Pin-outs are compatible with industry standard devices

Industrial Temperature (-40°C to +85°C) is available.

$SS

SSOOOOLF

LFD

D
D

DWLRQV

WLRQV

IEEE 802.3z Gigabit media interfaces:

1000BASE-LX Optical

1000BASE-SX Optical

Provides the PMA function of the PHY

High speed custom serial interface

Backplane serial link

Bus extension

'HVVVVFULSWLRQ

FULSWLRQ

The IDT77V7101 is a monolithic 1.25 Gigabits per second (Gbps)

Ethernet Serializer/Deserializer (SERDES) Transceiver. It is designed to
provide the Physical Medium Attachment (PMA) portion of the IEEE
802.3z PHY layer.

7\SLFDO

\SLFDO

\SLFDO $

$SSO

SSO

SSOLLLLF

F
F

D
D

DWLRQ %OR

WLRQ %OR

WLRQ %ORF

F
F

N
N

N '

'LLLLDJU

DJU

DJUDP

The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.

TRANSMIT

BLOCK

CONTROL

RECEIVE

BLOCK

LINK

CONFIG

TXER

TXEN

TXD[7:0]

GTX_CLK

COL

RPT

LEDs

RESET

CRS

MDIO

MDC

RXER
RXDV

RXD[7:0]

RXCLK

COMDET
ENCDET

RCLK[1:0]

RXCG[9:0]

EWRAP

TCLK

TXCG[9:0]

PCS CHIP

IDT77V7101/7111

PMA CHIP

SDT

TRANSMIT

SECTION

RECEIVE

SECTION

TXP

TXN

RXP
RXN

I
I

I
n

t
e

r
f
a

TERMINATION

NETWORK

TERMINATION

NETWORK

I
U

7101 drw 01

IDT77V7101

2 of 13

November 13, 2000

IDT77V7101TM

)XQFWLRQDO

)XQFWLRQDO '

'HVFULSWLRQ

HVFULSWLRQ

2YH

H
H

HUUUUYYYYLLLLH

H
H

Figure 1 shows a block diagram of a typical application. The parallel

interface connects to a Physical Coding Sublayer (PCS) chip. The serial
inputs and outputs connect directly to a fiber optic module for optical
transmission.

Figure 2 shows an internal block diagram of the IDT77V7101. The

TXCG[9:0] inputs receive parallel 10-bit transmit code groups, already
encoded in 8B/10B format by the PCS chip. The code groups are
latched on the rising edges of the incoming 125MHz reference clock
(TCLK). Then they are serialized, and the bit stream is retimed by an
internal PLL that multiplies TCLK up to 1250MHz. This data stream is
transmitted through PECL drivers into the cable or fiber optic module.

The 77V7101 receives serial data from the fiber optic module. It

deserializes the data into 10-bit receive code groups, and recovers a
receive clock (RCLK) from the data stream. RCLK is used to clock-out
the receive code groups to the PCS chip.

RCLK is output at 62.5MHz in two complementary phases as

RCLK[0] and RCLK[1]. RCLK[0] and RCLK[1] are used to clock out
alternating code groups.

A Signal Detect I/O pin has been provided. For fiber optic media, it

can be configured as an input, allowing the fiber module to perform
signal detection.

7UD

UDQ

Q
Q

QVVVVPL

PLWWWW &O

&OR

R
R

F
F

N
N

N 7

/
/

The user-supplied 125MHz transmit reference clock (TCLK) is used

for several functions. As the transmit code group clock, its rising edges
directly strobe the 10-bit input data latch to sample the transmit code
group bus, TXCG[9:0]. Therefore, its edges must be properly aligned to
the incoming parallel transmit data.

TCLK also serves as the frequency reference for the Transmit PLL

Clock Multiplier, which uses it to synthesize the internal clock signals
necessary for 1.25 Gbps signaling.

7UD

UDQ

Q
Q

QVVVVPL

PLWWWW 'D

'DWWWWD 3DW

D 3DW

D 3DWK

K
K

It is assumed that the original 8-bit user data to be transmitted has

already been 8B/10B-encoded into 10-bit transmit code groups by
external PCS logic before being sent to the IDT77V7101 for transmis-
sion. The incoming code groups are received on the Transmit Code
Group bus, TXCG[9:0], and are sampled on the rising edges of TCLK by
the input data latch. Figure 6 shows the timing relationship between the
clock and the parallel data, and the "AC Electrical Characteristics"
section shows the timing requirements for these signals.

The parallel transmit data is sent to the parallel-to-serial converter.

This uses the internal clock signals synthesized by the transmit PLL to
convert the 10-bit transmit data from parallel to serial format, and to
retime each bit at 1250MHz. The least significant bit TXCG[0] is trans-
mitted first.

Figure 1 IDT77V7101 Internal Block Diagram

I
N

DAT

LLE

L T

DRI

LLE

R X C L O C K &

D AT A

R E C O V E R Y

R X

E Q U AL IZ E R

C L O C K

M U L T IP L IE R

P L L

C O M M A
D E T E C T

R X C L O C K

D IV ID E R

DR IVE R

S IG N AL

D E T E C T

E N A B L E O P

T X N

T X P

E W R AP

R X N

R X P

R X C G [9 :0 ]

C O M D E T

E N D E T

R C L K [1]

R C L K [0]

S D T

S D T S E L

P L L C A P 2

P L L C A P 1

T C L K

T X C G [9: 0]

TX SERI AL DATA

TX CLOCK

ENA BLE

RX S E RIAL DATA

REC OVE RED
RX CLOC K

RE-S YNC

125M Hz

1,250MH z

62.5M Hz (V 7101)
125M Hz (V 7111)

125M Hz

1,250MH z

RE-TIM ED R X
SE RIAL DATA

E Q U S E L

3 of 13

November 13, 2000

IDT77V7101TM

The Transmit Line Driver transmits the serial data in differential form

onto the transmit half of the chosen medium. The Line Driver can
connect directly to copper media such as 150W twinax cable (through
DC-blocking capacitors), or through a fiber optic transceiver module to
fiber optic cable.

The Line Driver is a source-follower that provides a voltage-mode

differential PECL-level-compatible output. It has a differential source
impedance of approximately 30W. ENABLEOP must be held to a logic
high level for normal operation. When ENABLEOP is held low, the Line
Driver output is set to a high impedance state.

Refer to the "Medium Attachment" section below for more information

on connecting the line driver to various media.

H
H

HFHL

FHL

FHLYYYYH

H
H

H (TXDOL]

(TXDOL]

(TXDOL]D

D
D

DWLRQ

WLRQ

The 77V7101 has an equalization circuit at the receiver input to

compensate the signal distortion caused by unequalized cable. For
operation over short cables or long internally equalized cables, the
equalizer can be either enabled or disabled.

Users may wish to disable it in cases where crosstalk or reflections

rather than electrical line length are the major causes of signal impair-
ment, such as when the serial link runs through a crowded backplane or
poorly matched connector rather than a long unequalized cable. Doing
so can improve the tolerance of these impairments. The equalizer can
also be disabled for the same reason when interfacing to fiber optic
transceivers or to short or internally-equalized cables.

&OR

&ORF

F
F

N
N

N 5

5HF

HFR

R
R

RYYYYH

H
H

HUUUU\\\\

After the serial input signal has passed through the front end's equal-

izing amplifier, a receive clock must be recovered with which to sample
the incoming data stream. Clock recovery is automatic, with no user
intervention such as PLL training necessary. The internal Receive PLL
locks the phase of its VCO to that of the incoming data to produce a bit-
clock. This bit-clock is then divided down to become the internal
125MHz code-group clock (ICLK). Finally, the recovered receive clock is
output as complementary signals (180ø out of phase with each other) at
RCLK[0] and RCLK[1] at 62.5MHz in the 77V7101. In the 77V7101, the
62.5MHz RCLK[0] and RCLK[1] signals are used to clock out alternating
125MHz code groups.

D
D

DWD

WD 5

5HF

HFR

R
R

RYYYYH

H
H

HUUUU\\\\

Following equalization and buffering, the receive serial data stream is

retimed by the recovered bit-clock, then converted from serial to parallel
form using both bit- and code-group-clocks. Parallel receive data is
clocked into the output data latch by the internal 125MHz code-group-
clock, and output at the Receive Code Group bus, RXCG[9:0].
RCLK[1:0] are used to clock out the data from RXCG[9:0] as described
in "Clock Recovery" above.

&RG

G
G

GH *

H *

H *UUUURXS $OLJQPH

RXS $OLJQPH

RXS $OLJQPHQ

Q
Q

QWWWW

A code group alignment function detects the presence of comma+

characters (0011111xxx) in the receive data stream. If ENDET=1, each
occurrence of a comma+ causes realignment of the bit positions of the
received comma+ code group to match the standard 8B/10B format.
Realignment may be achieved by dropping bits from the data stream
when necessary. Comma+ characters are always clocked out by the
rising edge of RCLK[1]. In the case of the 77V7101 this may entail
stretching RCLK[1:0] half a cycle (nominally 8ns). Subsequent code
groups retain this bit and clock alignment unless shifted by errors. If
ENDET=0, realignment and clock stretching are disabled.

The COMDET output is an indicator for the detection of comma+

characters. When ENDET is high and a comma+ character is detected,
COMDET will go high for half an RCLK period, following the rising edge
of RCLK[0]. Otherwise, it will remain low.

Proper operation of COMDET, RCLK[1:0], and the code group align-

ment function requires that comma+ characters not be received back-to-
back, as per standard 8B/10B encoding.

6LJ

6LJQ

Q
Q

QDO 'HWHFW

DO 'HWHFW

The Signal Detect pin SDT is a bi-directional pin controlled by

SDTSEL. When STDSEL is high, SDT is an output that remains high
when the receive signal amplitude exceeds the Signal Detect threshold
VSD, and receive data will be output normally at RXCG[9:0]. (Note that
this does not indicate that a compliant 1000BASE-X signal is being
received.) A receive signal amplitude below the threshold causes the
SDT output to remain low, and the RXCG[9:0] outputs to all be forced to
logic 1. This helps prevent the generation of random data at the receiver
outputs in the absence of valid incoming data.

When SDTSEL is low, SDT becomes a PECL input to allow external

devices such as fiber optic modules to perform the Signal Detect func-
tion. Signal detection should cause the external device to drive SDT to
PECL logic 1, while insufficient signal amplitude should drive SDT to
PECL logic 0. As before, a logic 0 at SDT will cause RXCG[9:0] outputs
to all be forced to logic 1.

,QW

,QWH

H
H

HUUUUQDO

QDO

QDO /

/
/

/RRSED

RRSED

RRSEDF

F
F

N
N

Loopback mode permits testing most of the internal circuitry without

using an external medium, and is enabled by holding EWRAP high.
Transmit code groups sent to the TXCG[9:0] inputs are processed
normally by the transmit circuitry, then looped back through the receive
circuitry to the RXCG[9:0] outputs as if they were incoming serial data.
At the loopback point, transmit serial data is diverted from before the
Line Driver, and replaces the equalizer output as the input to the clock
and data recovery circuits. Nearly all the internal circuits except for the
Line Driver and Receive Equalizer are exercised, with all internal Serial-
izer, Deserializer, and clock functions occurring at their normal rates.

Loopback mode holds the Line Driver output at PECL logic 1. For

normal operation, EWRAP must be held low.

4 of 13

November 13, 2000

IDT77V7101TM

0HGLXP $WWDFKPHQW

6HULDO ,QWHUIDFH

Figure 3 shows a typical method of connecting either fiber optic links.

In this case 150

bias resistors are connected from TXP and TXN to

ground. AC-coupling of transmitter output to cable is used, as required
by IEEE 802.3z. The optional series resistors RSER may be added to
help absorb reflections due to mismatched loads. Typical values range
from 0-50

. The amount of output attenuation desired should also be

considered when setting these values. Load terminations, transmission
lines (including traces) and connectors should be selected or designed
to have matching impedances.

7KH

KHUUUUPDO

PDO

PDO &

&RQVLGH

RQVLGH

RQVLGHUUUUD

D
D

DWLRQV

WLRQV

The 77V7101 consumes less than 625 mW at peak power. The

device is guaranteed in an ambient temperature range of 0

to +70

for commercial temperature devices; -40

to +85

for industrial tempera-

ture devices.

H
H

HYLVLR

YLVLR

YLVLRQ

Q
Q

Q +LVWR

+LVWR

+LVWRUUUU\\\\

July 1, 1999: Initial publication.

September 14, 1999: Deleted drawing on page 3.

October 6, 1999: Revised Figure 2. Changed figure numbers. Added

"Recommended Operating Conditions."

October 21, 1999: Revised "Receive Equalization" session.

Changed t

JTT

from "200 ps pk-pk" to "40 ps RMS." Changed cable

length from 30m to 25m.

April 21, 2000: Removed references to 77V7114, 1000BASE-CX,

and TwinAx cable. Deleted the figure "Typical 1000BASE-CX Medium
Attachment."

September 15, 2000: Changed 100

to 115

on page 5.

November 13, 2000: Added Thermal Considerations section. Added

Industrial Temperature information to Features and Ordering Information
sections.

7 of 13

November 13, 2000

IDT77V7101TM

3LQ 'HVFULSWL

3LQ 'HVFULSWLR

R
R

RQV

7UD

UDQVPLW6LGH 6LJQDO

QVPLW6LGH 6LJQDO

QVPLW6LGH 6LJQDOVVVV

H
H

HFHL

FHL

FHLYYYYH

H
H

H6LGH 6LJQDOV

6LGH 6LJQDOV

&RQW

&RQWUUUURO 6LJQDOV

RO 6LJQDOV

Pin #

Name

Type

Description

TCLK

TTL Input

The transmit code group clock, 1/10 the serial baud rate, whose rising edges are used to sample the
incoming transmit code groups (TXCG[9:0]). TCLK is also the reference clock used by the transmit
PLL to synthesize the high-speed serial data clock.

13,12,11,9,8,7,
6,4,3,2

TXCG[9:0]

TTL Inputs

The PMA chip's transmit code group input port, accepting 10-bit parallel transmit data already
encoded in 8B/10B format. This bus is clocked into the chip on the rising edge of TCLK. TXCG[0] is
the least significant bit and the first to be transmitted.

62,61

TXP,TXN

HS Output

The high-speed + and - serial data differential outputs to the cable or fiber optic transmitter. For output
= "1", TXP > TXN.

Table 1 Transmit-Side Signals

Pin #

Name

Type

Description

54, 52

RXP, RXN

HS Input

The high-speed serial data differential inputs from the twisted-pair cable or fiber optic receiver. For
input = "1", RXP > RXN.

34,35,36,38,
39,40,41,43,
44,45

RXCG[9:0]

TTL Output

The PMA chip's receive code group output port, presenting 10-bit receive data on alternate rising edges
of RCLK[0] and RCLK[1] for the V7101. If ENCDET = 1, comma + code groups are realigned and
forced to be clocked by RCLK[1]. RXCG[9:0] are forced high when SDT = 0. RXCG[0] is the least sig-
nificant bit and the first to be received.

30, 31

RCLK1
RCKL0

TTL Output

The complementary receive clock outputs, recovered from the received serial data. The V7101
RCLK[1:0] outputs are 1/20 the serial baud rate, and clock-out alternate receive code groups from
RXCG[9:0] on their rising edges. If ENCDET = 1. RCLK[1] clocks all comma + characters.

Table 2 Receive-Side Signals

Pin #

Name

Type

Description

COMDET

TTL Output

When ENCDET=1 and a comma+ character is detected in the receive bit stream, COMDET will go
high for half an RCLK period in the V7101, or one clock period in the V7111, following the rising edge
of RCLK[0].

ENABLEOP

TTL Input

A high level on this pin is required to activate the Line Driver, which otherwise remains in a high
impedance state. An internal 50k pull-up resistor prevents "floating". Hold ENABLEOP high for normal
operation.

ENCDET

TTL Input

A logic 1 input enables code group realignment on comma+ reception. A logic 0 input keeps current
word alignment and disables COMDET. An internal 50k pull-up resistor prevents "floating".

EQUSEL

TTL Input

Mode Select input for Equalizer. If

EQUSEL

=0, equalization is on. If

EQUSEL

=1, equalization is off.

Equalization may be turned on for all cable lengths. An internal 50k pull-down resistor prevents "float-
ing". Hold

EQUSEL

low for normal operation.

Table 3 Control Signals (Part 1 of 2)

8 of 13

November 13, 2000

IDT77V7101TM

R
R

ZHU 6XSS

HU 6XSS

HU 6XSSOOOO\\\\ 3

3LQV

LQV

(OHFWULFDO 6S

(OHFWULFDO 6SH

H
H

HFLILF

FLILF

FLILFD

D
D

DWLRQV

WLRQV

$EVROXWH 0D

$EVROXWH 0D[

[
[

[LPXP 5

LPXP 5

LPXP 5D

D
D

DWLQJV

WLQJV

EWRAP

TTL Input

"Enable Wrap," this signal must be at a logic low level for normal operation. A high logic level forces
the transmit data to be looped back from TXCG[9:0] to RXCG[9:0], exercising most of the internal cir-
cuitry. An internal 50k pull-down resistor prevents "floating". Hold EWRAP low for normal operation.

16
17

PLLCAP1
PLLCAP2

Analog

A .001

F capacitor is connected between these pins to set the loop filter characteristics of the trans-

mit PLL.

SDT

Bi-directional
PECL Input
TTL Output

Signal Detect, with direction controlled by SDTBYPASS. If SDTBYPASS is high, SDT is a TTL output,
where a logic 1 indicates that the receiver input level is above the internal "signal detect" threshold. If
SDTBYPASS is low, SDT becomes a PECL input, enabling signal detection by external devices such
as fiber optic transceivers. In any case, a logic 0 at SDT forces all RXCG[9:0] signals high, while a
logic 1 allows normal operation.

SDTBYPASS

TTL Input

Signal Detect direction control. If SDTBYPASS=0, SDT is a PECL level input. If SDTBYPASS=1, SDT
is a TTL output. (See SDT description above.) An internal 50k pull-up resistor prevents "floating". Hold
SDTBYPASS high for normal operation.

UNUSED

TTL Input

This pin must be connected to VCC.

UNUSED

Output

This pin should be left unconnected.

Pin #

Name

Type

Description

5,10,18,20, 28,29,37,42,50,53,55,57,60,63

Power

Positive supply pins.

1,14,15,21, 25,32,33,46,51,56,58,64

GND

Power

Ground supply pins.

Table 4 Power Supply Pins

Parameter

Min.

Max.

Unit

DC Supply Voltage (V

)

-0.5

Terminal Voltage with respect to GND

-0.5

Terminal Voltage with respect to V

+0.5

Storage Temperature Range

-40°

+150°

Celsius

Table 5 Absolute Maximum Ratings

Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operations sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for extended periods may affect reliability.

Pin #

Name

Type

Description

Table 3 Control Signals (Part 2 of 2)

9 of 13

November 13, 2000

IDT77V7101TM

H
H

HFRPPHQGHG

FRPPHQGHG

FRPPHQGHG 2

2SH

SHUUUUD

D
D

DWLQJ &RQGLWL

WLQJ &RQGLWL

WLQJ &RQGLWLR

R
R

RQV

'& (OHFWULFDO

'& (OHFWULFDO &KDU

&KDU

&KDUDFWHULVWLFV

DFWHULVWLFV

,
,
,
,Q

Q
Q

F
F

FOOOOXG

XGH

H
H

HVVVV DOO ,

DOO ,

DOO ,2 S

2 S

2 SLLLLQ

Q
Q

QV H[

V H[

V H[F

F
F

H
H

HSW

SW 7;

7;3

3 7

7;1

;1 5

5;3

;3 5;1

5; 1

$& (OHFWULFD

& (OHFWULFD

& (OHFWULFDOOOO &KD

&KD

&KDUUUUDFWHULVWLFV

DFWHULVWLFV

Symbol

Parameter

Min.

Typ.

Max.

Unit

DC supply voltage

3.15

3.3

3.45

Ambient Temperature

-40

+85

°C

Table 6 Recommended Operating Conditions

Symbol

Parameter

Test Conditions

Test conditions are Recommended Operating Conditions unless otherwise noted.

0LQ

7\S

0D[

8QLW

, TTL

Not for SDT.

TTL Input High Voltage

2.0

+ 0.5

, TTL

TTL Input Low Voltage

-0.3

0.80

, PECL

For SDT only, when SDTSEL is logic low.

PECL Input High Voltage

SDTSEL is low

- 1.165

+ 0.5

, PECL

PECL Input Low Voltage

SDTSEL is low

-0.3

- 1.475

Input High Current

= 3.45V, VIN = 2.4V

Input Low Current

= 3.5V, VIN = 0.4V

-600

Output High Voltage

= 3.15V, IOUT = -400

2.2

Output Low Voltage

= 3.15V, IOUT = 1mA

0.5

Input Capacitance

Transceiver V

Supply Current

= 25°

180

DC supply voltage

3.15

3.3

3.45

Power dissipation

570

890

Table 7 DC Electrical Characteristics (Includes all I/O pins except TXP, TXN, RXP, RXN)

6\PERO

3DUDPHWHU

7HVW &RQGLWLRQV

0LQ

7\S

0D[

8QLW

fBD

Serial Baud Rate

1000

1250

1360

MBaud

fREF

TCLK Reference Frequency

fBD/10

MHz

fTOL

TCLK Frequency Tolerance

-100

+100

ppm

tDC, TC

TCLK Duty Cycle

tJTT

TCLK Jitter

ps RMS

tR, TC

TCLK Rise Time

0.8V to 2.0V

0.7

2.4

tF, TC

TCLK Fall Time

2.0V to 0.8V

0.7

2.4

fRCLK

RCLK Frequency (77V7101)

fBD/20

MHz

tR, RC

RCLK Rise Time

0.8V to 2.0V, CL = 10pF

0.7

2.4

Table 8 AC Electrical Characteristics (Part 1 of 2)

10 of 13

November 13, 2000

IDT77V7101TM

tF, RC

RCLK Fall Time

0.8V to 2.0V, CL = 10pF

0.7

2.4

tDC, RC

RCLK Duty Cycle

1.4V to 1.4V, CL = 10pF

tA-B

RCLK0 to RCLK1 rising edge skew (77V7101)

1.4V to 1.4V, CL = 10pF

7.5

8.5

tR, RX

RXCG Rise Time

0.8V to 2.0V, CL = 10pF

0.7

tF, RX

RXCG Fall Time

0.8V to 2.0V, CL = 10pF

0.7

tSU, RX

RXCG Setup Time to rising RCLK

{0.8,2.0}V to 1.4V, CL = 10pF

2.5

tHO, RX

RXCG Hold Time from rising RCLK

1.4V to {0.8,2.0}V, CL = 10pF

1.5

tR, TX

TXCG Rise Time

0.8V to 2.0V

0.7

tF, TX

TXCG Fall Time

0.8V to 2.0V

0.7

tSU, TX

TXCG Setup Time to rising TCLK

{0.8,2.0}V to 1.4V

2.0

tHO, TX

TXCG Hold Time to rising TCLK

1.4V to {0.8,2.0}V

1.0

tLAT, TX

Transmit Latency

tLAT, RX

Receiver Latency

Signal Detect Threshold

200

100

mV pk-pk

IHS

HS Input Differential Voltage

200

2000

mV pk-pk

OHS

HS Output Differential Voltage

1100

2000

mV pk-pk

OHS, OFF

HS Output Differential Off Voltage

170

mV pk-pk

tR, HS

HS Output Differential Rise Time

327

tF, HS

HS Output Differential Fall Time

327

TOTAL

Total Transmit Jitter

192

ps pk-pk

Test conditions are Recommended Operating Conditions unless otherwise noted.

1250 Mbaud ±100ppm is the rate specified by IEEE 802.3z.

IEEE does not specify code group maximum rise and fall times, but TXCG and RXCG inputs and outputs must meet the required setup and hold times.

Transmitter latency is the time from the positive edge of TCLK that clocks in a particular transmit code group to the differenti al first edge of the first bit of that code group to

be transmitted at TXP/N. Reference levels are 1.4V for TCLK, and zero-crossing for AC-coupled TXP-TXN.

Receiver latency is the time from the differential first edge of the first bit of a particular code group received at RXP/N to the positive edge of the RCLK output (RCLK

RCLK

) that clocks out that code group. Reference levels are 1.4V for RCLK and zero-crossing for AC-coupled RXP-RXN.

Total jitter at this component level is specified by IEEE 802.3z at TP1, as they define test points. See subclauses 38.5, 38.6.8 -9, and 39.3.3 for system level specifications

and measurement methods.

6\PERO

3DUDPHWHU

7HVW &RQGLWLRQV

0LQ

7\S

0D[

8QLW

Table 8 AC Electrical Characteristics (Part 2 of 2)

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 77V7101

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 77V7101

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 77V7101