1
1999 Integrated Device Technology, Inc.
March 1999
IDT79RV4640/IDT79RC64V474
PCI MEZZANINE CARD
PRELIMINARY
IDT7M9510
IDT7M9514
FEATURES:
PCI Mezzanine Card (PMC) (IEEE 1386) form factor
7M9510 High performance IDT79RV4640 MIPS Processor
100Mhz, 150Mhz, 180Mhz, 200MHz CPU speeds supported
50MHz maximum CPU bus frequency
33MHz maximum PCI bus frequency
7M9514 High performance IDT79RC64V474 MIPS Processor
180Mhz, 200Mhz, 250Mhz CPU speeds supported
50MHz maximum CPU bus frequency
33MHz maximum PCI bus frequency
DRAM
72-position SIMM slot
4MB to 128MB of DRAM supported
32-bit width
Flash
2MB of on board Flash memory
32-bit width
EPROM
up to 512KB
8-bit width
32 Pin PLCC socket
Two serial interface ports (16550A compatible)
Uses Galileo GT-64011 PCI System controller
DMA
four independent channels
chaining via linked lists of records
byte alignment on source and destination
transfers through a 32 byte internal FIFO
which moves data between PCI, memory and devices
FUNCTIONAL BLOCK DIAGRAM
PCI
host to PCI bridge
PCI to main memory bridge
fully compatible to PCI rev 2.1
high performance PCI interfaces via 96 bytes of posted write
and read prefetch buffers
Other Features
Manual Cold Reset (Pushbutton and two pin header)
hardware based masking of interrupts
Configurable Timer Interrupt Generator
32 Bits of user defined I/O mapped through system FPGA
VxWorks Board Support Package available from IDT
DESCRIPTION:
The IDT7M9510/7M9514 is a Single Board Computer utilizing IDT's
79RV4640/79RC64V474 MIPS processor. This CPU Mezzanine Card is
designed for use in applications where low profile, parallel board to board
mounting is required. The 7M9510/7M9514 consists of an IDT79RV4640 /
IDT79RC64V474 processor based subsystem that can either form the core
CPU function for an embedded application, or can be an optional add-in
accelerator to a PCI based system through a PCI v2.1 compatible, PMC
Standard (IEEE P1386.1) connector.
The card conforms, in length and width to the standard single size PMC form
factor as specified in IEEE P1386.1, and it contains all the features required of
a typical CPU subsystem for embedded processor applications. Some of these
features include: DRAM, Flash, serial ports and full PCI interrupt support.
4095 drw 01
DR AM
EPR O M
SIO
Serial
connector
System
FPG A
Flash
W atch Dog
Tim e r
Device Bus
ID T
RV4640/
RC64V474
G T-64011
33M hz
PCI Bus
8
32
Serial
connector
32
PM C Use r I/O H eader
32
CP
U
Bu
s
32
2
1999 Integrated Device Technology, Inc.
IDT
IDT7M9510 / IDT7M9514
SYSTEM FPGA
The system FPGA is responsible for the following functions: Processor
initialization, Reset Control, Device Decoding, Interrupt Masking / Mapping.
PROCESSOR INITIALIZATION
The 79RV4640 / 79RC64V474 requires a serial data stream for initializa-
tion. The initialization process is handled by the system FPGA.
RESET CONTROL
Once the FPGA is loaded, the CPU is booted by sequencing the VCCOK,
WARMRESET, COLDRESET lines. At boot-up, the CPU applies MODECLOCK
to the FPGA to read out several bytes of configuration information using the
MODEIN line.
There is a push button for resetting the 7M9510 / 7M9514. This is connected
to the FPGA through the SYSRESET signal. Additionally, a 2-pin header is
provided for connection to an external reset switch.
INTERRUPT STRUCTURE
The system FPGA implements a basic interrupt controller that maps the
various interrupt sources to the CPU interrupts. It also gives the CPU the ability
to mask interrupts and generate PCI interrupts.
PCI INTERFACE
The GT-64011 includes a full featured host to PCI bridge which can operate
as either a target or initiator. For improved performance the bridge contains 96
bytes of posted write and read prefetch buffers.
The GT-64011 initiates PCI cycles when either the CPU or the DMA engine
generates a bus cycle to PCI address space. These cycles can be either
Memory, Interrupt Acknowledge, Special, I/O, or Configuration cycles. Con-
figuration registers can be accessed from either the host bus or the PCI bus.
The GT-64011 includes a full featured DRAM controller and generates all
control signals for the DRAM SIMM.
Further information can be found in the GT-64011 Data Sheet, available
from Galileo Technology.
PC16552 DUAL SERIAL PORT CONTROLLER
The PC16552D is a Dual Universal Asynchronous Receiver/Transmitter.
Each independent channel is software compatible with the PC16550D. Further
information can be found in the PC16552D Data Sheet, available from National
Semiconductor.
WATCHDOG TIMER
The WatchDog Timer generates a non-maskable interrupt from a
MAX706TCSA. It is used to control the system reset logic and to provide a
watchdog reset. Further information can be found in the MAX706 Data Sheet,
available from Maxim.
BOARD OVERVIEW
The IDT7M9510/9514 consists of the following functional blocks:
IDT79RV4640/IDT79RC64V474 MIPS processor, Galileo GT-64011 PCI
System Controller, DRAM memory, system Glue Logic (FPGA based), Flash/
EPROM and dual serial channels. The IDT7M9510/9514 CPU subsystem is
designed to interface with its targeted system through a standard PCI Mezzanine
Card form factor.
IDT79RV4640 PROCESSOR
The IDT79RV4640 is a high performance cost-effective MIPS processor
targeted at embedded applications which runs at internal frequencies from
100MHz to 200MHz. Further information can be found in the 79RV4640 Data
Sheet, available from IDT.
IDT79RC64V474 PROCESSOR
The IDT79RC64V474 is a high performance cost-effective MIPS processor
targeted at embedded applications which runs at internal frequencies from
180MHz to 250MHz. Further information can be found in the 79RC64V474 Data
Sheet, available from IDT.
GT-64011 PCI SYSTEM CONTROLLER
The GT-64011 is a system support device from Galileo Technology, Inc.
This chip provides the bulk of the system control and support functions required
for a MIPS RV4640/RC64V474 CPU based system. The GT-64011 has a three
bus architecture. These three busses are: a CPU bus interface, a PCI bus
interface and a memory/device bus interface. In addition the GT-64011 contains
a DRAM controller and a DMA controller. Further information can be found in
the GT-64011 Data Sheet, available from Galileo Technology.
DRAM
The main memory is implemented using one standard 72-position DRAM
SIMM providing a 32-bit path to memory.
The main memory is designed to support one or two banks of DRAM which
is dependent on the type of SIMM being used. One bank is supported when
a single bank DRAM SIMM is used (e.g., 1M x 32), and two banks are
supported when a double bank DRAM SIMM is used (e.g., 2M x 32). The
design can use any standard DRAM SIMM containing 4MB (1M x 32), 8MB
(2M x 32), 16 MB (4M x 32), or 32MB (8M x 32), 64MB (16M x 32), or 128MB
(32M x 32) allowing the 7M9510/7M9514 to have up to a maximum of 128MB
of memory. 60ns memory is recommended. The memory configuration is
flexible and is field upgradeable.
BOOT EPROM
The Boot EPROM is a standard 512K x 8 EPROM which holds the boot
code, the debug monitor and power-on diagnostics. (Socket supports Flash
chip for development)
FLASH MEMORY
The 7M9510 / 7M9514 has 2MB of Flash on board, configured as 512K
x 32.
3
1999 Integrated Device Technology, Inc.
IDT
IDT7M9510 / IDT7M9514
SERIAL PORTS
There are two RS232-C serial port connectors on the 7M9510 / 7M9514
which are labeled on the board as "COM1" and "COM2". The Pin #1 reference
marking on the PCB should be utilized to ensure proper orientation when
connecting adapter cables to the header.
DCD 1 2 DSR
RD 3 4 RTS
TD 5 6 CTS
DTR 7 8 RI
GND 9 10 NC
SOFTWARE MEMORY MAP
The following is the default memory map of the IDT7M9510 / 7M9514. These
values can be changed by writing to the appropriate address decode registers
in the GT-64011. For further information on reconfiguring the Memory Map refer
to the GT-64011 Data Sheet, available from Galileo Technology.
SERIAL HEADER PINOUT (COM1, COM2)
(Top View)
4095 tbl 01
4095 tbl 02
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4095 tbl 03
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Notes:
1. Non-Condensing
4
1999 Integrated Device Technology, Inc.
IDT
IDT7M9510 / IDT7M9514
BOARD DIMENSIONS
14.278
5.924
6.178
14.024
M ax Com ponent Height
Top
M ax Com ponent Height
B ottom
SIDE VIEW
4095 drw 02
4095 drw 03
NOTES:
1. All dimensions in millimeters (mm).
.
FPGA
FLASH
512Kx8
DUART
X
T
A
L
PLL
PN1
PN2
PN4
73.873
74.127
148.873
149.127
FLASH
512Kx8
FLASH
512Kx8
FLASH
512Kx8
.
GT-64011
DRAM
SIMM
SCKT
BOOT
EPROM
COM1
COM2
RV4640/
RC64V474
CONFIG
EPROM
Pi
n
1
Pi
n
1
RESET
TO P V IE W
B O T TO M V IE W
5
1999 Integrated Device Technology, Inc.
IDT
IDT7M9510 / IDT7M9514
PMC CONNECTORS
The 7M9510 / 7M9514 utilizes three 64 position connectors that are
compliant with the PMC standard. The placement of these connectors is in
compliance with the Common Mezzanine Card (CMC) Specification (IEEE
1386) and the PCI Mezzanine Card (PMC) Specification (IEEE 1386.1).
Headers correspond as follows:
-J1 on the 7M9510 / 7M9514 corresponds to PN11 (PN1) and P12
(PN2) in the PMC and CMC Specifications.
-J2 on the 7M9510 / 7M9514 corresponds to P14 (PN4) in the PMC
and CMC Specifications.
For further information on the mechanical placement of the PMC
headers, refer to the Common Mezzanine Card (CMC) Specification (IEEE
1386).
PIN ASSIGNMENTS
The 32-bit bus is implemented in J1 (PN1 and PN2), in compliance with
the PMC Specifications and is provided below. The User-Defined I/O is
implemented in J2 (PN4) and is provided below.
1
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NOTES:
1. Not connected on 7M9510 / 7M9514
4095 tbl 04
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4095 tbl 05
6
1999 Integrated Device Technology, Inc.
IDT
IDT7M9510 / IDT7M9514
7M9510SR Version
The "SR" version of the 7M9510 is intended for customers using the I-Cube
Raptor
TM
Fast Ethernet Switch Design. In this configuration, the Boot ROM
shipped with the 7M9510 contains the most recent version of the I-Cube "Mini-
Boot Monitor" (MBM). For applications other than the I-Cube Raptor
TM
Reference Design and the I-Cube FPGA configuration PROM, the recom-
mended board configuration is the 7M9510SE which ships with IDT/Sim and
IDT FPGA configuration PROM.
7M9510SE Version (EVALUATION)
The "SE" version of the 7M9510 is packaged to support software develop-
ment and prototyping. Currently the Evaluation package contains the following
material:
- 1 7M9510S
- 1 8MB (2M x 32) EDO DRAM SIMM
- 1 512KB (512K x 8) IDT/Sim Boot ROM
Alternately, the 7M9710 Development Kit may be ordered. This kit
includes all of the 7M9510SE components listed above. In addition the
7M9710 includes the following items:
- 1 set of 7M9510 board schematics
- 1 copy of 7M9510 Datasheet
- 2 10 pin Serial Port to DB9 Adapter Cables
- 2 6 foot DB9 to DB9 null modem serial cables
- 1 7M9502 PCI Backplane
- 1 7M9710 Quickstart Guide
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6
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1
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1
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8
1
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0
2
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1
2
#
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2
2
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2
2
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4
2
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6
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2
7
2
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3
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2
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3
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4
3
#
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3
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3
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N
8
3
9
3
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0
4
1
4
C
N
C
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2
4
3
4
C
N
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N
4
4
5
4
C
N
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N
6
4
7
4
C
N
C
N
8
4
9
4
C
N
C
N
0
5
1
5
C
N
C
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2
5
3
5
C
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4
5
5
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6
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5
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6
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6
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2
6
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2
6
3
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3
6
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4
6
NOTES:
1. All of the User I/O pins are mapped through the on board FPGA.
4095 tbl 06
7
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015
408-988-5647
Santa Clara, CA 95054
fax: 408-492-8674
ssdhelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
4095 drw 04
X
Power
X
Speed
X
Package
X
Process/
Tem perature
Range
Blank
Comm ercial (0
o
C to +70
o
C)
M
PM C-Standard PCI Connection
250
200
180
150
100
S
SE
SR
Standard Configuration (2M B Flash/0M B DRA M)
Evaluation Configuration (2MB Flash/8M B DRAM )
I-C ube Raptor Version
XX XXX
Device
Type
7M9510
7M9514
IDT79RV4640 Processor-based card
IDT79RC64V 474 Processor-based card
IDT
Processor Core Frequency (MHz)
}
}
7M 95 14 O nly
7M 95 10 O nly
PDF 
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