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Quad T1/E1/J1 Long Haul /
Short Haul Transceiver
IDT82P2284
Version -
April 25, 2003
2975 Stender Way, Santa Clara, Califormia 95054
Telephone: (800) 345-7015 TWX: 910-338-2070 FAX: (408) 492-8674
Printed in U.S.A.
2001 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos-
sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe-
cuted between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
i
April 25, 2003
Table of Contents
*Notice: The information in this document is subject to change without notice
FEATURES ........................................................................................................................................................................ 1
APPLICATIONS ................................................................................................................................................................ 1
BLOCK DIAGRAM ............................................................................................................................................................ 2
1 PIN ASSIGNMENT ........................................................................................................................................................... 3
2 PIN DESCRIPTION ........................................................................................................................................................... 4
3 FUNCTIONAL DESCRIPTION ........................................................................................................................................ 12
3.1 T1 / E1 / J1 MODE SELECTION .................................................................................................................................................................. 14
3.2 RECEIVER IMPEDANCE MATCHING ......................................................................................................................................................... 15
3.3 ADAPTIVE EQUALIZER .............................................................................................................................................................................. 17
3.4 DATA SLICER .............................................................................................................................................................................................. 17
3.5 CLOCK AND DATA RECOVERY ................................................................................................................................................................ 17
3.6 RECEIVE JITTER ATTENUATOR ............................................................................................................................................................... 18
3.7 DECODER .................................................................................................................................................................................................... 19
3.7.1 Line Code Rule ............................................................................................................................................................................... 19
3.7.1.1 T1 / J1 Mode .................................................................................................................................................................... 19
3.7.1.2 E1 Mode ........................................................................................................................................................................... 19
3.7.2 Decode Error Detection ................................................................................................................................................................. 19
3.7.2.1 T1 / J1 Mode .................................................................................................................................................................... 19
3.7.2.2 E1 Mode ........................................................................................................................................................................... 19
3.7.3 LOS Detection ................................................................................................................................................................................ 20
3.8 FRAME PROCESSOR ................................................................................................................................................................................. 23
3.8.1 T1/J1 Mode ...................................................................................................................................................................................... 23
3.8.1.1 Synchronization Searching ............................................................................................................................................... 23
3.8.1.1.1 Super Frame (SF) Format ............................................................................................................................. 23
3.8.1.1.2 Extended Super Frame (ESF) Format ........................................................................................................... 24
3.8.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 25
3.8.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 26
3.8.1.2 Error Event And Out Of Synchronization Detection .......................................................................................................... 27
3.8.1.2.1 Super Frame (SF) Format ............................................................................................................................. 27
3.8.1.2.2 Extended Super Frame (ESF) Format ........................................................................................................... 27
3.8.1.2.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 27
3.8.1.2.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 27
3.8.1.3 Overhead Extraction (T1 Mode SLC-96 Format Only) ..................................................................................................... 28
3.8.1.4 Interrupt Summary ............................................................................................................................................................ 28
3.8.2 E1 Mode .......................................................................................................................................................................................... 30
3.8.2.1 Synchronization Searching ............................................................................................................................................... 32
3.8.2.1.1 Basic Frame .................................................................................................................................................. 32
3.8.2.1.2 CRC Multi-Frame ........................................................................................................................................... 33
3.8.2.1.3 CAS Signaling Multi-Frame ........................................................................................................................... 34
3.8.2.2 Error Event And Out Of Synchronization Detection .......................................................................................................... 34
3.8.2.2.1 Out Of Basic Frame Synchronization ............................................................................................................ 35
3.8.2.2.2 Out Of CRC Multi-Frame Synchronization .................................................................................................... 35
3.8.2.2.3 Out Of CAS Signaling Multi-Frame Synchronization ..................................................................................... 35
3.8.2.3 Overhead Extraction ......................................................................................................................................................... 35
3.8.2.3.1 International Bit Extraction ............................................................................................................................. 35
3.8.2.3.2 Remote Alarm Indication Bit Extraction ......................................................................................................... 35
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table of Contents
ii
April 25, 2003
*Notice: The information in this document is subject to change without notice
3.8.2.3.3 National Bit Extraction ................................................................................................................................... 35
3.8.2.3.4 National Bit Codeword Extraction .................................................................................................................. 35
3.8.2.3.5 Extra Bit Extraction ........................................................................................................................................ 35
3.8.2.3.6 Remote Signaling Multi-Frame Alarm Indication Bit Extraction ..................................................................... 35
3.8.2.3.7 Sa6 Code Detection Per ETS 300 233 .......................................................................................................... 35
3.8.2.4 V5.2 Link .......................................................................................................................................................................... 36
3.8.2.5 Interrupt Summary ............................................................................................................................................................ 36
3.9 PERFORMANCE MONITOR ........................................................................................................................................................................ 38
3.9.1 T1/J1 Mode ...................................................................................................................................................................................... 38
3.9.2 E1 Mode .......................................................................................................................................................................................... 40
3.10 ALARM DETECTOR .................................................................................................................................................................................... 42
3.10.1 T1/J1 Mode ...................................................................................................................................................................................... 42
3.10.2 E1 Mode .......................................................................................................................................................................................... 44
3.11 HDLC RECEIVER ......................................................................................................................................................................................... 45
3.11.1 HDLC Channel Configuration ........................................................................................................................................................ 45
3.11.2 Two HDLC Modes ........................................................................................................................................................................... 45
3.11.2.1 HDLC Mode ...................................................................................................................................................................... 45
3.11.2.2 SS7 Mode ......................................................................................................................................................................... 47
3.12 BIT-ORIENTED MESSAGE RECEIVER (T1/J1 ONLY) .............................................................................................................................. 49
3.13 INBAND LOOPBACK CODE DETECTOR (T1/J1 ONLY) ........................................................................................................................... 49
3.14 ELASTIC STORE BUFFER .......................................................................................................................................................................... 50
3.15 RECEIVE CAS/RBS BUFFER ..................................................................................................................................................................... 50
3.15.1 T1/J1 Mode ...................................................................................................................................................................................... 50
3.15.2 E1 Mode .......................................................................................................................................................................................... 51
3.16 RECEIVE PAYLOAD CONTROL ................................................................................................................................................................. 53
3.17 RECEIVE SYSTEM INTERFACE ................................................................................................................................................................. 55
3.17.1 T1/J1 Mode ...................................................................................................................................................................................... 55
3.17.1.1 Receive Clock Master Mode ............................................................................................................................................ 55
3.17.1.1.1 Receive Clock Master Full T1/J1 Mode ......................................................................................................... 55
3.17.1.1.2 Receive Clock Master Fractional T1/J1 Mode ............................................................................................... 56
3.17.1.2 Receive Clock Slave Mode .............................................................................................................................................. 56
3.17.1.3 Receive Multiplexed Mode ............................................................................................................................................... 57
3.17.1.4 Offset ................................................................................................................................................................................ 57
3.17.1.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/MRSIGA(MRSIGB) .................................................................................. 59
3.17.2 E1 Mode .......................................................................................................................................................................................... 60
3.17.2.1 Receive Clock Master Mode ............................................................................................................................................ 60
3.17.2.1.1 Receive Clock Master Full E1 Mode ............................................................................................................. 60
3.17.2.1.2 Receive Clock Master Fractional E1 Mode ................................................................................................... 60
3.17.2.2 Receive Clock Slave Mode .............................................................................................................................................. 60
3.17.2.3 Receive Multiplexed Mode ............................................................................................................................................... 61
3.17.2.4 Offset ................................................................................................................................................................................ 61
3.17.2.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/MRSIGA(MRSIGB) .................................................................................. 61
3.18 TRANSMIT SYSTEM INTERFACE .............................................................................................................................................................. 62
3.18.1 T1/J1 Mode ...................................................................................................................................................................................... 62
3.18.1.1 Transmit Clock Master Mode ............................................................................................................................................ 62
3.18.1.1.1 Transmit Clock Master Full T1/J1 Mode ........................................................................................................ 63
3.18.1.1.2 Transmit Clock Master Fractional T1/J1 Mode .............................................................................................. 63
3.18.1.2 Transmit Clock Slave Mode ............................................................................................................................................. 63
3.18.1.3 Transmit Multiplexed Mode .............................................................................................................................................. 64
3.18.1.4 Offset ................................................................................................................................................................................ 65
3.18.2 E1 Mode .......................................................................................................................................................................................... 67
3.18.2.1 Transmit Clock Master Mode ............................................................................................................................................ 67
3.18.2.1.1 Transmit Clock Master Full E1 Mode ............................................................................................................ 67
3.18.2.1.2 Transmit Clock Master Fractional E1 Mode .................................................................................................. 67
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table of Contents
iii
April 25, 2003
*Notice: The information in this document is subject to change without notice
3.18.2.2 Transmit Clock Slave Mode ............................................................................................................................................. 67
3.18.2.3 Transmit Multiplexed Mode .............................................................................................................................................. 68
3.18.2.4 Offset ................................................................................................................................................................................ 68
3.19 TRANSMIT PAYLOAD CONTROL .............................................................................................................................................................. 69
3.20 FRAME GENERATOR ................................................................................................................................................................................. 70
3.20.1 Generation ...................................................................................................................................................................................... 70
3.20.1.1 T1 / J1 Mode .................................................................................................................................................................... 70
3.20.1.1.1 Super Frame (SF) Format ............................................................................................................................. 70
3.20.1.1.2 Extended Super Frame (ESF) Format ........................................................................................................... 70
3.20.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 70
3.20.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 70
3.20.1.1.5 Interrupt Summary ......................................................................................................................................... 71
3.20.1.2 E1 Mode ........................................................................................................................................................................... 72
3.20.1.2.1 Interrupt Summary ......................................................................................................................................... 73
3.20.2 HDLC Transmitter .......................................................................................................................................................................... 75
3.20.2.1 HDLC Channel Configuration ........................................................................................................................................... 75
3.20.2.2 Two HDLC Modes ............................................................................................................................................................ 75
3.20.2.2.1 HDLC Mode ................................................................................................................................................... 75
3.20.2.2.2 SS7 Mode ...................................................................................................................................................... 75
3.20.2.3 Interrupt Summary ............................................................................................................................................................ 76
3.20.2.4 Reset ................................................................................................................................................................................ 76
3.20.3 Automatic Performance Report Message (T1/J1 Only) .............................................................................................................. 77
3.20.4 Bit-Oriented Message Transmitter (T1/J1 Only) .......................................................................................................................... 78
3.20.5 Inband Loopback Code Generator (T1/J1 Only) .......................................................................................................................... 78
3.20.6 All `Zero's & All `One's ................................................................................................................................................................... 78
3.20.7 Change Of Frame Alignment ......................................................................................................................................................... 78
3.21 TRANSMIT BUFFER .................................................................................................................................................................................... 79
3.22 ENCODER .................................................................................................................................................................................................... 79
3.22.1 Line Code Rule ............................................................................................................................................................................... 79
3.22.1.1 T1/J1 Mode ...................................................................................................................................................................... 79
3.22.1.2 E1 Mode ........................................................................................................................................................................... 79
3.22.2 BPV Error Insertion ........................................................................................................................................................................ 79
3.22.3 All `One's Insertion ........................................................................................................................................................................ 79
3.23 TRANSMIT JITTER ATTENUATOR ............................................................................................................................................................ 80
3.24 WAVEFORM SHAPER / LINE BUILD OUT ................................................................................................................................................. 81
3.24.1 Preset Waveform Template ........................................................................................................................................................... 81
3.24.1.1 T1/J1 Mode ...................................................................................................................................................................... 81
3.24.1.2 E1 Mode ........................................................................................................................................................................... 81
3.24.2 Line Build Out (LBO) (T1 Only) ..................................................................................................................................................... 82
3.24.3 User-Programmable Arbitrary Waveform .................................................................................................................................... 82
3.25 LINE DRIVER ............................................................................................................................................................................................... 89
3.26 TRANSMITTER IMPEDANCE MATCHING ................................................................................................................................................. 90
3.27 TESTING AND DIAGNOSTIC FACILITIES ................................................................................................................................................. 91
3.27.1 PRBS Generator / Detector ........................................................................................................................................................... 91
3.27.1.1 Pattern Generator ............................................................................................................................................................. 91
3.27.1.2 Pattern Detector ............................................................................................................................................................... 91
3.27.2 Loopback ........................................................................................................................................................................................ 92
3.27.2.1 System Loopback ............................................................................................................................................................. 92
3.27.2.1.1 System Remote Loopback ............................................................................................................................ 92
3.27.2.1.2 System Local Loopback ................................................................................................................................ 92
3.27.2.2 Payload Loopback ............................................................................................................................................................ 92
3.27.2.3 Local Digital Loopback 1 .................................................................................................................................................. 92
3.27.2.4 Remote Loopback ............................................................................................................................................................ 92
3.27.2.5 Local Digital Loopback 2 .................................................................................................................................................. 92
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table of Contents
iv
April 25, 2003
*Notice: The information in this document is subject to change without notice
3.27.2.6 Analog Loopback .............................................................................................................................................................. 92
3.27.3 G.772 Non-Intrusive Monitoring .................................................................................................................................................... 92
3.28 INTERRUPT SUMMARY .............................................................................................................................................................................. 95
4 OPERATION .................................................................................................................................................................... 96
4.1 POWER-ON SEQUENCE ............................................................................................................................................................................. 96
4.2 RESET .......................................................................................................................................................................................................... 96
4.3 RECEIVE / TRANSMIT PATH POWER DOWN ........................................................................................................................................... 96
4.4 MICROPROCESSOR INTERFACE ............................................................................................................................................................. 97
4.4.1 SPI Mode ......................................................................................................................................................................................... 97
4.4.2 Parallel Microprocessor Interface ................................................................................................................................................ 98
4.5 INDIRECT REGISTER ACCESS SCHEME ................................................................................................................................................. 99
4.5.1 Indirect Register Read Access ..................................................................................................................................................... 99
4.5.2 Indirect Register Write Access ..................................................................................................................................................... 99
5 PROGRAMMING INFORMATION ................................................................................................................................. 100
5.1 REGISTER MAP ......................................................................................................................................................................................... 100
5.1.1 T1/J1 Mode .................................................................................................................................................................................... 100
5.1.1.1 Direct Register ................................................................................................................................................................ 100
5.1.1.2 Indirect Register ............................................................................................................................................................. 105
5.1.2 E1 Mode ........................................................................................................................................................................................ 106
5.1.2.1 Direct Register ................................................................................................................................................................ 106
5.1.2.2 Indirect Register ............................................................................................................................................................. 111
5.2 REGISTER DESCRIPTION ........................................................................................................................................................................ 113
5.2.1 T1/J1 Mode .................................................................................................................................................................................... 114
5.2.1.1 Direct Register ................................................................................................................................................................ 114
5.2.1.2 Indirect Register ............................................................................................................................................................. 216
5.2.2 E1 Mode ........................................................................................................................................................................................ 229
5.2.2.1 Direct Register ................................................................................................................................................................ 229
5.2.2.2 Indirect Register ............................................................................................................................................................. 332
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................................................... 347
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) .................................................................................................................. 348
6.2 JTAG DATA REGISTER ............................................................................................................................................................................ 349
6.2.1 Device Identification Register (IDR) ........................................................................................................................................... 349
6.2.2 Bypass Register (BYP) ................................................................................................................................................................ 349
6.2.3 Boundary Scan Register (BSR) ................................................................................................................................................... 349
6.3 TEST ACCESS PORT CONTROLLER ...................................................................................................................................................... 352
7 PHYSICAL AND ELECTRICAL SPECIFICATIONS ..................................................................................................... 355
7.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................ 355
7.2 RECOMMENDED OPERATING CONDITIONS ......................................................................................................................................... 355
7.3 D.C. CHARACTERISTICS ......................................................................................................................................................................... 356
7.4 DIGITAL I/O TIMING CHARACTERISTICS ............................................................................................................................................... 357
7.5 CLOCK FREQUENCY REQUIREMENT .................................................................................................................................................... 357
7.6 T1/J1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ................................................................................................................... 358
7.7 E1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ........................................................................................................................ 359
7.8 T1/J1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................................................................ 360
7.9 E1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................................................ 361
7.10 JITTER TOLERANCE ................................................................................................................................................................................ 362
7.10.1 T1/J1 Mode .................................................................................................................................................................................... 362
7.10.2 E1 Mode ........................................................................................................................................................................................ 363
7.11 JITTER TRANSFER ................................................................................................................................................................................... 364
7.11.1 T1/J1 Mode .................................................................................................................................................................................... 364
7.11.2 E1 Mode ........................................................................................................................................................................................ 365
7.12 MICROPROCESSOR TIMING SPECIFICATION ....................................................................................................................................... 366
7.12.1 Motorola Non-Multiplexed Mode ................................................................................................................................................. 366
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table of Contents
v
April 25, 2003
*Notice: The information in this document is subject to change without notice
7.12.1.1 Read Cycle Specification ............................................................................................................................................... 366
7.12.1.2 Write Cycle Specification ................................................................................................................................................ 367
7.12.2 Intel Non-Multiplexed Mode ......................................................................................................................................................... 368
7.12.2.1 Read Cycle Specification ............................................................................................................................................... 368
7.12.2.2 Write Cycle Specification ................................................................................................................................................ 369
7.12.3 SPI Mode ....................................................................................................................................................................................... 370
ORDERING INFORMATION ......................................................................................................................................... 371
List of Tables
vi
April 25, 2003
List of Tables
*Notice: The information in this document is subject to change without notice
Table 1: Operating Mode Selection ........................................................................................................................................................................... 14
Table 2: Related Bit / Register In Chapter 3.1 ........................................................................................................................................................... 14
Table 3: Impedance Matching Value For The Receiver ............................................................................................................................................. 15
Table 4: Related Bit / Register In Chapter 3.2 ........................................................................................................................................................... 16
Table 5: Related Bit / Register In Chapter 3.3 & Chapter 3.4 .................................................................................................................................... 17
Table 6: Criteria Of Speed Adjustment Start .............................................................................................................................................................. 18
Table 7: Related Bit / Register In Chapter 3.6 ........................................................................................................................................................... 18
Table 8: Excessive Zero Error Definition ................................................................................................................................................................... 19
Table 9: LOS Condition In T1/J1 Mode ...................................................................................................................................................................... 21
Table 10: LOS Condition In E1 Mode .......................................................................................................................................................................... 21
Table 11: Related Bit / Register In Chapter 3.7 ........................................................................................................................................................... 22
Table 12: The Structure of SF ..................................................................................................................................................................................... 23
Table 13: The Structure of ESF ................................................................................................................................................................................... 24
Table 14: The Structure of T1 DM ............................................................................................................................................................................... 25
Table 15: The Structure of SLC-96 .............................................................................................................................................................................. 26
Table 16: Interrupt Source In T1/J1 Frame Processor ................................................................................................................................................ 28
Table 17: Related Bit / Register In Chapter 3.8.1 ........................................................................................................................................................ 29
Table 18: The Structure Of TS0 In CRC Multi-Frame .................................................................................................................................................. 33
Table 19: FAS/NFAS Bit/Pattern Error Criteria ............................................................................................................................................................ 34
Table 20: Interrupt Source In E1 Frame Processor ..................................................................................................................................................... 36
Table 21: Related Bit / Register In Chapter 3.8.2 ........................................................................................................................................................ 37
Table 22: Monitored Events In T1/J1 Mode ................................................................................................................................................................. 38
Table 23: Related Bit / Register In Chapter 3.9.1 ........................................................................................................................................................ 39
Table 24: Monitored Events In E1 Mode ..................................................................................................................................................................... 40
Table 25: Related Bit / Register In Chapter 3.9.2 ........................................................................................................................................................ 41
Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria ......................................................................................................................................... 42
Table 27: Related Bit / Register In Chapter 3.10.1 ...................................................................................................................................................... 43
Table 28: Related Bit / Register In Chapter 3.10.2 ...................................................................................................................................................... 44
Table 29: Related Bit / Register In Chapter 3.11.1 ...................................................................................................................................................... 45
Table 30: Interrupt Summarize In HDLC Mode ........................................................................................................................................................... 46
Table 31: Related Bit / Register In Chapter 3.11.2 ...................................................................................................................................................... 48
Table 32: Related Bit / Register In Chapter 3.12 ......................................................................................................................................................... 49
Table 33: Related Bit / Register In Chapter 3.13 ......................................................................................................................................................... 49
Table 34: Related Bit / Register In Chapter 3.14 ......................................................................................................................................................... 50
Table 35: Related Bit / Register In Chapter 3.15 ......................................................................................................................................................... 52
Table 36: A-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 53
Table 37: -Law Digital Milliwatt Pattern ..................................................................................................................................................................... 53
Table 38: Related Bit / Register In Chapter 3.16 ......................................................................................................................................................... 54
Table 39: Operating Modes Selection In T1/J1 Receive Path ..................................................................................................................................... 55
Table 40: Operating Modes Selection In E1 Receive Path .......................................................................................................................................... 60
Table 41: Related Bit / Register In Chapter 3.17 ......................................................................................................................................................... 61
Table 42: Operating Modes Selection In T1/J1 Transmit Path .................................................................................................................................... 62
Table 43: Operating Modes Selection In E1 Transmit Path ......................................................................................................................................... 67
Table 44: Related Bit / Register In Chapter 3.18 ......................................................................................................................................................... 68
Table 45: Related Bit / Register In Chapter 3.19 ......................................................................................................................................................... 69
Table 46: Related Bit / Register In Chapter 3.20.1.1 ................................................................................................................................................... 71
Table 47: E1 Frame Generation .................................................................................................................................................................................. 72
Table 48: Control Over E Bits ...................................................................................................................................................................................... 72
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
List of Tables
vii
April 25, 2003
*Notice: The information in this document is subject to change without notice
Table 49: Interrupt Summary In E1 Mode .................................................................................................................................................................... 73
Table 50: Related Bit / Register In Chapter 3.20.1.2 ................................................................................................................................................... 74
Table 51: Related Bit / Register In Chapter 3.20.2.1 ................................................................................................................................................... 75
Table 52: Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4 .................................................................................................................... 76
Table 53: APRM Message Format .............................................................................................................................................................................. 77
Table 54: APRM Interpretation .................................................................................................................................................................................... 77
Table 55: Related Bit / Register In Chapter 3.20.3 ...................................................................................................................................................... 78
Table 56: Related Bit / Register In Chapter 3.20.4 & Chapter 3.20.5 .......................................................................................................................... 78
Table 57: Related Bit / Register In Chapter 3.20.6, Chapter 3.20.7 & Chapter 3.21 ................................................................................................... 79
Table 58: Related Bit / Register In Chapter 3.22 ......................................................................................................................................................... 79
Table 59: Related Bit / Register In Chapter 3.23 ......................................................................................................................................................... 80
Table 60: PULS[3:0] Setting In T1/J1 Mode ................................................................................................................................................................ 81
Table 61: LBO PULS[3:0] Setting In T1 Mode ............................................................................................................................................................. 82
Table 62: Transmit Waveform Value For E1 75
...................................................................................................................................................... 83
Table 63: Transmit Waveform Value For E1 120
.................................................................................................................................................... 83
Table 64: Transmit Waveform Value For T1 0~133 ft ................................................................................................................................................. 84
Table 65: Transmit Waveform Value For T1 133~266 ft ............................................................................................................................................. 84
Table 66: Transmit Waveform Value For T1 266~399 ft ............................................................................................................................................. 85
Table 67: Transmit Waveform Value For T1 399~533 ft ............................................................................................................................................. 85
Table 68: Transmit Waveform Value For T1 533~655 ft ............................................................................................................................................. 86
Table 69: Transmit Waveform Value For J1 0~655 ft .................................................................................................................................................. 86
Table 70: Transmit Waveform Value For DS1 0 dB LBO ............................................................................................................................................ 87
Table 71: Transmit Waveform Value For DS1 -7.5 dB LBO ........................................................................................................................................ 87
Table 72: Transmit Waveform Value For DS1 -15.0 dB LBO ...................................................................................................................................... 88
Table 73: Transmit Waveform Value For DS1 -22.5 dB LBO ...................................................................................................................................... 88
Table 74: Related Bit / Register In Chapter 3.24 ......................................................................................................................................................... 88
Table 75: Impedance Matching Value For The Transmitter ........................................................................................................................................ 90
Table 76: Related Bit / Register In Chapter 3.25 & Chapter 3.26 ................................................................................................................................ 90
Table 77: Related Bit / Register In Chapter 3.27.1 ...................................................................................................................................................... 91
Table 78: Related Bit / Register In Chapter 3.27.2 & Chapter 3.27.3 .......................................................................................................................... 94
Table 79: Related Bit / Register In Chapter 3.28 ......................................................................................................................................................... 95
Table 80: Parallel Microprocessor Interface ................................................................................................................................................................ 98
Table 81: Related Bit / Register In Chapter 4 .............................................................................................................................................................. 99
Table 82: IR Code ..................................................................................................................................................................................................... 348
Table 83: IDR ............................................................................................................................................................................................................ 349
Table 84: Boundary Scan (BS) Sequence ................................................................................................................................................................ 349
Table 85: TAP Controller State Description .............................................................................................................................................................. 352
List of Figures
viii
April 25, 2003
List of Figures
*Notice: The information in this document is subject to change without notice
Figure 1. 208-Pin PBGA (Top View) ............................................................................................................................................................................. 3
Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 15
Figure 3. Monitoring Receive Path .............................................................................................................................................................................. 16
Figure 4. Monitoring Transmit Path ............................................................................................................................................................................. 16
Figure 5. Jitter Attenuator ............................................................................................................................................................................................ 18
Figure 6. AMI Bipolar Violation Error ........................................................................................................................................................................... 20
Figure 7. B8ZS Excessive Zero Error ......................................................................................................................................................................... 20
Figure 8. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................. 20
Figure 9. E1 Frame Searching Process ...................................................................................................................................................................... 31
Figure 10. Basic Frame Searching Process ................................................................................................................................................................ 32
Figure 11. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 34
Figure 12. Standard HDLC Packet .............................................................................................................................................................................. 45
Figure 13. Overhead Indication In The FIFO ............................................................................................................................................................... 46
Figure 14. Standard SS7 Packet ................................................................................................................................................................................. 47
Figure 15. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 51
Figure 16. Signaling Output In E1 Mode ...................................................................................................................................................................... 51
Figure 17. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 56
Figure 18. T1/J1 To E1 Format Mapping - One Filler Every Four Channels Mode ..................................................................................................... 56
Figure 19. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 57
Figure 20. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 58
Figure 21. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 58
Figure 22. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 59
Figure 23. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 59
Figure 24. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 63
Figure 25. E1 To T1/J1 Format Mapping - One Filler Every Four Channels Mode ..................................................................................................... 63
Figure 26. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 64
Figure 27. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 65
Figure 28. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 65
Figure 29. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 66
Figure 30. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 66
Figure 31. DSX-1 Waveform Template ........................................................................................................................................................................ 81
Figure 32. T1/J1 Pulse Template Measurement Circuit .............................................................................................................................................. 81
Figure 33. E1 Waveform Template .............................................................................................................................................................................. 81
Figure 34. E1 Pulse Template Measurement Circuit ................................................................................................................................................... 81
Figure 35. G.772 Non-Intrusive Monitor ...................................................................................................................................................................... 93
Figure 36. Hardware Reset When Powered-Up .......................................................................................................................................................... 96
Figure 37. Hardware Reset In Normal Operation ........................................................................................................................................................ 96
Figure 38. Read Operation In SPI Mode ..................................................................................................................................................................... 97
Figure 39. Write Operation In SPI Mode ...................................................................................................................................................................... 97
Figure 40. JTAG Architecture .................................................................................................................................................................................... 347
Figure 41. JTAG State Diagram ................................................................................................................................................................................ 354
Figure 42. I/O Timing in Mode ................................................................................................................................................................................... 357
Figure 43. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 362
Figure 44. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 363
Figure 45. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 364
Figure 46. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 365
Figure 47. Motorola Non-Multiplexed Mode Read Cycle ........................................................................................................................................... 366
Figure 48. Motorola Non-Multiplexed Mode Write Cycle ........................................................................................................................................... 367
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
List of Figures
ix
April 25, 2003
*Notice: The information in this document is subject to change without notice
Figure 49. Intel Non-Multiplexed Mode Read Cycle .................................................................................................................................................. 368
Figure 50. Intel Non-Multiplexed Mode Write Cycle .................................................................................................................................................. 369
Figure 51. SPI Timing Diagram ................................................................................................................................................................................. 370
1
April 25, 2003
IDT82P2284
Advance Information*
2002 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
DSC-6226/-
Quad T1/E1/J1 Long Haul /
Short Haul Transceiver
Advance Information
The IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
FEATURES
LINE INTERFACE
Each link can be configured as T1, E1 or J1
Supports T1/E1/J1 long haul/short haul line interface
HPS for 1+1 protection without external relays
Receive sensitivity exceeds -36 dB @ 772 Hz and -43 dB @ 1024
Hz
Selectable internal line termination impedance: 100
(for T1), 75
/ 120 (for E1) and 110 (for J1)
Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) line encod-
ing/decoding
Provides T1/E1/J1 short haul pulse templates, long haul LBO (per
ANSI T1.403 and FCC68: 0 dB, -7.5 dB, -15 dB, -22 dB) and user-
programmable arbitrary pulse template
Supports G.772 non-intrusive monitoring
Supports T1.102 line monitor
Transmit line short-circuit detection and protection
Separate Transmit and Receive Jitter Attenuators (2 per link)
Indicates the interval between the write pointer and the read pointer
of the FIFO in JA
Loss of signal indication with programmable thresholds according
to ITUT-T G.775, ETS 300 233 (E1) and ANSI T1.403 (T1/J1)
Supports Analog Loopback, Digital Loopback and Remote Loop-
back
Each receiver and transmitter can be individually powered down
FRAMER
Each link can be configured as T1, E1 or J1
Frame alignment/generation for T1 (per ITU-T G.704, TA-TSY-
000278, TR-TSY-000008), E1 (per ITU-T G.704), J1 (per JT G.704)
and un-framed mode
Supports T1/J1 Super Frame and Extended Super Frame, T1 Digi-
tal Multiplexer and Switch Line Carrier - 96, E1 CRC Multi-frame
and Signaling Multi-frame
Signaling extraction/insertion for CAS and RBS signaling
Provides programmable system interface supporting Mitel
TM
ST-
bus, AT&T
TM
CHI and MVIP bus, 8.192 Mb/s multiplexed bus and
1.544 Mb/s or 2.048 Mb/s non-multiplexed bus
Three HDLC controllers per link with separate 128-byte transmit
and receive FIFOs per controller
Supports Signaling System #7 (SS7)
Programmable bit insertion and bit inversion on per channel/
timeslot basis
Provides Bit Oriented Message (BOM) generation and detection
Provides Automatic Performance Report Message (APRM) genera-
tion
Detects and generates alarms (AIS, RAI)
Provides performance monitor to count Bipolar Violation error,
Excess Zero error, CRC error, framing bit error, far end CRC error,
out of frame and change of framing alignment position
Supports System Loopback, Payload Loopback, Digital Loopback
and Inband Loopback
Detects and generates selectable PRBS and QRSS
CONTROL INTERFACE
Supports Serial Peripheral Interface (SPI) microprocessor and par-
allel Intel/Motorola non-multiplexed microprocessor interface
Global hardware and software reset
Two general purpose I/O pins
Per link power down
GENERAL
Flexible reference clock (N x 1.544 MHz or N x 2.048 MHz)
(0<N<5)
JTAG boundary scan
3.3 V I/O with 5 V tolerant inputs
Low power consumption (Typical 450 mW)
3.3 V and 1.8 V power supply
208-pin PBGA package
APPLICATIONS
C.O, PABX, ISDN PRI
Wireless Base Stations
T1/E1/J1 ATM Gateways, Multiplexer
T1/E1/J1 Access Networks
LAN/WAN Router
Digital Cross Connect
SONET/SDH Add/Drop Equipment
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Block Diagram
2
April 25, 2003
*Notice: The information in this document is subject to change without notice
Advance Information
BLOCK DIAGRAM
Re
ce
i
v
e
Sys
t
em
In
te
r
f
a
c
e
RSF
S
n
RSIGn
RSD
n
MR
SCK
MRSFS
MRSIGA[1]/
MRSIG
B
[1]
MRSD
A[
1
]
/
MRSD
B[
1
]
Re
cei
v
e
Pay
l
oa
d
C
ontr
o
l
F
r
ame
Proce
sso
r
B8ZS/
HD
B3/
AMI
Dec
o
d
e
r
Re
ceive
Ji
tt
e
r
At
tenu
ator
Wavef
o
r
m
S
h
ap
er
/

Li
ne
B
u
ild
O
u
t
Data
S
lic
e
r
CL
K&Da
t
a
R
e
co
ver
y
(
D
PLL)
RT
I
P
n
RR
I
N
Gn
Tr
an
smi
t
System
In
te
r
f
a
c
e
TSI
G
n
MTSFS
TS
D
n
MTSC
K
MTSDA[
1
]
/
MTSDB[
1
]
MTSI
GA[
1
]/
MTSI
GB[
1
]
Tr
an
s
m
i
t
Pa
yl
o
a
d
Con
t
rol
F
r
am
e Ge
ne
r
a
t
o
r
Tr
an
s
m
i
t
Buff
e
r
B8
Z
S
/
HD
B3/AM
I
En
co
de
r
Tr
an
smi
t
Ji
tt
e
r
At
t
e
nu
ator
Li
n
e
Dri
v
er
TT
I
P
n
TR
I
N
G
n
O
n
e of

t
h
e Fo
ur
Li
n
k
s
(LP
1,
2
)
(L
P
4
)
G.772
Mon
i
t
o
r
C
o
n
t
ro
l In
te
rf
a
c
e
I
EEE1
14
9.1
JTAG
TCK
TMS
TDI
TDO
TRST
VDDD
I
O
/

VDDD
C /
VDD
A
R / VDD
A
T

/
VDD
AX
/
VDDAP /
VDDAB
GN
DA / GNDD
DS/RD/SCLK
CS
INT
A[9:0]
D[7:1]
No
te:
LP1
,
2 -

S
yst
e
m

Lo
op
ba
ck
LP3
- Pa
yl
o
a
d
Lo
op
ba
ck
LP4
- L
o
ca
l
D
i
gi
tal

Lo
op
bac
k 1
LP5
- R
e
mote
Lo
opb
ac
k
LP6
- L
o
ca
l
D
i
gi
tal

Lo
op
bac
k 2
LP7
- An
al
o
g

Lo
op
ba
ck
RSCKn
El
a
s
t
i
c
Stor
e
Bu
f
f
er
Re
ceive
CAS/
RBS
Buff
er
Al
a
r
m
De
t
e
ct
o
r
HD
LC
Re
cei
v
er
#1
,
#
2
, #3
Bi
t
-
Or
i
e
nted
Me
ssa
ge
Rec
e
i
v
e
r
I
n
ba
nd
Lo
op
ba
c
k
C
o
d
e
De
t
e
c
t
o
r
P
e
r
f
or
m
a
n
c
e M
o
ni
t
o
r
Ada
p
ti
ve
E
q
u
a
liz
e
r
Re
c
e
i
v
e
In
t
e
r
n
a
l
Te
rm
inati
o
n
TSFSn
TSC
K
n
Bi
t
-
Or
i
e
nted
Me
ssa
ge
Tr
an
smi
t
t
e
r
HD
LC
Tran
s
m
it
ter
#1
,
#
2
, #3
I
n
ba
nd
Lo
op
ba
c
k
C
ode
Gener
a
t
o
r
A
u
to
m
a
ti
c
Per
f
o
r
m
a
nc
e
Rep
o
rt
Mess
age
Tr
an
s
m
i
t
Interna
l
Te
r
m
in
a
t
io
n
PRBS
G
e
n
e
rator /
Detector
REFR
MPM
SPIEN
Cl
oc
k Gen
e
rator
REFA_OUT
REFB_OUT
OSCI
OSCO
CLK_SEL[2:0]
THZ
(L
P
3
)
(L
P
5
)
(LP
6)
(LP
7)
RW/WR/SDI
RESET
GPIO[1:0]
CLK_GEN_1.544
CLK_GEN_2.048
D[0]/SDO
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Assignment
3
April 25, 2003
Advance Information
1
PIN ASSIGNMENT
Figure 1. 208-Pin PBGA (Top View)
TTIP4
TRING4
VDDAT4
VDDAR4
VDDAR3
TRING3
TTIP3
TTIP2
TRING2
VDDAR1
TRING1
TTIP1
VDDAP
RESET
REFA_
OUT
CLK_GE
N_1.544
NC
VDDAX4
GNDA
RTIP4
VDDAT3
GNDA
VDDAX3
VDDAX2
VDDAT2
GNDA
GNDA
VDDAT1
OSCI
REFB_
OUT
CLK_SEL
2
THZ
NC
NC
GNDA
RRING4
GNDA
GNDA
GNDA
GNDA
VDDAR2
GNDA
RTIP1
VDDAX1
OSCO
CLK_SEL
1
IC
REFR
NC
NC
GNDA
GNDA
RRING3
RTIP3
GNDA
RTIP2
RRING2
GNDA
RRING1
VDDAB
GPIO1
CLK_GE
N_2.048
CLK_SEL
0
IC
TSIG2/
MTSIGB1
NC
NC
NC
GPIO0
VDDDIO
VDDDIO
NC
TSIG1/
MTSIGA1
TSD2/
MTSDB1
TSD4
TSIG4
GNDD
NC
GNDD
NC
TSFS4
TSD1/
MTSDA1
TSD3
TSIG3
GNDD
GNDD
GNDD
GNDD
GNDD
NC
GNDD
VDDDIO
TSFS3
TSCK4
NC
NC
VDDDC
VDDDC
GNDD
GNDD
NC
VDDDIO
VDDDIO
NC
TSCK3
TSFS2
NC
NC
VDDDC
VDDDC
VDDDC
VDDDC
NC
GNDD
VDDDIO
NC
TSCK2
TSFS1/
MTSFS
NC
NC
VDDDC
VDDDC
VDDDC
VDDDC
GNDD
GNDD
VDDDIO
NC
TSCK1/
MTSCK
NC
NC
NC
NC
GNDD
GNDD
NC
NC
NC
NC
NC
NC
GNDD
VDDDIO
VDDDIO
NC
NC
RSIG4
RSFS3
RSFS1/
MRSFS
A2
A6
NC
D1
CS
IC
TRST
GNDD
NC
NC
VDDDIO
RSD4
RSIG2/
MRSIGB1
RSD1/
MRSDA1
RSCK3
RSCK1/
MRSCK
A3
A7
D7
D2
MPM
RW/WR
/SDI
IC
GNDD
GNDD
GNDD
VDDDIO
RSIG3
RSD2/
MRSDB1
RSFS4
RSFS2
A0
A4
A8
D6
D3
DS/RD
/SCLK
SPIEN
NC
TDI
TMS
VDDDIO
NC
RSD3
RSIG1/
MRSIGA1
RSCK4
RSCK2
A1
A5
A9
D5
D4
D0/SDO
INT
IC
TDO
TCK
NC
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Description
4
April 25, 2003
Advance Information
2
PIN DESCRIPTION
Name
Type
Pin No.
Description
Line and System Interface
RTIP[1]
RTIP[2]
RTIP[3]
RTIP[4]
RRING[1]
RRING[2]
RRING[3]
RRING[4]
Input
C11
D8
D6
B4
D11
D9
D5
C4
RTIP[1:4] / RRING[1:4]: Receive Bipolar Tip/Ring for Link 1 ~ 4
These pins are the differential line receiver inputs.
TTIP[1]
TTIP[2]
TTIP[3]
TTIP[4]
TRING[1]
TRING[2]
TRING[3]
TRING[4]
Output
A12
A8
A7
A1
A11
A9
A6
A2
TTIP[1:4] / TRING[1:4]: Transmit Bipolar Tip/Ring for Link 1 ~ 4
These pins are the differential line driver outputs and can be set to high impedance state globally or individu-
ally. A logic high on the THZ pin sets all these pins to high impedance state. When the T_HZ bit (b4, T1/J1-
023H,... / b4, E1-023H,...) * is set to `1', the TTIPn/TRINGn pins in the corresponding link are set to high
impedance state.
Besides, TTIPn/TRINGn will also be set to high impedance state by other ways (refer to Chapter 3.25 Line
Driver for details).
RSD[1] / MRSDA[1]
RSD[2] / MRSDB[1]
RSD[3]
RSD[4]
Tri-state
Output
P3
R2
T1
P1
RSD[1:4]: Receive Side System Data for Link 1 ~ 4
The processed data stream is output on these pins.
In Receive Clock Master mode, the RSDn pins are updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSDn pins
are updated on the active edge of the corresponding RSCKn or all four RSDn pins are updated on the active
edge of RSCK[1].
MRSDA[1] / MRSDB[1]: Multiplexed Receive Side System Data A / B for Link 1 ~ 4
In Receive Multiplexed mode, the MRSDA[1] pin or the MRSDB[1] pin is used to output the processed data
stream. Using a byte-interleaved multiplexing scheme, the MRSDA[1]/MRSDB[1] pins output the data from
Link 1 to Link 4. The data on the MRSDA[1]/MRSDB[1] pin is updated on the active edge of the MRSCK. The
data on MRSDA[1] is the same as the data on MRSDB[1]. MRSDB[1] is for back-up purpose.
RSIG[1] / MRSIGA[1]
RSIG[2] / MRSIGB[1]
RSIG[3]
RSIG[4]
Tri-state
Output
T2
P2
R1
N3
RSIG[1:4]: Receive Side System Signaling for Link 1 ~ 4
The extracted signaling bits are output on these pins. They are located in the lower nibble (b5 ~ b8) and are
channel/timeslot-aligned with the data output on the corresponding RSDn pin.
In Receive Clock Master mode, the RSIGn pins are updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSIGn pins
are updated on the active edge of the corresponding RSCKn or all four RSIGn are updated on the active edge
of RSCK[1].
MRSIGA[1] / MRSIGB[1]: Multiplexed Receive Side System Signaling A / B for Link 1 ~ 4
In Receive Multiplexed mode, the MRSIGA[1] pin or the MRSIGB[1] pin is used to output the extracted signal-
ing bits. The signaling bits are located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the
data output on the corresponding MRSDA[1]/MRSDB[1] pins. Using the byte-interleaved multiplexing
scheme, the MRSIGA[1]/MRSIGB[1] pins output the signaling bits from Link 1 to Link 4. The signaling bits on
the MRSIGA[1]/MRSIGB[1] pin is updated on the active edge of the MRSCK. The signaling bits on
MRSIGA[1] is the same as the signaling bits on MRSIGB[1]. MRSIGB[1] is for back-up purpose.
Note:
*
The contents in the brackets indicate the position of the preceding bit and the address of the register. After the address, if the punctuation `,...' is followed, this bit is in a per-link control reg-
ister and the listed address belongs to Link 1. Users can find the omitted addresses in Chapter 5. If there is no punctuation followed the address, this bit is in a global control register.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Description
5
April 25, 2003
Advance Information
RSFS[1] / MRSFS
RSFS[2]
RSFS[3]
RSFS[4]
Output / Input
N5
R4
N4
R3
RSFS[1:4]: Receive Side System Frame Pulse for Link 1 ~ 4
In T1/J1 Receive Clock Master mode, RSFSn outputs the pulse to indicate each F-bit, every second F-bit in
SF frame, the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame or the first F-bit of every second SF
multi-frame.
In T1/J1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125
s to indicate
the start of a frame.
In E1 Receive Clock Master mode, RSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame,
Signaling Multi-frame, or both the CRC Multi-frame and Signaling Multi-frame, or the TS1 and TS16 over-
head.
In E1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125
s to indicate
the start of a frame.
RSFSn is updated/sampled on the active edge of the corresponding RSCKn. The active polarity of RSFSn is
selected by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).
MRSFS: Multiplexed Receive Side System Signaling for Link 1 ~ 4
In Receive Multiplexed mode, MRSFS inputs the pulse at a rate of integer multiple of 125
s to indicate the
start of a frame on the multiplexed data bus. MRSFS is sampled on the active edge of MRSCK. The active
polarity of MRSFS is selected by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).
RSFS[1:4]/MRSFS are Schmitt-triggered inputs/outputs with pull-up resistors.
RSCK[1] / MRSCK
RSCK[2]
RSCK[3]
RSCK[4]
Output / Input
P5
T4
P4
T3
RSCK[1:4]: Receive Side System Clock for Link 1 ~ 4
In Receive Clock Master mode, the RSCKn pins output a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz
(for E1 mode) clock used to update the signal on the corresponding RSDn, RSIGn and RSFSn pins.
In Receive Clock Slave mode, the RSCKn pins input a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096
MHz clock used to update the signals on the corresponding RSDn and RSIGn pins and sample the signals on
the corresponding RSFSn pins. Selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSCK[1]
pin can be used for all four links.
MRSCK: Multiplexed Receive Side System Clock for Link 1 ~ 4
In Receive Multiplexed mode, MRSCK inputs a 8.192 MHz or 16.384 MHz clock used to update the signals on
the corresponding MRSDA/MRSDB and MRSIGA/MRSIGB pins and sample the signal on the corresponding
MRSFS pin.
RSCK[1:4]/MRSCK are Schmitt-triggered inputs/outputs with pull-up resistors.
TSD[1] / MTSDA[1]
TSD[2] / MTSDB[1]
TSD[3]
TSD[4]
Input
G2
F2
G3
F3
TSD[1:4]: Transmit Side System Data for Link 1 ~ 4
The data stream from the system side is input on these pins.
In Transmit Clock Master mode, the TSDn pins are sampled on the active edge of the corresponding TSCKn.
In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), the TSDn pins
are sampled on the active edge of the corresponding TSCKn or all four TSDn pins are sampled on the active
edge of TSCK[1].
MTSDA[1] / MTSDB[1]: Multiplexed Transmit Side System Data A / B for Link 1 ~ 4
In Transmit Multiplexed mode, selected by the MTSDA bit (b2, T1/J1-010H / b2, E1-010H), the MTSDA[1] pin
or the MTSDB[1] pin is used to input the data stream. Using a byte-interleaved multiplexing scheme, the
MTSDA[1]/MTSDB[1] pins input the data for Link 1 to Link 4. The data on the MTSDA[1]/MTSDB[1] pins are
sampled on the active edge of MTSCK.
TSD[1:4]/MTSDA[1]/MTSDB[1] are Schmitt-triggered inputs.
Name
Type
Pin No.
Description
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Description
6
April 25, 2003
Advance Information
TSIG[1] / MTSIGA[1]
TSIG[2] / MTSIGB[1]
TSIG[3]
TSIG[4]
Input
F1
E1
G4
F4
TSIG[1:4]: Transmit Side System Signaling for Link 1 ~ 4
The signaling bits are input on these pins. They are located in the lower nibble (b5 ~ b8) and are channel/
timeslot-aligned with the data input on the corresponding TSDn pin.
In Transmit Clock Master mode, TSIGn is sampled on the active edge of the corresponding TSCKn.
In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), TSIGn is sam-
pled on the active edge of the corresponding TSCKn or all four TSIGn are updated on the active edge of
TSCK[1].
MTSIGA[1] / MTSIGB[1]: Multiplexed Transmit Side System Signaling A / B for Link 1 ~ 4
In Transmit Multiplexed mode, selected by the MTSDA bit (b2, T1/J1-010H / b2, E1-010H), the MTSIGA[1] pin
or the MTSIGB[1] pin is used to input the signaling bits. The signaling bits are located in the lower nibble (b5
~ b8) and are channel/timeslot-aligned with the data input on the corresponding MTSDA[1]/MTSDB[1] pin.
Using the byte-interleaved multiplexing scheme, the MTSIGA[1]/MTSIGB[1] pins input the signaling bits for
Link 1 to Link 4. The signaling bits on the MTSIGA[1]/MTSIGB[1] pin is sampled on the active edge of
MTSCK.
TSIG[1:4]/MTSIGA[1]/MTSIGB[1] are Schmitt-triggered inputs.
TSFS[1] / MTSFS
TSFS[2]
TSFS[3]
TSFS[4]
Output / Input
K2
J2
H1
G1
TSFS[1:4]: Transmit Side System Frame Pulse for Link 1 ~ 4
In T1/J1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate each F-bit or the first F-bit of every
SF/ESF/T1 DM/SLC-96 multi-frame.
In T1/J1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate each F-bit or the first F-bit of every
SF/ESF/T1 DM/SLC-96 multi-frame.
In E1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame
and/or Signaling Multi-frame.
In E1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate the Basic frame, CRC Multi-frame and/
or Signaling Multi-frame.
TSFSn is updated/sampled on the active edge of the corresponding TSCKn. The active polarity of TSFSn is
selected by the FSINV bit (b1, T1/J1-042H,... / b1, E1-042H,...).
MTSFS: Multiplexed Transmit Side System Signaling for Link 1 ~ 4
In T1/J1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each F-bit or the first F-bit of every
SF/ESF/T1 DM/SLC-96 multi-frame of one link on the multiplexed data bus.
In E1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each Basic frame, CRC Multi-frame
and/or Signaling Multi-frame of one link on the multiplexed data bus.
MTSFS is sampled on the active edge of MTSCK. The active polarity of MTSFS is selected by the FSINV bit
(b1, T1/J1-042H,... / b1, E1-042H,...).
TSFS[1:4]/MTSFS are Schmitt-triggered inputs/outputs with pull-up resistors.
TSCK[1] / MTSCK
TSCK[2]
TSCK[3]
TSCK[4]
Output / Input
L1
K1
J1
H2
TSCK[1:4]: Transmit Side System Clock for Link 1 ~ 4
In Transmit Clock Master mode, TSCKn outputs a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1
mode) clock used to sample the signal on the corresponding TSDn and TSIGn pins and update the signal on
the corresponding TSFSn pin.
In Transmit Clock Slave mode, TSCKn inputs a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz
clock used to sample the signal on the corresponding TSDn, TSIGn and TSFSn pins. Selected by the
TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), the TSCK[1] can be used for all four links.
MTSCK: Multiplexed Transmit Side System Clock for Link 1 ~ 4
In Transmit Multiplexed mode, MTSCK inputs a 8.192 MHz or 16.384 MHz clock used to sample the signal on
the corresponding MTSDA/MTSDB, MTSIGA/MTSIGB and MTSFS pins.
TSCK[1:4]/MTSCK are Schmitt-triggered inputs/outputs with pull-up resistors.
Clock Generator
Name
Type
Pin No.
Description
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Description
7
April 25, 2003
Advance Information
OSCI
Input
B13
OSCI: Crystal Oscillator Input
This pin is connected to an external clock source.
The clock frequency of OSCI is defined by CLK_SEL[2:0]. The clock accuracy should be 32 ppm and duty
cycle should be from 40% to 60%.
OSCO
Output
C13
OSCO: Crystal Oscillator Output
This pin outputs the inverted, buffered clock input from OSCI.
CLK_SEL[0]
CLK_SEL[1]
CLK_SEL[2]
Input
D15
C14
B15
CLK_SEL[2:0]: Clock Selection
These three pins select the input clock signal:
When the CLK_SEL[2] pin is low, the input clock signal is N X 1.544 MHz;
when the CLK_SEL[2] pin is high, the input clock signal is N X 2.048 MHz.
When the CLK_SEL[1:0] pins are `00', the N is 1;
when the CLK_SEL[1:0] pins are `01', the N is 2;
when the CLK_SEL[1:0] pins are `10', the N is 3;
when the CLK_SEL[1:0] pins are `11', the N is 4.
CLK_SEL[2:0] are Schmitt-trigger inputs.
CLK_GEN_1.544
Output
A16
CLK_GEN_1.544: Clock Generator 1.544 MHz Output
This pin outputs the 1.544 MHz clock signal generated by the Clock Generator.
CLK_GEN_2.048
Output
D14
CLK_GEN_2.048: Clock Generator 2.048 MHz Output
This pin outputs the 2.048 MHz clock signal generated by the Clock Generator.
REFA_OUT
Output
A15
REFA_OUT: Reference Clock Output A
This pin outputs a recovered clock from the Clock and Data Recovery function block of one of the four links.
The link is selected by the RO1[1:0] bits (b1~0, T1/J1-007H / b1~0, E1-007H).
REFB_OUT
Output
B14
REFB_OUT: Reference Clock Output B
This pin outputs a recovered clock from the Clock and Data Recovery function block of one of the four links.
The link is selected by the RO2[1:0] bits (b4~3, T1/J1-007H / b4~3, E1-007H).
Control Interface
RESET
Input
A14
RESET: Reset (Active Low)
A low pulse for more than 100 ns on this pin resets the device. All the registers are accessible 2 ms after the
reset. The RESET pin is a Schmitt-trigger input with a weak pull-up resistor.
GPIO[0]
GPIO[1]
Output / Input
E13
D13
General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0, T1/J1-006H / b1~0, E1-
006H) respectively. When the pins are input, their polarities are indicated by the LEVEL[1:0] bits (b3~2, T1/J1-
006H / b3~2, E1-006H) respectively. When the pins are ouput, their polarities are controlled by the
LEVEL[1:0] bits (b3~2, T1/J1-006H / b3~2, E1-006H) respectively.
GPIO[1:0] are Schmitt-trigger input/output with a pull-up resistor.
THZ
Input
B16
THZ: Transmit High-Z
A high level on this pin puts all the TTIPn/TRINGn pins into high impedance state.
THZ is a Schmitt-trigger input.
INT
Output
T11
INT: Interrupt (Active Low)
This is the open drain, active low interrupt output. This pin will stay low until all the active unmasked interrupt
indication bits are cleared.
REFR
Output
C16
REFR:
This pin should be connected to ground via an external 10K resistor.
CS
Input
N10
CS: Chip Select (Active Low)
This pin must be asserted low to enable the microprocessor interface. The signal must be asserted high at
least once after power up to clear the internal test modes. A transition from high to low must occur on this pin
for each Read/Write operation and can not return to high until the operation is completed.
CS is a Schmitt-trigger input.
Name
Type
Pin No.
Description
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Description
8
April 25, 2003
Advance Information
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
Input
R5
T5
N6
P6
R6
T6
N7
P7
R7
T7
A[9:0]: Address Bus
In parallel mode, the signals on these pins select the register for the microprocessor to access.
In SPI mode, these pins should be connected to ground.
A[9:0] are Schmitt-trigger inputs.
D[0] / SDO
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
Output / Input
T10
N9
P9
R9
T9
T8
R8
P8
D[7:0]: Bi-directional Data Bus
In parallel mode, the signals on these pins are the data for Read / Write operation.
In SPI mode, the D[7:1] pins should be connected to the ground through a 10 K resistor.
D[7:0] are Schmitt-trigger inputs/outputs.
SDO: Serial Data Output
In SPI mode, the data is serially output on this pin.
MPM
Input
P11
MPM: Micro Controller Mode
In parallel mode, set this pin low for Motorola mode or high for Intel mode.
In SPI mode, set this pin to a fixed level (high or low). This pin is useless in SPI mode.
MPM is a Schmitt-trigger input.
RW / WR / SDI
Input
P10
RW: Read / Write Select
In parallel Motorola mode, this pin is active high for read operation and active low for write operation.
WR: Write Strobe (Active Low)
In parallel Intel mode, this pin is active low for write operation.
SDI: Serial Data Input
In SPI mode, the address/control and/or data are serially input on this pin.
RW / WR / SDI is a Schmitt-trigger input.
DS / RD / SCLK
Input
R10
DS: Data Strobe (Active Low)
In parallel Motorola mode, this pin is active low.
RD: Read Strobe (Active Low)
In parallel Intel mode, this pin is active low for read operation.
SCLK: Serial Clock
In SPI mode, this pin inputs the timing for the SDO and SDI pins. The signal on the SDO pin is updated on the
falling edge of SCLK, while the signal on the SDI pin is sampled on the rising edge of SCLK.
DS / RD / SCLK is a Schmitt-trigger input.
SPIEN
Input
R11
SPIEN: Serial Microprocessor Interface Enable
When this pin is low, the microprocessor interface is in parallel mode.
When this pin is high, the microprocessor interface is in SPI mode.
SPIEN is a Schmitt-trigger input.
JTAG (per IEEE 1149.1)
TRST
Input
N12
TRST: Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. This pin is a Schmitt-triggered input with an internal pull-up
resistor. It must be connected to the RESET pin or ground when JTAG is not used.
Name
Type
Pin No.
Description
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Description
9
April 25, 2003
Advance Information
TMS
Input
R14
TMS: Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. This pin
is a Schmitt-triggered input with an internal pull-up resistor.
TCK
Input
T14
TCK: Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO
is clocked out of the device on the falling edge of TCK. This pin is a Schmitt-triggered input with an internal
pull-up resistor.
TDI
Input
R13
TDI: Test Input
The test data is sampled at this pin on the rising edge of TCK. This pin is a Schmitt-triggered input with an
internal pull-up resistor.
TDO
Tri-State
T13
TDO: Test Output
The test data are output on this pin. It is updated on the falling edge of TCK. This pin is tri-stated except dur-
ing the process of data scanning.
Power & Ground
VDDDIO
Power
E14
E15
G16
H14
H15
J15
K15
M15
M16
N16
P16
R15
VDDDIO: 3.3 V I/O Power Supply
VDDDC
Power
H7
H8
J7
J8
J9
J10
K7
K8
K9
K10
VDDDC: 1.8 V Digital Core Power Supply
VDDAR[1]
VDDAR[2]
VDDAR[3]
VDDAR[4]
Power
A10
C9
A5
A4
VDDAR[8:1]: 3.3 V Power Supply for Receiver
VDDAT[1]
VDDAT[2]
VDDAT[3]
VDDAT[4]
Power
B12
B9
B5
A3
VDDAT[8:1]: 3.3 V Power Supply for Transmitter
VDDAX[1]
VDDAX[2]
VDDAX[3]
VDDAX[4]
Power
C12
B8
B7
B2
VDDAX[8:1]: 3.3 V Power Supply for Transmit Driver
VDDAP
Power
A13
VDDAP: 3.3 V Power Analog PLL
VDDAB
Power
D12
VDDAB: 3.3 V Power Analog Bias
Name
Type
Pin No.
Description
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Description
10
April 25, 2003
Advance Information
GNDA
Ground
B3
B6
B10
B11
C3
C5
C6
C7
C8
C10
D3
D4
D7
D10
GNDA: Analog Ground
GNDD
Ground
F13
F15
G7
G8
G9
G10
G13
G15
H9
H10
J14
K13
K14
L14
L15
M14
N13
P13
P14
P15
GNDD: Digital Ground
TEST
IC
-
C15
D16
N11
P12
T12
IC: Internal Connected
Thess pins are for IDT use only and should be connected to ground.
Others
Name
Type
Pin No.
Description
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Pin Description
11
April 25, 2003
Advance Information
NC
-
B1, C1, C2, D1,
D2, E2, E3, E4,
E16, F14, F16,
G14, H3, H4,
H13, H16, J3,
J4, J13, J16,
K3, K4, K16,
L2, L3, L4, L13,
L16, M1, M2,
M3, M4, M13,
N1, N2, N8,
N14, N15, R12,
R16, T15, T16
NC: Not Connected
Name
Type
Pin No.
Description
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
12
April 25, 2003
Advance Information
3
FUNCTIONAL DESCRIPTION
The IDT82P2284 is a highly featured single device solution for T1/
E1/J1 trunks. Each link of the IDT82P2284 can be independently config-
ured. The configuration is performed through a SPI or parallel micropro-
cessor interface.
LINE INTERFACE - RECEIVE PATH
In the receive path, the signals from the line side are coupled into
the RTIPn and RRINGn pins and pass through an Impedance Termina-
tor. An Adaptive Equalizer is provided to increase the sensitivity for small
signals. Clock and data are recovered from the digital pulses output from
the slicer. After passing through the Receive Jitter Attenuator (can be
enabled or disabled), the recovered data is decoded using B8ZS (for T1/
J1) / HDB3 (for E1) or AMI line code rules and clocked into the Frame
Processor. Loss of signal, line code violations and excessive zero are
detected.
FRAMER - RECEIVE PATH
In T1/J1 Mode, the recovered data and clock of each link can be
configured in Super Frame (SF), Extended Super Frame (ESF), T1 Digi-
tal Multiplexer (DM) or Switch Line Carrier - 96 (SLC-96) formats. (The
T1 DM and SLC-96 formats only exist in T1 mode). The framing can also
be bypassed (unframed mode). The Framer detects and indicates the
out of SF/ESF/DM/SLC-96 synchronization event, the Yellow, Red and
AIS alarms. The Framer also detects the presence of inband loopback
codes and bit-oriented messages. Frame Alignment Signal errors, CRC-
6 errors, out of SF/ESF/T1 DM/SLC-96 events and Frame Alignment
position changes are counted. Up to three HDLC links (in ESF and T1
DM format) or two HDLC links (in SF and SLC-96 format) are provided
to extract the HDLC message on the DL bit (in ESF format) / D bit in
CH24 (in T1 DM format) or any arbitrary position. In the T1/J1 receive
path, signaling debounce, signaling freeze, idle code substitution, digital
milliwatt code insertion, idle code insertion, data inversion and pattern
generation or detection are supported on a per-channel basis. An Elastic
Store Buffer that supports controlled slip and adaptation to backplane
timing may be enabled. In the Receive System Interface, various operat-
ing modes can be selected to output signals to the system.
In E1 Mode, the recovered data and clock of each link can be con-
figured to frame to Basic Frame, CRC Multi-Frame and Signaling Multi-
Frame. The framing can be bypassed (unframed mode). The Framer
detects and indicates the following event: out of Basic Frame Sync, out
of CRC Multi-Frame, out of Signaling Multi-Frame, Remote Alarm Indi-
cation signal and Remote Signaling Multi-Frame Alarm Indication signal.
The Framer also monitors Red and AIS alarms. Basic Frame Alignment
Signal errors, Far End Block Errors (FEBE) and CRC errors are
counted. Up to three HDLC links are provided to extract the HDLC mes-
sage on TS16, the Sa National bits or any arbitrary timeslot. In the E1
receive path, signaling debounce, signaling freezing, idle code substitu-
tion, digital milliwatt code insertion, trunk conditioning, data inversion
and pattern generation or detection are also supported on a per-timeslot
basis. An Elastic Store Buffer that supports slip buffering and adaptation
to backplane timing may be enabled. In the Receive System Interface,
various operating modes can be selected to output signals to the sys-
tem.
SYSTEM INTERFACE
On the system side, if the device is in T1/J1 mode, the data stream
of 1.544 Mbit/s can be converted to/from the data stream of 2.048 Mbit/s
by software configuration. In addition, the four links can be grouped into
one set. The set can be multiplexed to or de-multiplexed from one of the
two 8.192 Mbit/s buses. If the device is in E1 mode, the four links can be
multiplexed to or de-multiplexed from one of the two 8.192 Mbit/s buses.
FRAMER - TRANSMIT PATH
In the transmit path, the Transmit System Interface inputs the sig-
nals with various operating modes. In T1/J1 mode, the signals can be
processed by a Transmit Payload Control to execute the signaling inser-
tion, idle code substitution, data insertion, data inversion and test pattern
generation or detection on a per-channel basis. The transmit path of
each transceiver can be configured to generate SF, ESF, T1 DM or SLC-
96. The framer can also be disabled (unframed mode). The Framer can
transmit Yellow alarm and AIS alarm. Inband loopback codes and bit ori-
ented message can be transmitted. Up to three HDLC links (in ESF and
T1 DM format) or two HDLC links (in SF and SLC-96 format) are pro-
vided to insert the HDLC message on the DL bit (in ESF format) / D bit in
CH24 (in T1 DM format) or any arbitrary position. After passing through
a Transmit Buffer, the processed data and clock are input to the
Encoder.
In E1 mode, the signals can be processed by a Transmit Payload
Control to execute the signaling insertion, idle code substitution, data
insertion, data inversion and test pattern generation or detection on a
per-timeslot basis. The transmit path of each transceiver can be config-
ured to generate Basic Frame, CRC Multi-Frame and Signaling Multi-
Frame. The framer can be disabled (unframed mode). The Framer can
transmit Remote Alarm Indication signal, the Remote Signaling Multi-
Frame Alarm Indication signal, AIS alarm and FEBE. Three HDLC links
are provided to insert the HDLC message on TS16, the Sa National bits
or any arbitrary timeslot. The processed data and clock are input to the
Encoder.
LINE INTERFACE - TRANSMIT PATH
The data is encoded using AMI or B8ZS (for T1/J1) and HDB3 (for
E1) line code rules. The Transmit Jitter Attenuator, if enabled, is pro-
vided with a FIFO in the transmit data path. A de-jittered clock is gener-
ated by an integrated digital phase-locked loop and is used to read data
from the FIFO. The shapes of the pulses are user programmable to
ensure that the T1/E1/J1 pulse template is met after the signal passing
through different cable lengths and types. Bipolar violation can be
inserted for diagnostic purposes if AMI line code rule is enabled. The
signal is transmitted on the TTIPn and TRINGn pins through an Imped-
ance Terminator.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
13
April 25, 2003
Advance Information
TEST AND DIAGNOSES
To facilitate the testing and diagnostic functions, Analog Loopback,
Remote Digital Loopback, Remote Loopback, Local Digital Loopback,
Payload Loopback and System Loopback are also integrated in the
IDT82P2284. A programmable pseudo random bit sequence can be
generated in receive/transmit direction and detected in the opposite
direction for testing purpose.
The G.772 Non-intrusive monitoring and JTAG are also supported
by the IDT82P2284.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
14
April 25, 2003
Advance Information
3.1
T1 / E1 / J1 MODE SELECTION
Each link in the IDT82P2284 can be configured as a duplex T1
transceiver, or a duplex E1 transceiver, or a duplex J1 transceiver. When
it is in T1 mode, Super Frame (SF), Extended Super Frame (ESF), T1
Digital Multiplexer (T1 DM) and Switch Line Carrier - 96 (SLC-96) fram-
ing formats can be selected. When it is in J1 mode, Super Frame (SF)
and Extended Super Frame (ESF) formats can be selected. All the
selections are made by the TEMODE bit, the T1/J1 bit and the FM[1:0]
bits as shown in Table 1.
Table 1: Operating Mode Selection
TEMODE T1/J1 FM[1:0]
Operating Mode
1
0
0 0
T1 mode SF format
0 1
T1 mode ESF format
1 0
T1 mode T1 DM format
1 1
T1 mode SLC-96 format
1
0 0
J1 mode SF format
0 1
J1 mode ESF format
0
X
X
E1 mode
Table 2: Related Bit / Register In Chapter 3.1
Bit
Register
Address (Hex)
TEMODE
T1/J1 Or E1 Mode
020, 120, 220, 320
T1/J1
FM[1:0]
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
15
April 25, 2003
Advance Information
3.2
RECEIVER IMPEDANCE MATCHING
The receiver impedance matching can be realized by using internal
impedance matching circuit or external impedance matching circuit.
When the R_TERM[2] bit is `0', the internal impedance matching
circuit is enabled. 100
, 110 , 75 or 120 internal impedance
matching circuit can be selected by the R_TERM[1:0] bits.
When the R_TERM[2] bit is `1', the internal impedance matching
circuit is disabled, and different external resistors should be used to real-
ize different impedance matching.
Figure 2 shows the appropriate components to connect with the
cable for one link. Table 3 lists the recommended impedance matching
value for the receiver.
Figure 2. Receive / Transmit Line Circuit
In short haul applications, after the data stream passes through the
receive internal impedance circuitry, the non-intrusive monitoring can be
performed between two devices. The monitored link of one device is in
normal operation, and the monitoring link of the other device taps the
monitored one through a high impedance bridging circuit (refer to
Figure 3 and Figure 4). Because of the high resistance bridging circuit,
the signal arriving at the RTIPn/RRINGn of the monitoring link is dramat-
ically attenuated. To compensate this attenuation, the Monitor Gain can
be used to boost the signal by 22 dB, 26 dB and 32 dB selected by the
MG[1:0] bits. For normal operation, the Monitor Gain should be set to 0
dB, i.e. the Monitor Gain of the monitored link should be 0 dB.
Table 3: Impedance Matching Value For The Receiver
Cable
Configuration
Internal Termination
External Termination
R_TERM[2:0]
R
R
R_TERM[2:0]
R
R
75
(E1)
0 0 0
120
1 X X
75
120
(E1)
0 0 1
120
100
(T1)
0 1 0
100
110
(J1)
0 1 1
110
A
B
R
X
Line
R
R
T
X
Line
R
T
R
T
RTIP
RRING
TRING
TTIP
I
D
T82
P2284
(
o
ne of
t
he f
o
u
r
i
dent
i
c
al
l
i
n
ks)
VDDAX
VDDAX
D4
D3
D2
D1
1:1
2:1
D6
D5
D8
D7
Cp
VDDAR
VDDAR
Note: 1. Common decoupling capacitor
2. Cp 0-560 (pF)
3. D1 - D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060
0.1
F
GNDA
VDDAX
68
F
1
3.3 V
0.1
F
GNDA
VDDAR
68
F
3.3 V
1
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
16
April 25, 2003
Advance Information
Figure 3. Monitoring Receive Path
Figure 4. Monitoring Transmit Path
RTIPn
RRINGn
RTIPn
RRINGn
Monitored Link
Monitoring Link
DSX cross connect point
R
Monitor Gain
= 0 dB
Monitor Gain
=22/26/32 dB
TTIPn
TRINGn
RTIPn
RRINGn
Monitored Link
Monitoring Link
DSX cross connect point
R
Monitor Gain
=22/26/32 dB
Table 4: Related Bit / Register In Chapter 3.2
Bit
Register
Address (Hex)
R_TERM[2:0]
Transmit And Receive Termination Configuration
032, 132, 232, 332
MG[1:0]
Receive Configuration 2
02A, 12A, 22A, 32A
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
17
April 25, 2003
Advance Information
3.3
ADAPTIVE EQUALIZER
The Adaptive Equalizer can remove most of the signal distortion
due to intersymbol interference caused by cable attenuation and distor-
tion. Usually, the Adaptive Equalizer is off in short haul applications and
is on in long haul applications, which is configured by the EQ_ON bit.
The peak detector keeps on measuring the peak value of the
incoming signals during a selectable observation period. The observa-
tion period is selected by the UPDW[1:0] bits. A shorter observation
period allows quicker response to pulse amplitude variation, while a
longer observation period can minimize the possible overshoots.
Based on the observed peak value for a period, the equalizer will
be adjusted to achieve a normalized signal. The LATT[4:0] bits indicate
the signal attenuation introduced by the cable in approximately 2 dB per
step.
In short haul application, the receive sensitivity is -10 dB in both T1/
J1 and E1 modes. In long haul application, the receive sensitivity is -36
dB in T1/J1 mode or -43 dB in E1 mode.
3.4
DATA SLICER
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The criteria of
mark or space generation are based on a selected ratio of the incoming
signal amplitude against the peak value detected during the observation
period. This ratio is selected by the SLICE[1:0] bits. The output of the
Data Slicer is forwarded to the Clock and Data Recovery unit.
3.5
CLOCK AND DATA RECOVERY
The Clock and Data Recovery is used to recover the clock signal
from the received data. It is accomplished by Digital Phase Locked Loop
(DPLL). The recovered clock tracks the jitter in the data output from the
Data Slicer and keeps the phase relationship between data and clock
during the absence of the incoming pulse.
Table 5: Related Bit / Register In Chapter 3.3 & Chapter 3.4
Bit
Register
Address (Hex)
EQ_ON
Receive Configuration 1
029, 129, 229, 329
UPDW[1:0]
Receive Configuration 2
02A, 12A, 22A, 32A
SLICE[1:0]
LATT[4:0]
Line Status Register 1
037, 137, 237, 337
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
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April 25, 2003
Advance Information
3.6
RECEIVE JITTER ATTENUATOR
The Receive Jitter Attenuator of each link can be chosen to be
used or not. This selection is made by the RJA_E bit.
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
Figure 5.
Figure 5. Jitter Attenuator
The FIFO is used as a pool to buffer the jittered input data, then the
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the RJA_DP[1:0]
bits. Accordingly, the constant delay produced by the Jitter Attenuator is
16 bits, 32 bits or 64 bits. The 128-bit FIFO is used when large jitter tol-
erance is expected, while the 32-bit FIFO is used in delay sensitive
applications.
The DPLL is used to generate a de-jittered clock to clock out the
data stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter whose fre-
quency is lower than the CF passes through the DPLL without any atten-
uation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or 1.26
Hz, as selected by the RJA_BW bit. In E1 applications, the CF of the
DPLL can be 6.77 Hz or 0.87 Hz, as selected by the RJA_BW bit. The
lower the CF is, the longer time is needed to achieve synchronization.
If the incoming data moves faster than the outgoing data, the FIFO
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
RJA_IS bit. When the RJA_IS bit is `1', an interrupt will be reported on
the INT pin if enabled by the RJA_IE bit.
To avoid overflow or underflow, the JA-Limit function can be
enabled by setting the RJA_LIMT bit. When the JA-Limit function is
enabled, the speed of the outgoing data will be adjusted automatically if
the FIFO is close to its full or emptiness. The criteria of speed adjust-
ment start are listed in Table 6. Though the JA-Limit function can reduce
the possibility of FIFO overflow and underflow, the quality of jitter attenu-
ation is deteriorated.
Selected by the RJITT_TEST bit, the real time interval between the
read and write pointer of the FIFO or the peak-peak interval between the
read and write pointer of the FIFO can be indicated in the RJITT[6:0]
bits. When the RJITT_TEST bit is `0', the current interval between the
read and write pointer of the FIFO will be written into the RJITT[6:0] bits.
When the RJITT_TEST bit is `1', the current interval will be compared
with the old one in the RJITT[6:0] bits and the larger one will be indi-
cated by the RJITT[6:0] bits.
The performance of Receive Jitter Attenuator meets the ITU-T
I.431, G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/
13, AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.9 Jitter Tolerance and Chapter 7.10 Jitter
Transfer for details.
Table 6: Criteria Of Speed Adjustment Start
FIFO Depth
Criteria Of Speed Adjustment Start
32 bits
2-bit close to full or empty
64 bits
3-bit close to full or empty
128 bits
4-bit close to full or empty
FIFO
32/64/128
DPLL
Jittered Data
De-jittered Data
Jittered Clock
De-jittered Clock
write
pointer
read
pointer
Table 7: Related Bit / Register In Chapter 3.6
Bit
Register
Address (Hex)
RJA_E
Receive Jitter Attenuation Configuration 027, 127, 227, 327
RJA_DP[1:0]
RJA_BW
RJA_LIMT
RJITT_TEST
RJA_IS
Interrupt Status 1
03B, 13B, 23B, 33B
RJA_IE
Interrupt Enable Control 1
034, 134, 234, 334
RJITT[6:0]
Receive Jitter Measure Value Indication 039, 139, 239, 339
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
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April 25, 2003
Advance Information
3.7
DECODER
3.7.1
LINE CODE RULE
3.7.1.1
T1 / J1 Mode
In T1/J1 mode, the AMI and B8ZS line code rules are provided. The
selection is made by the R_MD bit.
3.7.1.2
E1 Mode
In E1 mode, the AMI and HDB3 line code rules are provided. The
selection is made by the R_MD bit.
3.7.2
DECODE ERROR DETECTION
3.7.2.1
T1 / J1 Mode
The decode errors can be divided into three types in T1/J1 mode:
1. Bipolar Violation (BPV) Error: When AMI line code rule is used,
the BPV error will be detected if two consecutive pulses are received
with the same polarity (refer to Figure 6). The event of the Bipolar Viola-
tion (BPV) Error is forwarded to the Performance Monitor.
2. B8ZS Code Violation (CV) Error: When B8ZS line code rule is
used, a CV error is detected when the received code does not match the
standard B8ZS line code pattern (expect the Excessive Zero error).
3. Excessive Zero (EXZ) Error: EXZ error can be detected in both
AMI and B8ZS line code rules. There are two standards defining the
EXZ error: ANSI and FCC. The EXZ_DEF bit chooses a standard for the
corresponding link to judge the EXZ error. Table 8 shows the definition of
EXZ. To count the event of the Excessive Zero (EXZ) Error, the
EXZ_ERR[1:0] bits should be set to `01'. The Excessive Zero (EXZ)
Error is counted in an internal 16-bit EXZ counter. The content in the
EXZ counter is transferred to the EXZ Error Counter L-Byte & H-Byte
registers in two ways:
a. When the CNT_MD bit is `0', the Manual-Report mode is
selected. The EXZ counter transfers its content to the EXZ Error
Counter L-Byte & H-Byte registers when there is a transition from `0' to
`1' on the CNT_TRF bit;
b. When the CNT_MD bit is `1', the Auto-Report mode is selected.
The EXZ counter transfers its content to the EXZ Error Counter L-Byte &
H-Byte registers every one second automatically.
After the content in the counter is transferred to the EXZ Error
Counter L-Byte & H-Byte registers, the counter will be cleared to `0' and
start a new round counting automatically. No error event is lost during
data transferring.
The overflow of the counter is reflected by the CNTOV_IS bit, and
can trigger an interrupt if the corresponding CNT_IE bit is set.
When the Bipolar Violation (BPV) Error or the B8ZS Code Violation
(CV) Error is detected, it will be indicated by the CV_IS bit. When the
Excessive Zero (EXZ) Error is detected, it will be indicated by the
EXZ_IS bit. When the CV_IS bit or the EXZ_IS bit is `1', an interrupt will
be reported by the INT pin if enabled by the corresponding CV_IE bit or
the EXZ_IE bit.
3.7.2.2
E1 Mode
The decode errors can be divided into three types in E1 mode:
1. Bipolar Violation (BPV) Error: When AMI line code rule is used,
the BPV error will be detected if two consecutive pulses are received
with the same polarity (refer to Figure 6). The event of the Bipolar Viola-
tion (BPV) Error is forwarded to the Performance Monitor.
2. HDB3 Code Violation (CV) Error: When HDB3 line code rule is
used, a CV error is detected if two consecutive BPV errors are detected,
and the pulses that have the same polarity as the previous pulse are not
the HDB3 zero substitution pulsed (refer to Figure 8).
3. Excessive Zero (EXZ) Error: EXZ error can be detected in both
AMI and HDB3 line code rules. There are two standards defining the
EXZ error: ANSI and FCC. The EXZ_DEF bit chooses a standard for the
corresponding link to judge the EXZ error. Table 8 shows the definition of
EXZ. To count the event of the Excessive Zero (EXZ) Error, the
EXZ_ERR[1:0] bits should be set to `01'. The Excessive Zero (EXZ)
Error is counted in an internal 16-bit EXZ counter. The content in the
EXZ counter is transferred to the EXZ Error Counter L-Byte & H-Byte
registers in two ways:
a. When the CNT_MD bit is `0', the Manual-Report mode is
selected. The EXZ counter transfers its content to the EXZ Error
Counter L-Byte & H-Byte registers when there is a transition from `0' to
`1' on the CNT_TRF bit;
b. When the CNT_MD bit is `1', the Auto-Report mode is selected.
The EXZ counter transfers its content to the EXZ Error Counter L-Byte &
H-Byte registers every one second automatically.
After the content in the counter is transferred to the EXZ Error
Counter L-Byte & H-Byte registers, the counter will be cleared to `0' and
start a new round counting automatically. No error event is lost during
data transferring.
The overflow of the counter is reflected by the CNTOV_IS bit, and
can trigger an interrupt if the corresponding CNT_IE bit is set.
When the Bipolar Violation (BPV) Error or the HDB3 Code Violation
(CV) Error is detected, it will be indicated by the CV_IS bit. When the
Excessive Zero (EXZ) Error is detected, it will be indicated by the
EXZ_IS bit. When the CV_IS bit or the EXZ_IS bit is `1', an interrupt will
be reported by the INT pin if enabled by the corresponding CV_IE bit or
the EXZ_IE bit.
Table 8: Excessive Zero Error Definition
ANSI
FCC
AMI
More than 15 consecutive 0s are
detected.
More than 80 consecutive 0s are
detected.
B8ZS
More than 8 consecutive 0s are
detected (refer to Figure 7).
More than 8 consecutive 0s are
detected (refer to Figure 7).
HDB3
More than 3 consecutive 0s are
detected (refer to Figure 8).
More than 3 consecutive 0s are
detected (refer to Figure 8).
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
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April 25, 2003
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Figure 6. AMI Bipolar Violation Error
Figure 7. B8ZS Excessive Zero Error
Figure 8. HDB3 Code Violation & Excessive Zero Error
3.7.3
LOS DETECTION
The Loss of Signal (LOS) Detector monitors the amplitude and den-
sity of the received signal. When the received signal is below an ampli-
tude for continuous intervals, the LOS is detected. When the received
signal is above the amplitude and the density of marks meets the
requirement, the LOS is cleared.
The different criteria for LOS Declaring/Clearing are illustrated in
Table 9 and Table 10. In T1/J1 mode, the LOS detection supports ANSI
T1.231 and I.431. In E1 mode, the LOS detection supports ITU-T G.775
and I.431. The criteria are selected by the LAC bit.
When the LOS is detected, it will be indicated by the LOS_S bit.
Selected by the LOS_IES bit, a transition from '0' to '1' on the LOS_S bit
or any transition (from `0' to `1' or from `1' to `0') on the LOS_S bit will set
the LOS_IS bit to `1'. When the LOS_IS bit is `1', an interrupt will be
reported by the INT pin if enabled by the LOS_IE bit.
During LOS, if the RAISE bit is set to `1', all 'One's will be inserted
to the received data stream.
Bipolar violation
clock
RTIPn
RRINGn
1
2
3
4
5
V
6
7
Excessive zero
clock
RTIPn
RRINGn
8 consecutive
zeros
1
2
3
5
4
6
7
8
9
Excessive zero
clock
RTIPn
RRINGn
Code violation
4 consecutive
zeros
1
2
3
4
V
V
5
6
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
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April 25, 2003
Advance Information
Table 9: LOS Condition In T1/J1 Mode
Loss of Signal in T1/J1 Mode
Short Haul Application
Long Haul Application
ANSI T1.231
I.431
ANSI T1.231
I.431
LOS
Detected
Amplitude
below 800 mVpp
below 800 mVpp
below Q dB *
below Q dB *
Continuous Intervals 175 bits
1544 bits
175 bits
1544 bits
LOS
Cleared
Amplitude
above 1 Vpp
above 1 Vpp
above Q + 4 dB *
above Q + 4 dB *
Mark Density
12.5% (16 marks in a hopping
128-bit window **) with less
than 100 continuous zeros
12.5% (16 marks in a hopping
128-bit window **) with less
than 100 continuous zeros
12.5% (16 marks in a hopping
128-bit window **) with less
than 100 continuous zeros
12.5% (16 marks in a hopping
128-bit window **) with less
than 100 continuous zeros
Note:
*
The Q dB is set in the LOS[4:0] bits.
** A hopping 128-bit window means this: An entire 128 bits is taken from the data stream and is checked. If the criteria are not met, all the 128 bits are thrown and another 128 bits are
caught for checking.
Table 10: LOS Condition In E1 Mode
Loss of Signal in E1 Mode
Short Haul Application
Long Haul Application
G.775
I.431
G.775
I.431
LOS
Detected
Amplitude
below 800 mVpp
below 800 mVpp
below Q dB *
below Q dB *
Continuous Intervals 32 bits
2048 bits
32 bits
2048 bits
LOS
Cleared
Amplitude
above 1 Vpp
above 1 Vpp
above Q + 4 dB *
above Q + 4 dB *
Mark Density
12.5% (4 marks in a hopping
32-bit window **) with less than
16 continuous zeros
12.5% (4 marks in a hopping
32-bit window **) with less than
16 continuous zeros
12.5% (4 marks in a hopping
32-bit window **) with less than
16 continuous zeros
12.5% (4 marks in a hopping
32-bit window **) with less than
16 continuous zeros
Note:
* The Q dB is set in the LOS[4:0] bits.
** A hopping 32-bit window means this: An entire 32 bits is taken from the data stream and is checked. If the criteria are not met, all the 32 bits are thrown and another 32 bits are caught
for checking.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
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April 25, 2003
Advance Information
Table 11: Related Bit / Register In Chapter 3.7
Bit
Register
Address (Hex)
R_MD
Receive Configuration 0
028, 128, 228, 328
EXZ_ERR
Maintenance Function Control 2
031, 131, 231, 331
EXZ_DEF
CNT_MD
CNT_TRF
CNTL[7:0]
EXZ Error Counter L-Byte
03D, 13D, 23D, 33D
CNTH[7:0]
EXZ Error Counter H-Byte
03C, 13C, 23C, 33C
CV_IS
Interrupt Status 1
03B, 13B, 23B, 33B
EXZ_IS
CNTOV_IS
CV_IE
Interrupt Enable Control 1
034, 134, 234, 334
EXZ_IE
CNT_IE
LAC
Maintenance Function Control 1
02C, 12C, 22C, 32C
RAISE
LOS_S
Line Status Register 0
036, 136, 236, 336
LOS_IES
Interrupt Trigger Edges Select
035, 135, 235, 335
LOS_IS
Interrupt Status 0
03A, 13A, 23A, 33A
LOS_IE
Interrupt Enable Control 0
033, 133, 233, 333
LOS[4:0]
Receive Configuration 1
029, 129, 229, 329
IDT82P2284
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3.8
FRAME PROCESSOR
3.8.1
T1/J1 MODE
In T1/J1 mode, the Frame Processor searches for the frame align-
ment patterns in the standard Super-Frame (SF), Extended Super-
Frame (ESF), T1 Digital Multiplexer (DM) or Switch Line Carrier - 96
(SLC-96) framing formats. The T1 DM and SLC-96 formats are only sup-
ported in T1 mode. The Frame Processor acquires frame alignment per
ITU-T requirement.
When frame alignment is achieved, the Framer Processor contin-
ues to monitor the received data stream. The Frame Processor will
declare framing bit errors or bit error events events if any. The Frame
Processor can also detect out-of-frame events based on selected crite-
ria.
The Frame Processor can also be bypassed by setting the UNFM
bit.
3.8.1.1
Synchronization Searching
3.8.1.1.1
Super Frame (SF) Format
The structure of T1/J1 SF is illustrated in Table 12. The SF is made
up of 12 frames. Each frame consists of one overhead bit (F-bit) and 24
8-bit channels. Its Frame Alignment Pattern is `100011011100' for T1
and `10001101110X' for J1 located in the F-bit position. The same pat-
tern is a mimic pattern if it is received in the data stream other than F-bit.
The synchronization criteria of SF format is selected by the MIMICC bit.
When the MIMICC bit is set to `1', the SF synchronization is acquired if
two consecutive Frame Alignment Patterns are received error free in the
data stream without a mimic pattern. When the MIMICC bit is set to `0',
the SF synchronization is acquired if two consecutive Frame Alignment
Patterns are received error free in the data stream. In this case, the
existence of mimic patterns is ignored. If a mimic pattern exists during
the frame searching procedure, the MIMICI bit will be set to indicate the
presence of a mimic pattern.
The SF synchronization is indicated by `0' in the OOFV bit. The
RMFBI bit is set at the first bit of each SF frame.
Table 12: The Structure of SF
Frame No. In The SF
F-Bit (Frame Alignment)
The Bit In Each Channel
Ft
Fs
Data Bit
Signaling Bit
1
1
1 - 8
-
2
0
1 - 8
-
3
0
1 - 8
-
4
0
1 - 8
-
5
1
1 - 8
-
6
1
1 - 7
A (bit 8)
7
0
1 - 8
-
8
1
1 - 8
-
9
1
1 - 8
-
10
1
1 - 8
-
11
0
1 - 8
-
12
X
1 - 7
B (bit 8)
Note:
`X' should be logic 0 in T1 FAS.
`X' can be logic 0 or 1 in J1 FAS because this position is used as Yellow Alarm Indication bit.
IDT82P2284
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April 25, 2003
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3.8.1.1.2
Extended Super Frame (ESF) Format
The structure of T1/J1 ESF is illustrated in Table 13. The ESF is
made up of 24 frames. Each frame consists of one overhead bit (F-bit)
and 24 8-bit channels. The F-bit in Frame (4n) (0<n<7) is for Frame
Alignment; the F-bit in Frame (2n-1) (0<n<13) is for Data Link; and the
F-bit in Frame (4n-2) (0<n<7) is for CRC checking.
The Frame Alignment Pattern is `001011', which is located in
Frame (4n) (0<n<7). The same pattern is a mimic pattern if it is received
in the data stream other than F-bit. The synchronization criteria of ESF
format is selected by the MIMICC bit. When the MIMICC bit is set to `1',
the ESF synchronization is acquired if four consecutive Frame Align-
ment Patterns are detected error free in the received data stream with-
out a mimic pattern. When the MIMICC bit is set to `0', the ESF
synchronization is acquired if a single correct Frame Alignment Pattern
and a single correct CRC-6 based on this correct Frame Alignment Pat-
tern are found. In this case, the existence of mimic patterns is ignored. If
a mimic pattern exists during the frame searching procedure, the MIMICI
bit will be set to indicate the presence of a mimic pattern.
The ESF synchronization is indicated by `0' in the OOFV bit. The
RMFBI bit is set at the first bit of each ESF frame.
Table 13: The Structure of ESF
Frame No. In The ESF
F-Bit Assignment
The Bit In Each Channel
Frame Alignment
Data Link
CRC
Data Bit
Signaling Bit
1
-
DL
-
1 - 8
-
2
-
-
C1
1 - 8
-
3
-
DL
-
1 - 8
-
4
0
-
-
1 - 8
-
5
-
DL
-
1 - 8
-
6
-
-
C2
1 - 7
A (bit 8)
7
-
DL
-
1 - 8
-
8
0
-
-
1 - 8
-
9
-
DL
-
1 - 8
-
10
-
-
C3
1 - 8
-
11
-
DL
-
1 - 8
-
12
1
-
-
1 - 7
B (bit 8)
13
-
DL
-
1 - 8
-
14
-
-
C4
1 - 8
-
15
-
DL
-
1 - 8
-
16
0
-
-
1 - 8
-
17
-
DL
-
1 - 8
-
18
-
-
C5
1 - 7
C (bit 8)
19
-
DL
-
1 - 8
-
20
1
-
-
1 - 8
-
21
-
DL
-
1 - 8
-
22
-
-
C6
1 - 8
-
23
-
DL
-
1 - 8
-
24
1
-
-
1 - 7
D (bit 8)
IDT82P2284
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3.8.1.1.3
T1 Digital Multiplexer (DM) Format (T1 only)
The structure of T1 DM is illustrated in Table 14. The T1 DM is
made up of 12 frames. Each frame consists of one overhead bit (F-bit)
and 24 8-bit channels. Except for channel 24, all other channels carry
data. Channel 24 should be `0DY11101'. Its Frame Alignment Pattern is
`100011011100' in the F-bit. The fixed 6 bits in channel 24 are called
DDS.
The synchronization criteria of T1 DM format are selected by the
DDSC bit. When the DDSC bit is `0', the T1 DM synchronization is
acquired if one correct DDS pattern is received before the first F-bit of a
single correct Frame Alignment Pattern. When the DDSC bit is `1', the
T1 DM synchronization is acquired if a single correct Frame Alignment
Pattern is received and twelve correct DDS patterns before each F-bit of
the correct Frame Alignment Pattern are all detected.
The T1-DM synchronization is indicated by `0' in the OOFV bit. The
RMFBI bit is set at the first bit of each T1 DM frame.
Table 14: The Structure of T1 DM
Frame No. In The T1 DM
F-Bit (Frame Alignment)
Channel 24
Ft
Fs
1
1
0DY11101
2
0
0DY11101
3
0
0DY11101
4
0
0DY11101
5
1
0DY11101
6
1
0DY11101
7
0
0DY11101
8
1
0DY11101
9
1
0DY11101
10
1
0DY11101
11
0
0DY11101
12
0
0DY11101
Note:
In Channel 24, the `D' bit is used for data link, and the `Y' bit is used for alarm. The other 6 bits are fixed and they are called `DDS' pattern.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
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3.8.1.1.4
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
The structure of SLC-96 is illustrated in Table 15. The SLC-96 is
made up of 6 SFs, but some F-bit are used as Concentrator Bits, Spoiler
Bits, Maintenance Bits, Alarm Bits and Switch Bits. Each frame consists
of one overhead bit (F-bit) and 24 8-bit channels. Its Frame Alignment
Pattern is `001000110111001000110111' in 24 consecutive F-bit posi-
tions. If the Frame Alignment Pattern is found in 24 consecutive F-bit
positions in the data stream, the SLC-96 synchronization is acquired.
The first frame is numbered from the frame whose F-bit contains the first
`1' of the Frame Alignment Pattern.
The SLC-96 synchronization is indicated by `0' in the OOFV bit.
The RMFBI bit is set at the first bit of each SLC-96 frame.
Table 15: The Structure of SLC-96
Frame No.
F-Bit (Frame Alignment) - Ft
The Bit In Each Channel
Frame No.
F-Bit (Frame Alignment) - Fs
The Bit In Each Channel
Data Bit
Signaling Bit
Data Bit
Signaling Bit
1
1
1 - 8
-
2
0
1 - 8
-
3
0
1 - 8
-
4
0
1 - 8
-
5
1
1 - 8
-
6
1
1 - 7
A (bit 8)
7
0
1 - 8
-
8
1
1 - 8
-
9
1
1 - 8
-
10
1
1 - 8
-
11
0
1 - 8
-
12
0
1 - 7
B (bit 8)
13
1
1 - 8
-
14
0
1 - 8
-
15
0
1 - 8
-
16
0
1 - 8
-
17
1
1 - 8
-
18
1
1 - 7
C (bit 8)
19
0
1 - 8
-
20
1
1 - 8
-
21
1
1 - 8
-
22
1
1 - 8
-
23
0
1 - 8
-
24
C1 (Concentrator Bit)
1 - 7
D (bit 8)
25
1
1 - 8
-
26
C2 (Concentrator Bit)
1 - 8
-
27
0
1 - 8
-
28
C3 (Concentrator Bit)
1 - 8
-
29
1
1 - 8
-
30
C4 (Concentrator Bit)
1 - 7
A (bit 8)
31
0
1 - 8
-
32
C5 (Concentrator Bit)
1 - 8
-
33
1
1 - 8
-
34
C6 (Concentrator Bit)
1 - 8
-
35
0
1 - 8
-
36
C7 (Concentrator Bit)
1 - 7
B (bit 8)
37
1
1 - 8
-
38
C8 (Concentrator Bit)
1 - 8
-
39
0
1 - 8
-
40
C9 (Concentrator Bit)
1 - 8
-
41
1
1 - 8
-
42
C10 (Concentrator Bit)
1 - 7
C (bit 8)
43
0
1 - 8
-
44
C11 (Concentrator Bit)
1 - 8
-
45
1
1 - 8
-
46
0 (Spoiler Bit)
1 - 8
-
47
0
1 - 8
-
48
1 (Spoiler Bit)
1 - 7
D (bit 8)
49
1
1 - 8
-
50
0 (Spoiler Bit)
1 - 8
-
51
0
1 - 8
-
52
M1 (Maintenance Bit)
1 - 8
-
53
1
1 - 8
-
54
M2 (Maintenance Bit)
1 - 7
A (bit 8)
55
0
1 - 8
-
56
M3 (Maintenance Bit)
1 - 8
-
57
1
1 - 8
-
58
A1 (Alarm Bit)
1 - 8
-
59
0
1 - 8
-
60
A2 (Alarm Bit)
1 - 7
B (bit 8)
61
1
1 - 8
-
62
S1 (Switch Bit)
1 - 8
-
63
0
1 - 8
-
64
S2 (Switch Bit)
1 - 8
-
65
1
1 - 8
-
66
S3 (Switch Bit)
1 - 7
C (bit 8)
67
0
1 - 8
-
68
S4 (Switch Bit)
1 - 8
-
69
1
1 - 8
-
70
1 (Spoiler Bit)
1 - 8
-
71
0
1 - 8
-
72
0
1 - 7
D (bit 8)
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
27
April 25, 2003
Advance Information
3.8.1.2
Error Event And Out Of Synchronization Detection
After the frame is in synchronization, the Frame Processor contin-
ues to monitor the received data stream to detect errors and judge if it is
out of synchronization.
3.8.1.2.1
Super Frame (SF) Format
In SF format, two kinds of errors are detected:
1. Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 12). Each unmatched Ft bit leads to an Ft
bit error event. When 2 or more Ft bit errors are detected in a 6-basic-
frame fixed window, the severely Ft bit error occurs. This error event is
captured by the SFEI bit.
2. F Bit Error: Each received F bit is compared with the expected
one (refer to Table 12). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is forwarded to
the Performance Monitor.
When the F Bit Error number exceeds the ratio set in the M2O[1:0]
bits, it is out of synchronization. Then if the REFEN bit is `1', the Frame
Processor will start to search for synchronization again. If the REFEN bit
is `0', no error can lead to reframe except for manually setting. The man-
ual reframe is executed by a transition from `0' to `1' on the REFR bit.
During out of synchronization state, the error event detection is sus-
pended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.2.2
Extended Super Frame (ESF) Format
In ESF format, four kinds of errors are detected:
1. Frame Alignment Bit Error: Each received Frame Alignment bit is
compared with the expected one (refer to Table 13). Each unmatched bit
leads to a frame alignment bit error event. This error event is captured
by the FERI bit and is forwarded to the Performance Monitor.
2. CRC-6 Error: When the local calculated CRC-6 of the current
received ESF frame does not match the received CRC-6 of the next
received ESF frame, a single CRC-6 error event is generated. This error
event is captured by the BEEI bit and is forwarded to the Performance
Monitor.
3. Excessive CRC-6 Error: Once the accumulated CRC-6 errors
exceed 319 occasions (> 319) in a 1 second fixed window, an excessive
CRC-6 error event is generated. This error event is captured by the
EXCRCERI bit and is forwarded to the Performance Monitor.
4. Severely Frame Alignment Bit Error: When 2 or more frame
alignment bit errors are detected in a 1-ESF-frame fixed window, the
severely frame alignment bit error occurs. This error event is captured
by the SFEI bit.
When the Frame Alignment Bit Error number exceeds the ratio set
in the M2O[1:0] bits, it is out of synchronization. Then if the REFEN bit is
`1', the Frame Processor will start to search for synchronization again.
Additionally, the Excessive CRC-6 Error also leads to out of ESF syn-
chronization. In this condition, both the REFEN bit being `1' and the
REFCRCE bit being `1' will allow the Frame Processor to search for syn-
chronization again. If the REFEN bit is `0', no error can lead to reframe
except for manually setting. The manual reframe is executed by a transi-
tion from `0' to `1' on the REFR bit. During out of synchronization state,
the error event detection is suspended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.2.3
T1 Digital Multiplexer (DM) Format (T1 only)
In T1 DM format, three kinds of errors are detected:
1. Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 14). Each unmatched Ft bit leads to an Ft
bit error event. When 2 or more Ft bit errors are detected in a 6-basic-
frame fixed window, the severely Ft bit error occurs. This error event is
captured by the SFEI bit.
2. F Bit Error: Each received F bit is compared with the expected
one (refer to Table 14). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is forwarded to
the Performance Monitor.
3. DDS Pattern Error: The received 6-bit DDS in each CH24 is
compared with the DDS pattern - `0XX11101' (MSB left and `X' is not
cared). When one or more bits do not match the DDS pattern, a single
DDS pattern error event is generated. This error event is forwarded to
the Performance Monitor.
The 6-bit DDS pattern and its following F-bit make up a 7-bit pat-
tern. When one or more bits do not match its pattern (refer to Table 14),
a single error is generated. When this error number exceeds the ratio
set in the M2O[1:0] bits, it is out of synchronization. Then if the REFEN
bit is `1', the Frame Processor will start to search for synchronization
again. If the REFEN bit is `0', no error can lead to reframe except for
manually setting. The manual reframe is executed by a transition from
`0' to `1' on the REFR bit. During out of synchronization state, the error
event detection is suspended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.2.4
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
In SLC-96 format, only one kind of error is detected:
1. F Bit Error: The Ft bit in each odd frame and the Fs bit in Frame
(2n) (0<n<12 and n=36) is compared with the expected one (refer to
Table 15). Each unmatched bit leads to a F-bit error event. This error
event is captured by the FERI bit and is forwarded to the Performance
Monitor.
Each unmatched Ft bit in the odd frame and each unmatched Fs bit
in Frame (2n) (0<n<12 and n=36) are also counted separately. When the
number of either of them exceeds the ratio set in the M2O[1:0] bits, it is
out of synchronization. Then if the REFEN bit is `1', the Frame Proces-
sor will start to search for synchronization again. If the REFEN bit is `0',
no error can lead to reframe except for manually setting. The manual
reframe is executed by a transition from `0' to `1' on the REFR bit. During
out of synchronization state, the error event detection is suspended.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
28
April 25, 2003
Advance Information
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.3
Overhead Extraction (T1 Mode SLC-96 Format Only)
In SLC-96 format, the Concentrator bits, Maintenance bits, Alarm
bits and Switch bits are all extracted to the RDL0, RDL1 & RDL2 regis-
ters respectively.
All these extractions will be set to de-bounce if the SCDEB bit is set
to `1'. Thus, the value in the RDL0, RDL1 & RDL2 registers are updated
if the received corresponding code is the same for 2 consecutive SLC-
96 frames. Whether de-bounced or not, a change indication will be set in
the SCCI bit, SCMI bit, SCAI bit and SCSI bit respectively if the corre-
sponding codes in the RDL0, RDL1 & RDL2 registers differ from the pre-
vious ones.
The value in the RDL0, RDL1 & RDL2 registers is held during out of
SLC-96 synchronization state.
3.8.1.4
Interrupt Summary
The interrupt sources in this block are summarized in Table 16.
When there are conditions meeting the interrupt sources, the corre-
sponding Status bit will be asserted high. When there is a transition
(from `1' to `0' or from `0' to `1') on the Status bit, the corresponding Sta-
tus Interrupt Indication bit will be set to `1' (If the Status bit does not
exist, the source will cause its Status Interrupt Indication bit to `1'
directly) and the Status Interrupt Indication bit will be cleared by writing
`1'. A `1' in the Status Interrupt Indication bit indicates an interrupt
occurred. The interrupt is reported by the INT pin if its Status Interrupt
Enable bit was set to `1'.
Table 16: Interrupt Source In T1/J1 Frame Processor
Sources
Status Bit
Interrupt Indication Bit Interrupt Enable Bit
It is out of synchronization.
OOFV
OOFI
OOFE
The first bit of each SF / ESF / T1 DM / SLC-96 frame is received.
-
RMFBI
RMFBE
The new-found F bit position differs from the previous one.
-
COFAI
COFAE
In SF / T1 DM / SLC-96 format, the F Bit Error occurs.
In ESF format, the Frame Alignment Bit Error occurs.
-
FERI
FERE
In ESF format, the CRC-6 Error occurs.
(This interrupt does not exist in other formats.)
-
BEEI
BEEE
In SF / T1 DM format, the Severely Ft Bit Error occurs.
In ESF format, the Severely Frame Alignment Bit Error occurs.
(This interrupt does not exist in SLC-96 format.)
-
SFEI
SFEE
In SLC-96 format, the Concentrator bits differ from the previous ones.
-
SCCI
SCCE
In SLC-96 format, the Maintenance bits differ from the previous ones.
-
SCMI
SCME
In SLC-96 format, the Alarm bits differ from the previous ones.
-
SCAI
SCAE
In SLC-96 format, the Switch bits differ from the previous ones.
-
SCSI
SCSE
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
29
April 25, 2003
Advance Information
Table 17: Related Bit / Register In Chapter 3.8.1
Bit
Register
T1/J1 Address (Hex)
UNFM
FRMR Mode 0
04D, 14D, 24D, 34D
REFEN
REFR
REFCRCE
MIMICC
FRMR Mode 1
04E, 14E, 24E, 34E
M2O[1:0]
DDSC
OOFV
FRMR Status
04F, 14F, 24F, 34F
MIMICI
FRMR Interrupt Indication 0
052, 152, 252, 352
EXCRCERI
OOFI
RMFBI
FRMR Interrupt Indication 1
053, 153, 253, 353
SFEI
BEEI
FERI
COFAI
OOFE
FRMR Interrupt Control 0
050, 150, 250, 350
RMFBE
FRMR Interrupt Control 1
051, 151, 251, 351
SFEE
BEEE
FERE
COFAE
C[11:1]
RDL1 & RDL0
057, 157, 257, 357 & 056, 156, 256, 356
M[3:1]
RDL1
057, 157, 257, 357
A[2:1]
RDL2
058, 158, 258, 358
S[4:1]
SCAI
DLB Interrupt Indication
05D, 15D, 25D, 35D
SCSI
SCMI
SCCI
SCDEB
DLB Interrupt Control
05C, 15C, 25C, 35C
SCAE
SCSE
SCME
SCCE
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
30
April 25, 2003
Advance Information
3.8.2
E1 MODE
In E1 mode, the Frame Processor searches for Basic Frame syn-
chronization, CRC Multi-frame synchronization, and Channel Associated
Signaling (CAS) Multi-frame synchronization in the received data
stream. Figure 9 shows the searching process.
Once the frame is synchronized, the Frame Processor keeps on
monitoring the received data stream. If there are any framing bit errors,
CAS Multi-Frame alignment pattern errors, CRC Multi-Frame alignment
pattern errors or CRC errors, the Frame Processor will indicate these
errors. The status of loss of frame, loss of Signaling Multi-Frame and
loss of CRC Multi-Frame can also be detected and declared based on
user-selectable criteria. A software reset can also make the Frame Pro-
cessor reframe.
The Frame Processor can extract the data stream in TS16, and
output the extracted data on a separate pin. The Frame Processor also
extracts the contents of the International bits (from both the FAS and the
NFAS frames), the National bits and the Extra bits (from TS16 in the
frame 0 of the Signaling Multi-Frame), and stores these data in registers.
The CRC Sub Multi-Frame alignment 4 bit codeword in the National bit
positions Sa4 to Sa8 can also be extracted and stored in registers, and
updated every CRC Sub Multi-Frame.
The Framer Processor identifies the Remote Alarm bit (bit 3 of TS0
of NFAS frames) and Remote Signaling Multi-Frame Alarm (bit 6 of
TS16 of the frame 0 of the Signaling Multi-Frame). The `de-bounced'
Remote Alarm and Remote Signaling Multi-Frame Alarm can be indi-
cated if the corresponding bit has been a certain logic for 1 or 4 consec-
utive times. The AIS (Alarm Indication Signal) Alarm can also be
detected. The Frame Processor can also declare a Red Alarm if the out-
of-frame condition has persisted for at least 100 ms.
An interrupt output is provided to indicate status changes and the
occurrence of some events. The interrupts may be generated every
Basic Frame, CRC Sub Multi-Frame, CRC Multi-Frame or Signaling
Multi-Frame.
The Frame Processor can also be bypassed by setting the UNFM
bit.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
31
April 25, 2003
Advance Information
Figure 9. E1 Frame Searching Process
Out of sync.
OOFV = 1, OOCMFV = 1,
OOSMFV = 1, OOOFV = 0
find FAS in
N frame
search for Basic Fframe alignment patten
(refer to Basic Frame)
find NFAS in
(N+1) frame
th
No (N=N+1)
Yes
find FAS in
(N+2) frame
th
Yes
No (N=N+3)
Basic Frame sync. acquired
OOFV = 0
Start to check FAS errors
search for CRC Multi-Frame
alignment pattern if CRCEN =
1 (refer to CRC Multi-Frame)
Start 8ms and
400ms timer
find 2 CRC Multi-Frame
alignment patterns within 8ms, with the
interval time of each pattern being a
multiple of 2ms
Yes
CRC Multi-Frame sync.
acquired; Start CRC and
E-bits processing;
OOCMFV = 0, OOFV = 0 CRC
to CRC interworking
No, and
8ms
expired
C2NCIWV = 1
CRC to non-CRC
interworking
Stop CRC processing if
C2NCIWCK = 0
No, and 400ms
expired with
basic frame sync.
Yes
find Signaling
Multi-Frame alignment
pattern
search for Signaling Multi-Frame
alignment if CASEN = 1 (refer to
Signaling Multi-Frame)
Yes
Signaling
Multi-Frame sync.
acquired
No
check for out
of Signaling Multi-Frame
Sync conditions which criteria
are set in the SMFASC
& TS16C
No (n=n+3)
Yes
3 consecutive FAS or NFAS
errors (criteria selected by the
BIT2C) or manually re-frame
> 914
CRC
errors in
one
second
find NFAS in
(n+1) frame
th
Yes
find FAS in
(n+2) frame
th
Yes
Yes
Lock the Sync. Position
Start Offline Frame
search OOOFV = 1
Basic Frame sync. acquired
OOOFV = 0
Start 8ms timer
find 2 CRC Multi-Frame
alignment patterns within 8ms, with the
interval time of each pattern being a
multiple of 2ms
Yes
No (skip one
frame, N=N+3)
No
No (skip one
frame, n=n+3)
th
th
find FAS in
n frame
No (n = n+1)
No, and
8ms
expired
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
32
April 25, 2003
Advance Information
3.8.2.1
Synchronization Searching
3.8.2.1.1
Basic Frame
The algorithm used to search for the E1 Basic Frame alignment
pattern (as shown in Figure 10) meets the ITU-T Recommendation
G.706 4.1.2 and 4.2.
Generally, it is performed by detecting a successive FAS/NFAS/
FAS sequence. If STEP 2 is not met, a new searching will start after the
following frame is skipped. If STEP 3 is not met, a new searching will
start immediately in the next frame. Once the Basic Frame alignment
pattern is detected in the received PCM data stream, the Basic Frame
synchronization is found and the OOFV bit will be set to `0' for indication.
Figure 10. Basic Frame Searching Process
STEP1: Search
for 7-bit Frame Alignment
Sequence (FAS) (X0011011)
in the N frame
STEP 2: Find logic 1 in the
2nd bit of TS0 of the (N+1) frame to ensure
that this is a non-frame alignment
sequence (NFAS)
STEP 3: Search for
the correct 7-bit FAS (X0011011)
in the TS0 in the (N+2)
frame
Yes
No (N=N+1)
Yes
Yes
Basic Frame
Synchronization Found
No
(N=N+3)
No (skip
one frame,
N=N+3)
th
th
th
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
33
April 25, 2003
Advance Information
3.8.2.1.2
CRC Multi-Frame
The CRC Multi-Frame is provided to enhance the ability of verifying
the data stream. The structure of TS0 of the CRC Multi-Frame is illus-
trated in Table 18.
A CRC Multi-Frame consists of 16 continuous Basic Frames (No. 0
15) which are numbered from a Basic Frame with FAS. Each CRC
Multi-Frame can be divided into two Sub Multi-Frames (SMF I & SMF II).
The first bit of TS0 of each frame is called the International (Si) bit.
The Si bit in each even frame is the CRC bit. Thus, there are C1, C2,
C3, C4 in each SMF. The C1 is the most significant bit, while the C4 is
the least significant bit. The Si bit in the first six odd frames is the CRC
Multi-Frame alignment pattern. Its pattern is `001011'. The Si bit in
Frame 13 and Frame 15 are E1 and E2 bits. The value of the E bits can
indicate the Far End Block Errors (FEBE).
After the Basic Frame has been synchronized, the Frame Proces-
sor initiates an 8 and a 400 ms timer to check the CRC Multi-Frame
alignment signal if the CRCEN bit is `1'. The CRC Multi-Frame synchro-
nization is declared with a `0' in the OOCMFV bit only if at least two CRC
Multi-Frame alignment patterns are found within 8 ms, with the interval
time of each pattern being a multiple of 2 ms. Then if the received CRC
Multi-Frame alignment signal does not meet its pattern, it will be indi-
cated by the CMFERI bit.
If the 2 CRC Multi-Frame alignment patterns can not be found
within 8ms with the interval time being a multiple of 2 ms, an offline
search for the Basic Frame alignment pattern will start which is indicated
in the OOOFV bit. The process is the same as shown in Figure 10. This
offline operation searches in parallel with the pre-found Basic Frame
synchronization searching process. After the new Basic Frame synchro-
nization is found by this offline search, the 8 ms timer is restarted to
check whether the two CRC Multi-Frame alignment patterns are found
within 8 ms, with the interval time of each pattern being a multiple of 2
ms again. If the condition can not be met, the procedure will go on until
the 400 ms timer ends. If the condition still can not be met at that time
and the Basic Frame is still synchronized, the device declares by the
C2NCIWV bit to run under the CRC to non-CRC interworking process. In
this process, the CRC Multi-Frame alignment pattern can still be
searched if the C2NCIWCK bit is logic 1.
Table 18: The Structure Of TS0 In CRC Multi-Frame
SMF
Basic Frame
No. / Type
the Eight Bits in Timeslot 0
1 (Si bit)
2
3
4
5
6
7
8
CRC-4
Multi-Frame
SMF I
0 / FAS
C1
0
0
1
1
0
1
1
1 / NFAS
0
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
2 / FAS
C2
0
0
1
1
0
1
1
3 / NFAS
0
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
4 / FAS
C3
0
0
1
1
0
1
1
5 / NFAS
1
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
6 / FAS
C4
0
0
1
1
0
1
1
7 / NFAS
0
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
SMF II
8 / FAS
C1
0
0
1
1
0
1
1
9 / NFAS
1
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
10 / FAS
C2
0
0
1
1
0
1
1
11 / NFAS
1
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
12 / FAS
C3
0
0
1
1
0
1
1
13 / NFAS
E1
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
14 / FAS
C4
0
0
1
1
0
1
1
15 / NFAS
E2
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
34
April 25, 2003
Advance Information
3.8.2.1.3
CAS Signaling Multi-Frame
After the Basic Frame has been synchronized, the Frame Proces-
sor starts to search for CAS Signaling Multi-Frame alignment signal if
the CASEN bit is `1'.
The Signaling Multi-Frame alignment pattern is located in the high
nibble (Bit 1 ~ Bit 4) of TS16. Its pattern is `0000'. When the pattern is
found in TS16 and the high nibble of the previous TS16 are not all zeros,
the Signaling Multi-Frame synchronization is acquired and it is indicated
with a `0' in the OOSMFV bit. The frame containing the Signaling Multi-
Frame alignment pattern is Frame 0 of Signaling Multi-Frame. The TS16
structure of the Signaling Multi-Frame is shown in Figure 11. The entire
content in TS16 of Frame 0 of Signaling Multi-Frame is `0000XYXX'. `Y'
is for remote Signaling Multi-Frame alarm indication and `X's are extra
bits. The codeword `ABCD' are the signaling bits for different timeslots.
Figure 11. TS16 Structure Of CAS Signaling Multi-
Frame
3.8.2.2
Error Event And Out Of Synchronization Detection
After the frame is in synchronization, the Frame Processor keeps
on monitoring the received data stream to detect errors and judge if it is
out of synchronization.
The following five kinds of errors are detected:
1. FAS/NFAS Bit/Pattern Error: The criteria of this error are deter-
mined by the WORDERR bit and the CNTNFAS bit (refer to Table 19).
This error event is captured by the FERI bit and is forwarded to the Per-
formance Monitor.
2. CRC Multi-Frame Alignment Pattern Error: The received CRC
Multi-Frame alignment signals are compared with the expected ones
(`001011'). When one or more bits do not match, a single CRC Multi-
Frame alignment pattern error event is generated. This error event is
captured by the CMFERI bit.
3. CRC-4 Error: When the local calculated CRC-4 of the current
received CRC Sub Multi-Frame does not match the received CRC-4 of
the next received CRC Sub Multi-Frame, a single CRC-4 error event is
generated. This error event is captured by the CRCEI bit and is for-
warded to the Performance Monitor.
4. Excessive CRC-4 Error: Once the accumulated CRC-4 errors
are not less than 915 occasions (915 is included) in a 1 second fixed
window, an excessive CRC-4 error event is generated. This error event
is captured by the EXCRCERI bit.
5. CAS Signaling Multi-Frame Alignment Pattern Error: The
received Signaling Multi-Frame alignment signals are compared with the
expected ones (`0000'). When one or more bits do not match, a single
CAS Signaling Multi-Frame alignment pattern error event is generated.
This error event is captured by the SMFERI bit.
6. Far End Block Error (FEBE): When any of the CRC error indica-
tion (E1 or E2) bits is received as a logic 0, a far end block error event is
generated. This error event is captured by the FEBEI bit and is for-
warded to the Performance Monitor.
7. Continuous RAI & FEBE Error: When a logic 1 is received in the
A bit and a logic 0 is received in any of the E1 or E2 bit for 10 ms, the
RAICRCV bit is set. This bit is cleared if any of the conditions is not met.
8. Continuous FEBE Error: When a logic 0 is received in any of the
E1 or E2 bits on
990 occasions per second for the latest 5 consecutive
seconds, the CFEBEV bit is set, otherwise this bit will be cleared.
9. NT FEBE Error (per ETS 300 233): If the 4-bit Sa6 codeword of a
CRC Sub Multi-Frame is matched with `0001' or `0011', the Network Ter-
minal Far End Block Error event is generated. This error event is cap-
tured by the TFEBEI bit and is forwarded to the Performance Monitor.
A
B
C
D
A
B
C
D
for TS31
for TS15
A
B
C
D
A
B
C
D
for TS18
for TS2
A
B
C
D
A
B
C
D
for TS17
for TS1
F1
F2
F15
0
0
0
0
X0
Y
X1
X2
F0
Signaling Multi-Frame
alignment pattern
RMAI
Extra Bits
TS16 (Bit 1 - Bit 8)
Table 19: FAS/NFAS Bit/Pattern Error Criteria
WORDERR CNTNFAS
Error Generation
0
0
Each bit error in FAS is counted as an error event.
1
0
A FAS pattern error is counted as an error event.
0
1
Each bit error in FAS or NFAS error is counted as an
error event.
1
1
A FAS pattern error or NFAS error is counted as an
error event.
IDT82P2284
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10. NT CRC Error (per ETS 300 233): If the 4-bit Sa6 codeword of
a CRC Sub Multi-Frame is matched with `0010' or `0011', the Network
Terminal CRC Error event is generated. This error event is captured by
the TCRCEI bit and is forwarded to the Performance Monitor.
Various errors will lead to out of synchronization:
3.8.2.2.1
Out Of Basic Frame Synchronization
If there is one or more bit errors in a FAS pattern, a FAS pattern
error will occur. If the NFAS bit position is received as zero, a NFAS error
will occur. Determined by the BIT2C bit, if this bit is `0', 3 consecutive
FAS pattern errors lead to out of Basic frame synchronization; if this bit
is `1', 3 consecutive FAS pattern errors or 3 consecutive NFAS errors
lead to out of Basic frame synchronization. Then if the REFEN bit is `1',
the Frame Processor will start to search for synchronization again. Addi-
tionally, Excessive CRC-4 Error also leads to out of Basic frame syn-
chronization. In this condition, both the REFEN bit being `1' and the
REFCRCE bit being `1' will allow the Frame Processor to search for syn-
chronization again. If the REFEN bit is `0', no error can lead to reframe
except for manually setting. The manual reframe searches from Basic
frame and is executed by a transition from `0' to `1' on the REFR bit. Dur-
ing out of Basic frame synchronization state, the FAS/NFAS Bit/Pattern
Error detection is suspended.
Once resynchronized, if the new-found Basic frame alignment pat-
tern position differs from the previous one, the change of frame align-
ment event is generated. This event is captured by the COFAI bit and is
forwarded to the Performance Monitor.
3.8.2.2.2
Out Of CRC Multi-Frame Synchronization
The conditions introducing out of Basic frame synchronization will
also cause out of CRC Multi-Frame synchronization. During out of CRC
Multi-Frame synchronization state, the FAS/NFAS Bit/Pattern Error
detection, CRC Multi-Frame Alignment Pattern Error detection, CRC-4
Error detection, Excessive CRC-4 Error detection, Far End Block Error
detection, Continuous RAI & FEBE Error detection, Continuous FEBE
Error detection, NT CRC Error detection and NT FEBE Error detection
are suspended.
3.8.2.2.3
Out Of CAS Signaling Multi-Frame Synchronization
The conditions introducing out of Basic frame synchronization will
also cause out of CAS Signaling Multi-Frame synchronization.
In addition, determined by the SMFASC bit and the TS16C bit, if the
CAS Signaling Multi-Frame Alignment Pattern Error occurs or all the
contents in TS16 are zeros, it is out of CAS Signaling Multi-Frame syn-
chronization. Then no matter what the value in the REFEN bit is, the
Frame Processor will search for the CAS Signaling Multi-Frame syn-
chronization again only if the Basic frame is in synchronization. During
out of CAS Signaling Multi-Frame synchronization state, the CAS Sig-
naling Multi-Frame Alignment Pattern Error detection is suspended.
3.8.2.3
Overhead Extraction
3.8.2.3.1
International Bit Extraction
The International bits (Si bits, refer to Table 18) are extracted to the
Si[0:1] bits in the TS0 International / National register. The Si[0:1] bits in
the TS0 International / National register are updated on the boundary of
the associated FAS/NFAS frame and are held during out of Basic frame
state.
3.8.2.3.2
Remote Alarm Indication Bit Extraction
The Remote Alarm Indication bit (A bit, refer to Table 18) is
extracted to the A bit in the TS0 International / National register. The A
bit in the TS0 International / National register is updated on the bound-
ary of the associated NFAS frame and is held during out of Basic frame
state.
3.8.2.3.3
National Bit Extraction
The National bits (Sa bits, refer to Table 18) are extracted to the
Sa[4:8] bits in the TS0 International / National register. The Sa[4:8] bits
in the TS0 International / National register are updated on the boundary
of the associated NFAS frame and are held during out of Basic frame.
3.8.2.3.4
National Bit Codeword Extraction
The five sets of the National Bit codewords (Sa4[1:4] to Sa8[1:4] in
the CRC Sub Multi-Frame, refer to Table 18) are extracted to the corre-
sponding SaX Codeword register. Here the `X' is from 4 through 8. The
National Bit codeword extraction will be set to de-bounce if the SaDEB
bit is set to `1'. Thus, the SaX Codeword registers are updated if the
received National Bit codeword is the same for 2 consecutive CRC Sub
Multi-Frames. Whether de-bounced or not, a change indication will be
set in the SaXI bit (`X' is from 4 through 8) if the corresponding codeword
in the SaX Codeword register differs from the previous one.
The value in the SaX Codeword registers is held during out of CRC
Multi-Frame synchronization state.
3.8.2.3.5
Extra Bit Extraction
The Extra bits (X bits, refer to Figure 11) are extracted to the X[0:2]
bits in the TS16 Spare register. The X[0:2] bits in the TS16 Spare regis-
ter are updated at the first bit of the next CAS Signaling Multi-Frame and
are held during out of CAS Signaling Multi-Frame state.
3.8.2.3.6
Remote Signaling Multi-Frame Alarm Indication Bit
Extraction
The Remote Signaling Multi-Frame Alarm Indication bit (Y bit, refer
to Figure 11) are extracted to the Y bit in the TS16 Spare register. The Y
bit in the TS16 Spare register is updated at the first bit of the next CAS
Signaling Multi-Frame and is held during out of CAS Signaling Multi-
Frame state.
3.8.2.3.7
Sa6 Code Detection Per ETS 300 233
When Basic frame is synchronized, any 12 consecutive Sa6 bits
(MSB is the first received bit) are compared with 0x888, 0xAAA, 0xCCC,
0xEEE and 0xFFF. When CRC Multi-Frame is synchronized, any 3 con-
secutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are com-
IDT82P2284
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pared if the Sa6SYN bit is `1'. If a matched code is detected, the
corresponding indication bit in the Sa6 Code Indication register will be
set.
3.8.2.4
V5.2 Link
The V5.2 link ID signal, i.e., 2 out of 3 sliding Sa7 bits being logic 0,
is detected with the indication in the V52LINKV bit. This detection is dis-
abled when the Basic Frame is out of synchronization.
3.8.2.5
Interrupt Summary
The interrupt sources in this block are summarized in Table 20.
When there are conditions meeting the interrupt sources, the corre-
sponding Status bit will be asserted high. When there is a transition
(from `1' to `0' or from `0' to `1') on the Status bit, the corresponding Sta-
tus Interrupt Indication bit will be set to `1' (If the Status bit does not
exist, the source will cause its Status Interrupt Indication bit to `1'
directly) and the Status Interrupt Indication bit will be cleared by a write
signal. A `1' in the Status Interrupt Indication bit means an interrupt
occurred. The interrupt will be reported by the INT pin if its Status Inter-
rupt Enable bit is `1'.
Table 20: Interrupt Source In E1 Frame Processor
Sources
Status Bit
Interrupt Indication Bit
Interrupt Enable Bit
In CRC to Non-CRC inter-working.
C2NCIWV
C2NCIWI
C2NCIWE
It is out of Basic frame synchronization.
OOFV
OOFI
OOFE
It is out of CRC multi-frame synchronization.
OOCMFV
OOCMFI
OOCMFE
It is out of CAS Signaling multi-frame synchronization.
OOSMFV
OOSMFI
OOSMFE
The new-found Basic frame alignment pattern position differs from the previous one.
-
COFAI
COFAE
FAS/NFAS Bit/Pattern Error occurs.
-
FERI
FERE
CRC Multi-Frame Alignment Pattern Error occurs.
-
CMFERI
CMFERE
CAS Signaling Multi-Frame Alignment Pattern Error occurs.
-
SMFERI
SMFERE
CRC-4 Error occurs.
-
CRCEI
CRCEE
Offline Basic frame search indication.
OOOFV
OOOFI
OOOFE
Far End Block Error occurs.
-
FEBEI
FEBEE
Continuous RAI & FEBE Error occurs.
RAICRCV
RAICRCI
RAICRCE
Continuous FEBE Error occurs.
CFEBEV
CFEBEI
CFEBEE
At the first bit of each CRC Multi-Frame.
-
ICMFPI
ICMFPE
At the first bit of each CRC Sub Multi-Frame.
-
ICSMFPI
ICSMFPE
At the first bit of each CAS Signaling Multi-Frame.
-
ISMFPI
ISMFPE
There is change in the corresponding SaX[1:4] bits. The `X' is from 4 through 8.
-
Sa4I / Sa5I / Sa6I / Sa7I /
Sa8I
Sa4E / Sa5E / Sa6E /
Sa7E / Sa8E
Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords are matched
with 0x888, 0xAAA, 0xCCC, 0xEEE or 0xFFF.
-
Sa6SCI
Sa6SCE
NT FEBE Error occurs.
-
TFEBEI
TFEBEE
NT CRC Error occurs.
-
TCRCEI
TCRCEE
2 out of 3 sliding Sa7 bits are received as logic 0.
V52LINKV
V52LINKI
V52LINKE
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Table 21: Related Bit / Register In Chapter 3.8.2
Bit
Register
E1 Address (Hex)
UNFM
FRMR Mode 0
04D, 14D, 24D, 34D
REFEN
REFCRCE
REFR
CRCEN
FRMR Mode 1
04E, 14E, 24E, 34E
C2NCIWCK
CASEN
WORDERR
CNTNFAS
BIT2C
SMFASC
TS16C
OOFV
FRMR Status
04F, 14F, 24F, 34F
OOCMFV
OOOFV
C2NCIWV
OOSMFV
EXCRCERI
FRMR Interrupt Indication 0
052, 152, 252, 352
C2NCIWI
OOFI
OOCMFI
OOSMFI
OOOFI
OOFE
FRMR Interrupt Control 0
050, 150, 250, 350
OOCMFE
OOOFE
C2NCIWE
OOSMFE
CMFERI
FRMR Interrupt Indication 1
053, 153, 253, 353
FERI
CRCEI
SMFERI
COFAI
ICMFPI
ICSMFPI
ISMFPI
CMFERE
FRMR Interrupt Control 1
051, 151, 251, 351
FERE
CRCEE
SMFERE
COFAE
ICMFPE
ICSMFPE
ISMFPE
RAICRCV
Overhead Error Status
05F, 15F, 25F, 35F
CFEBEV
V52LINKV
FEBEI
Overhead Interrupt Indication
061, 161, 261, 361
TFEBEI
TCRCEI
RAICRCI
CFEBEI
V52LINKI
FEBEE
Overhead Interrupt Control
060, 160, 260, 360
TFEBEE
TCRCEE
RAICRCE
CFEBEE
V52LINKE
Si[0:1]
TS0 International / National
054, 154, 254, 354
A
Sa[4:8]
X[0:2]
TS16 Spare
055, 155, 255, 355
Y
SaX[1:4] (`X' is
from 4 to 8)
Sa4 Codeword ~ Sa8 Codeword
056 ~ 05A, 156 ~ 15A,
256 ~ 25A, 356 ~ 35A
SaXI (`X' is
from 4 to 8)
Sa Codeword Interrupt Indication
05D, 15D, 25D, 35D
Sa6SCI
SaXE (`X' is
from 4 to 8)
Sa Codeword Interrupt Control
05C, 15C, 25C, 35C
SaDEB
Sa6SYN
Sa6SCE
Sa6-8I
Sa6 Codeword Indication
05B, 15B, 25B, 35B
Sa6-AI
Sa6-CI
Sa6-EI
Sa6-FI
Table 21: Related Bit / Register In Chapter 3.8.2 (Continued)
Bit
Register
E1 Address (Hex)
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3.9
PERFORMANCE MONITOR
3.9.1
T1/J1 MODE
Several internal counters are used to count different events for per-
formance monitoring. For different framing format, the counters are used
differently. The overflow of each counter is reflected by an Overflow Indi-
cation Bit, and can trigger an interrupt if the corresponding Overflow
Interrupt Enable Bit is set. This is shown in Table 22.
These internal counters are indirect registers, and can only be
accessed through other direct registers. At one time, only one internal
counter can be accessed. Users should use the LINKSEL[1:0] bits to
select the Link, then use the ADDR[3:0] bits to select one internal
counter. The content of the selected counter is transferred to the
DATA[7:0] bits in the following two ways:
1. Auto-Report: When the AUTOUP bit is `1', the selected counter
transfers its content to the DATA[7:0] bits every one second automati-
cally;
2. Manual-Report: No matter the AUTOUPD bit is `1' or `0', at any
time, when there is a transition from `0' to `1' on the UPDAT bit, the
selected counter will transfer its content to the DATA[7:0] bits.
After the content in the selected coutner is transferred to the
DATA[7:0] bits, all counters belong to the selected Link will be cleared to
`0' as a group and start a new round counting automatically. No error
event is lost during updating.
Table 22: Monitored Events In T1/J1 Mode
Format
Event
Counter
Overflow Interrupt Indication Bit Overflow Interrupt Enable Bit
SF
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
LCV[15:0]
LCVOVI
LCVOVE
F Bit Error
FER[11:0]
FEROVI
FEROVE
The new-found F bit position differs from the previous one
COFA[2:0]
COFAOVI
COFAOVE
Out of SF synchronization
OOF[4:0]
OOFOVI
OOFOVE
PRGD Bit Error
PRGD[15:0]
PRGDOVI
PRGDOVE
ESF
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
LCV[15:0]
LCVOVI
LCVOVE
Frame Alignment Bit Error
FER[11:0]
FEROVI
FEROVE
CRC-6 Error
CRCE[9:0]
CRCOVI
CRCOVE
The new-found F bit position differs from the previous one
COFA[2:0]
COFAOVI
COFAOVE
Out of ESF synchronization
OOF[4:0]
OOFOVI
OOFOVE
PRGD Bit Error
PRGD[15:0]
PRGDOVI
PRGDOVE
T1 DM
(T1 only)
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
LCV[15:0]
LCVOVI
LCVOVE
F Bit Error
FER[11:0]
FEROVI
FEROVE
DDS Pattern Error
DDSE[9:0]
DDSOVI
DDSOVE
The new-found F bit position differs from the previous one
COFA[2:0]
COFAOVI
COFAOVE
Out of T1 DM synchronization
OOF[4:0]
OOFOVI
OOFOVE
PRGD Bit Error
PRGD[15:0]
PRGDOVI
PRGDOVE
SLC-96
(T1 only)
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
LCV[15:0]
LCVOVI
LCVOVE
F Bit Error
FER[11:0]
FEROVI
FEROVE
The new-found F bit position differs from the previous one
COFA[2:0]
COFAOVI
COFAOVE
Out of SLC-96 synchronization
OOF[4:0]
OOFOVI
OOFOVE
PRGD Bit Error
PRGD[15:0]
PRGDOVI
PRGDOVE
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Table 23: Related Bit / Register In Chapter 3.9.1
Bit
Register
T1/J1 Address (Hex)
LCV[15:0]
ID* - LCV Counter Mapping 1 & 0
PMON ID - 09 & 08
FER[11:0]
ID - FER Counter Mapping 1 & 0
PMON ID - 03 & 02
COFA[2:0]
ID - COFA Counter Mapping
PMON ID - 04
OOF[4:0]
ID - OOF Counter Mapping
PMON ID - 05
PRGD[15:0]
ID - PRGD Counter Mapping 1 & 0
PMON ID - 07 & 06
CRCE[9:0]
ID - CRCE Counter Mapping 1 & 0
PMON ID - 01 & 00
DDSE[9:0]
ID - DDSE Counter Mapping 1 & 0
PMON ID - 0B & 0A
LCVOVI
PMON Interrupt 1
0C6, 1C6, 2C6, 3C6
FEROVI
PMON Interrupt 0
0C5, 1C5, 2C5, 3C5
COFAOVI
OOFOVI
PRGDOVI
CRCOVI
DDSOVI
LCVOVE
PMON Interrupt Control 1
0C4, 1C4, 2C4, 3C4
FEROVE
PMON Interrupt Control 0
0C3, 1C3, 2C3, 3C3
COFAOVE
OOFOVE
PRGDOVE
CRCOVE
DDSOVE
LINKSEL[1:0]
PMON Access Port
00E
ADDR[3:0]
DATA[7:0]
PMON Access Data
00F
UPDAT
PMON Control
0C2, 1C2, 2C2, 3C2
AUTOUPD
Note:
*
ID means Indirect Register in the Performance Monitor function block.
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3.9.2
E1 MODE
Several internal counters are used to count different events for per-
formance monitoring. The overflow of each counter is reflected by an
Overflow Indication Bit, and can trigger an interrupt if the corresponding
Overflow Interrupt Enable Bit is set. This is shown in Table 24.
These internal counters are indirect registers, and can only be
accessed through other direct registers. At one time, only one internal
counter can be accessed. Users should use the LINKSEL[1:0] bits to
select the Link, then use the ADDR[3:0] bits to select one internal
counter. The content of the selected counter is transferred to the
DATA[7:0] bits in the following two ways:
1. Auto-Report: When the AUTOUP bit is `1', the selected counter
transfers its content to the DATA[7:0] bits every one second automati-
cally;
2. Manual-Report: No matter the AUTOUPD bit is `1' or `0', at any
time, when there is a transition from `0' to `1' on the UPDAT bit, the
selected counter will transfer its content to the DATA[7:0] bits.
After the content in the selected coutner is transferred to the
DATA[7:0] bits, all counters belong to the selected Link will be cleared to
`0' as a group and start a new round counting automatically. No error
event is lost during updating.
Table 24: Monitored Events In E1 Mode
Event
Counter
Overflow Interrupt
Indication Bit
Overflow Interrupt
Enable Bit
Bipolar Violation (BPV) Error (in AMI decoding) or HDB3 Code Violation (CV) Error (in HDB3 decoding)
LCV[15:0]
LCVOVI
LCVOVE
FAS/NFAS Bit/Pattern Error
FER[11:0]
FEROVI
FEROVE
CRC-4 Error
CRCE[9:0]
CRCOVI
CRCOVE
Far End Block Error
FEBE[9:0]
FEBEOVI
FEBEOVE
The the new-found Basic frame alignment pattern position differs from the previous one
COFA[2:0]
COFAOVI
COFAOVE
Out of Basic frame synchronization
OOF[4:0]
OOFOVI
OOFOVE
PRGD Bit Error
PRGD[15:0]
PRGDOVI
PRGDOVE
NT FEBE Error
TFEBE[9:0]
TFEBEOVI
TFEBEOVE
NT CRC Error
TCRCE[9:0]
TCRCOVI
TCRCOVE
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Table 25: Related Bit / Register In Chapter 3.9.2
Bit
Register
E1 Address (Hex)
LCV[15:0]
ID* - LCV Counter Mapping 1 & 0
PMON ID - 09 & 08
FER[11:0]
ID - FER Counter Mapping 1 & 0
PMON ID - 03 & 02
CRCE[9:0]
ID - CRCE Counter Mapping 1 & 0
PMON ID - 01 & 00
FEBE[9:0]
ID - FEBE Counter Mapping 1 & 0
PMON ID - 0D & 0C
COFA[2:0]
ID - COFA Counter Mapping
PMON ID - 04
OOF[4:0]
ID - OOF Counter Mapping
PMON ID - 05
PRGD[15:0]
ID - PRGD Counter Mapping 1 & 0
PMON ID - 07 & 06
TFEBE[9:0]
ID - TFEBE Counter Mapping 1 & 0
PMON ID - 0F & 0E
TCRCE[9:0]
ID - TCRCE Counter Mapping 1 & 0
PMON ID - 0B & 0A
LCVOVI
PMON Interrupt 1
0C6, 1C6, 2C6, 3C6
FEROVI
PMON Interrupt 0
0C5, 1C5, 2C5, 3C5
CRCOVI
FEBEOVI
COFAOVI
OOFOVI
PRGDOVI
TFEBEOVI
TCRCOVI
LCVOVE
PMON Interrupt Control 1
0C4, 1C4, 2C4, 3C4
FEROVE
PMON Interrupt Control 0
0C3, 1C3, 2C3, 3C3
CRCOVE
FEBEOVE
COFAOVE
OOFOVE
PRGDOVE
TFEBEOVE
TCRCOVE
LINKSEL[1:0]
PMON Access Port
00E
ADDR[3:0]
DATA[7:0]
PMON Access Data
00F
UPDAT
PMON Control
0C2, 1C2, 2C2, 3C2
AUTOUPD
Note:
*
ID means Indirect Register in the Performance Monitor function block.
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3.10
ALARM DETECTOR
3.10.1
T1/J1 MODE
The RED alarm, Yellow alarm and Blue alarm are detected in this
block (refer to Table 26).
The status of the RED alarm, Yellow alarm and Blue alarm are indi-
cated by the corresponding Status bit. Any transition (from `0' to `1' or
from `1' to `0') on the Status bit will set the corresponding Interrupt Indi-
cation bit to `1' and the Interrupt Indication bit will be cleared by writing a
`1'. A `1' in the Interrupt Indication bit means there is an interrupt. The
interrupt will be reported by the INT pin if its Interrupt Enable bit is `1'.
Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria
Declare Condition
Clear Condition
Status Bit Interrupt Indication Bit Interrupt Enable Bit
RED Alarm
(per T1.403,
T1.231)
The out of SF/ESF/T1 DM/SLC-96 syn-
chronization status persists Nx40 ms. Here
`N' is decided by the REDDTH[7:0] bits.
The in SF/ESF/T1 DM/SLC-96 synchro-
nization status persists Mx120 ms. Here
`M' is decided by the REDCTH[7:0] bits.
RED
REDI
REDE
Yellow
Alarm*
T1 SF/
SLC-96
Format
Less than 77 'One's are detected on the Bit
2 of each channel during a 40 ms fixed win-
dow and this status persists for Nx40 ms.
Here `N' is decided by the YELDTH[7:0]
bits.
More than 76 'One's are detected on the
Bit 2 of each channel during a 40 ms
fixed window and this status persists for
Mx40 ms. Here `M' is decided by the
YELCTH[7:0] bits.
YEL
YELI
YELE
T1 ESF
Format
More than 7 `0xFF00' (MSB first) are
detected on the DL bits during a 40 ms
fixed window and this status persists for
Nx40 ms. Here `N' is decided by the
YELDTH[7:0] bits.
Less than 8 `0xFF00' (MSB first) are
detected on the DL bits during a 40 ms
fixed window and this status persists for
Mx40 ms. Here `M' is decided by the
YELCTH[7:0] bits.
YEL
YELI
YELE
T1 DM
Format
Less than 4 'One's are detected on the Y
bit (Bit 6 in each CH 24) during a 40 ms
fixed window and this status persists for
Nx40 ms. Here `N' is decided by the
YELDTH[7:0] bits.
More than 3 'One's are detected on the
Y bit (Bit 6 in each CH 24) during a 40
ms fixed window and this status persists
for Mx40 ms. Here `M' is decided by the
YELCTH[7:0] bits.
YEL
YELI
YELE
J1 SF
Format
Less than 4 zeros are detected on the F-bit
of the 12nd frame during a 40 ms fixed win-
dow and this status persists for Nx40 ms.
Here `N' is decided by the YELDTH[7:0]
bits.
More than 3 zeros are detected on the
F-bit of the 12nd frame during a 40 ms
fixed window and this status persists for
Mx40 ms. Here `M' is decided by the
YELCTH[7:0] bits.
YEL
YELI
YELE
J1 ESF
Format
Less than 3 zeros are detected on the DL
bits during a 40 ms fixed window and this
status persists for Nx40 ms. Here `N' is
decided by the YELDTH[7:0] bits.
More than 2 zeros are detected on the
DL bits during a 40 ms fixed window and
this status persists for Mx40 ms. Here
`M' is decided by the YELCTH[7:0] bits.
YEL
YELI
YELE
Blue Alarm
(per T1.231)
Less than 61 zeros are detected in a 40 ms
fixed window and this status persists for
Nx40 ms. Here `N' is decided by the AIS-
DTH[7:0] bits.
More than 60 zeros are detected in a 40
ms fixed window and this status persists
for Mx40 ms. Here `M' is decided by the
AISCTH[7:0] bits.
AIS
AISI
AISE
Note: * The Yellow Alarm can only be detected when the frame is synchronized.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
43
April 25, 2003
Advance Information
Table 27: Related Bit / Register In Chapter 3.10.1
Bit
Register
T1/J1 Address (Hex)
REDDTH[7:0]
RED Declare Threshold
0BC, 1BC, 2BC, 3BC
REDCTH[7:0]
RED Clear Threshold
0BD, 1BD, 2BD, 3BD
YELDTH[7:0]
Yellow Declare Threshold
0BE,1BE, 2BE, 3BE
YELCTH[7:0]
Yellow Clear Threshold
0BF, 1BF, 2BF, 3BF
AISDTH[7:0]
AIS Declare Threshold
0C0, 1C0, 2C0, 3C0
AISCTH[7:0]
AIS Clear Threshold
0C1, 1C1, 2C1, 3C1
RED
Alarm Status
0B9, 1B9, 2B9, 3B9
YEL
AIS
REDI
Alarm Indication
0BB, 1BB, 2BB, 3BB
YELI
AISI
REDE
Alarm Control
0BA, 1BA, 2BA, 3BA
YELE
AISE
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
44
April 25, 2003
Advance Information
3.10.2
E1 MODE
The Remote alarm, Remote Signaling Multi-Frame alarm, RED
alarm, AIS alarm, AIS in TS16 and LOS in TS16 are detected in this
block.
The Remote Alarm Indication bit is the A bit (refer to Table 18). It is
detected on the base of Basic frame synchronization. The criteria of
Remote alarm detection are defined by the RAIC bit. If the RAIC bit is
`0', the Remote alarm will be declared when 4 consecutive A bits are
received as `1', and the Remote alarm will be cleared when a single A bit
is received as `0'. If the RAIC bit is `1', the Remote alarm will be declared
when a single A bit is received as `1', and the Remote alarm will be
cleared when a single A bit is received as `0'. The Remote alarm status
is reflected by the RAIV bit. Any transition (from `0' to `1' or from `1' to `0')
on the RAIV bit will set the RAII bit to `1' and the RAII bit will be cleared
by writing a `1'. A `1' in the RAII bit means there is an interrupt. The inter-
rupt will be reported by the INT pin if the RAIE bit is `1'.
The Remote Signaling Multi-Frame Alarm Indication bit is the Y bit
(refer to Figure 11). It is detected on the base of CAS Signaling Multi-
Frame synchronization. The Remote Signaling Multi-Frame alarm will be
declared when 3 consecutive Y bits are received as `1', and the Remote
Signaling Multi-Frame alarm will be cleared when a single Y bit is
received as `0'. The Remote Signaling Multi-Frame alarm status is
reflected by the RMAIV bit. Any transition (from `0' to `1' or from `1' to `0')
on the RMAIV bit will set the RMAII bit to `1' and the RMAII bit will be
cleared by writing a `1'. A `1' in the RMAII bit means there is an interrupt.
The interrupt will be reported by the INT pin if the RMAIE bit is `1'.
The criteria of RED alarm detection meet I.431. The RED alarm will
be declared when out of Basic frame synchronization persists for 100
ms, and the RED alarm will be cleared when in Basic frame synchroni-
zation persists for 100 ms. The RED alarm status is reflected by the
RED bit. Any transition (from `0' to `1' or from `1' to `0') on the RED bit will
set the REDI bit to `1' and the REDI bit will be cleared by writing a `1'. A
`1' in the REDI bit means there is an interrupt. The interrupt will be
reported by the INT pin if the REDE bit is `1'.
The AIS alarm is detected whether it is in synchronization or not.
The criteria of AIS alarm are defined by the AISC bit. When the AISC bit
is `0', the criteria meet I.431. The AIS alarm will be declared when less
than 3 zeros are detected in a 512-bit fixed window and it is out of Basic
frame synchronization, and the AIS alarm will be cleared when more
than 2 zeros are detected in a 512-bit fixed window. When the AISC bit
is `1', the criteria meet G.775. The AIS alarm will be declared when less
than 3 zeros are detected in each of 2 consecutive 512-bit fixed win-
dows, and the AIS alarm will be cleared when more than 2 zeros are
detected in each of 2 consecutive 512-bit fixed windows. The AIS alarm
status is reflected by the AIS bit. Any transition (from `0' to `1' or from `1'
to `0') on the AIS bit will set the AISI bit to `1' and the AISI bit will be
cleared by writing a `1'. A `1' in the AISI bit means there is an interrupt.
The interrupt will be reported by the INT pin if the AISE bit is `1'.
The AIS in TS16 is detected on the base of Basic frame synchroni-
zation. The AIS in TS16 will be declared when TS16 contains less than 4
zeros in each of two 16-consecutive-Basic-frame periods. The AIS in
TS16 will be cleared when TS16 contains more than 3 zeros in a 16-
consecutive-Basic-frame period. The AIS in TS16 status is reflected by
the TS16AISV bit. Any transition (from `0' to `1' or from `1' to `0') on the
TS16AISV bit will set the TS16AISI bit to `1' and the TS16AISI bit will be
cleared by writing a `1'. A `1' in the TS16AISI bit means there is an inter-
rupt. The interrupt will be reported by the INT pin if the TS16AISE bit is
`1'.
The LOS in TS16 is detected on the base of Basic frame synchroni-
zation. The LOS in TS16 will be declared when 16 consecutive TS16 are
all received as `0'. The LOS in TS16 will be cleared when 16 consecutive
TS16 are not all received as `0'. The LOS in TS16 status is reflected by
the TS16LOSV bit. Any transition (from `0' to `1' or from `1' to `0') on the
TS16LOSV bit will set the TS16LOSI bit to `1' and the TS16LOSI bit will
be cleared by writing a `1'. A `1' in the TS16LOSI bit means there is an
interrupt. The interrupt will be reported by the INT pin if the TS16LOSE
bit is `1'.
Table 28: Related Bit / Register In Chapter 3.10.2
Bit
Register
E1 Address (Hex)
RAIC
Alarm Criteria Control
0BC, 1BC, 2BC, 3BC
AISC
RAIV
Alarm Status
0B9, 1B9, 2B9, 3B9
RMAIV
RED
AIS
TS16AISV
TS16LOSV
RAII
Alarm Indication
0BB, 1BB, 2BB, 3BB
RMAII
REDI
AISI
TS16AISI
TS16LOSI
RAIE
Alarm Control
0BA, 1BA, 2BA, 3BA
RMAIE
REDE
AISE
TS16AISE
TS16LOSE
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
45
April 25, 2003
Advance Information
3.11
HDLC RECEIVER
The HDLC Receiver extracts the HDLC/SS7 data stream from the
selected position and processes the data according to the selected
mode.
3.11.1
HDLC CHANNEL CONFIGURATION
In T1/J1 mode ESF & T1 DM formats, three HDLC Receivers (#1,
#2 & #3) per link are provided for HDLC extraction from the received
data stream. In T1/J1 mode SF & SLC-96 formats, two HDLC Receivers
(#2 & #3) per link are provided for HDLC extraction. In E1 mode, three
HDLC Receivers (#1, #2 & #3) per link are provided for HDLC extraction.
Except in T1/J1 mode ESF & T1 DM formats, the HDLC channel of
HDLC #1 is fixed in the DL bit (in ESF format) and D bit in CH24 (in T1
DM format) respectively (refer to Table 13 & Table 14), the other HDLC
channels are configured as follows:
1. Set the EVEN bit and/or the ODD bit to select the even and/or
odd frames;
2. Set the TS[4:0] bits to define the channel/timeslot of the
assigned frame;
3. Set the BITEN[7:0] bits to select the bits of the assigned channel/
timeslot.
Then all the functions of the HDLC Receiver will be enabled only if
the corresponding RDLEN bit is set to `1'.
3.11.2
TWO HDLC MODES
Two modes are selected by the RHDLCM bit in the corresponding
HDLC Receiver. The two modes are: HDLC mode (per Q.921) and SS7
mode (per Q.703).
3.11.2.1
HDLC Mode
The structure of a standard HDLC packet consists of the following
parts as shown in Figure 12. Each HDLC packet starts with a 7E (Hex)
opening flag and ends with the same flag. The closing flag may also
serve as the opening flag of the next HDLC packet. Following the open-
ing flag, two-byte address is compared if the address comparison mode
is selected. Before the closing flag, two bytes of CRC-CCITT frame
check sequences (FCS) are provided to check all the HDLC packet
(excluding the opening flag and closing flag).
Figure 12. Standard HDLC Packet
After the stuffed zero (the zero following five consecutive 'One's) is
discarded, the data stream between the opening flag and the FCS is
divided into blocks. Each block (except the last block) has 32 bytes. The
block will be pushed into a FIFO with one-byte overhead until any of the
following invalid packet conditions occurs:
- A packet with error FCS;
Table 29: Related Bit / Register In Chapter 3.11.1
Bit
Register
Address (Hex)
EVEN
RHDLC1 Assignment (E1 only) / RHDLC2 Assignment /
RHDLC3 Assignment
08C, 18C, 28C, 38C (E1 only) / 08D, 18D, 28D, 38D / 08E, 18E, 28E,
38E
ODD
TS[4:0]
BITEN[7:0]
RHDLC1 Bit Select (E1 only) / RHDLC2 Bit Select /
RHDLC3 Bit Select
08F, 18F, 28F, 38F (E1 only) / 090, 190, 290, 390 / 091, 191, 291,
391
RDLEN3
RHDLC Enable Control
08B, 18B, 28B, 38B
RDLEN2
RDLEN1
Flag
one byte
'01111110'
FCS
two bytes
Information
n bytes
Control
one byte
Address
(optional)
low byte
address
one byte
high byte
address
one byte
Flag
one byte
'01111110'
b7
b0
b0
C/R
b7
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
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April 25, 2003
Advance Information
- The data between the opening flag and the closing flag is less
than 5 bytes (including the FCS, excluding the flags);
- The extracted HDLC packet does not consist of an integral num-
ber of octets;
- A 7F (Hex) abort sequence is received;
- Address is not matched if the address comparison is enabled.
(The address comparison mode is selected by the ADRM[1:0] bits. If
high byte address comparison is required, the high byte address posi-
tion (the byte following the opening flag) is compared with the value in
the HA[7:0] bits, or with `0xFC' or `0xFE'. Here the `C/R' bit position is
excluded to compare. If low byte address comparison is required, the
high byte address position is compared with the value in the LA[7:0] bits.
Here the `C/R' bit position is included to compare. If both bytes address
comparison is required, the high byte address position is compared with
the value in the HA[7:0] bits, or with `0xFC' or `0xFE'. Here the `C/R' bit
position is excluded to compare. And the low byte position (the byte fol-
lowing the high byte address position) is compared with the value in the
LA[7:0] bits.
If any of the above conditions is detected, the current block will be
discarded, but the one-byte overhead will still be written into the FIFO.
The overhead consists of the M[2:0] bits and the length indication bits as
shown in Figure 13.
Figure 13. Overhead Indication In The FIFO
The FIFO depth is 128 bytes. The FIFO is accessed by the
DAT[7:0] bits. When the overhead is read from the FIFO, it will be indi-
cated by the PACK bit. When all valid HDLC blocks are pushed into the
FIFO or all the blocks are read from the FIFO, it will be indicated by the
EMP bit.
The interrupt sources in this block are summarized in Table 30.
When there are conditions meeting the interrupt sources, the corre-
sponding Interrupt Indication bit will be set to `1' and the Interrupt Indica-
tion bit will be cleared by writing a `1'. A `1' in the Interrupt Indication bit
means there is an interrupt. The interrupt will be reported by the INT pin
if its Interrupt Enable bit is `1'.
The HDLC Receiver will be reset when there is a transition from `0'
to `1' on the RRST bit. The reset will clear the FIFO, the PACK bit and
the EMP bit.
overhead (one byte)
bit 7
bit 0
M2
M1
M0
Length Indication
M[2:0]:
= 000: A valid short HDLC/SS7 packet is received, i.e., the data stream between the opening flag and the FCS is less than 32 bytes (including
32 bytes).
= 001: The current block is not the last block of the HDLC/SS7 packet.
= 010: The current block is the last block of a valid long (more than 32 bytes) HDLC/SS7 packet.
= 011: Reserved.
= 100: An invalid short HDLC/SS7 packet is received and the current block is discarded.
= 101: The current block is the last block of an invalid long HDLC/SS7 packet and the block is discarded.
= 110: Reserved.
= 111: Reserved.
The Length Indication is valid when the M2 bit is zero: Length Indication = N - 1 (N is the number of byte).
Otherwise, the Length Indication is zero.
Table 30: Interrupt Summarize In HDLC Mode
Sources
Interrupt Indication Bit Interrupt Enable Bit
A block is pushed into the FIFO.
RMBEI
RMBEE
Data is still attempted to write
into the FIFO when the FIFO
has been already full (128
bytes).
OVFLI
OVFLE
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
47
April 25, 2003
Advance Information
3.11.2.2
SS7 Mode
In SS7 mode, there are three kinds of signaling units - MSU, LSSU
and FISU (refer to Figure 14). Their opening flag and closing flag are
both 7E (Hex). The closing flag may also serve as the opening flag of
the next HDLC packet.
Figure 14. Standard SS7 Packet
After the stuffed zero (the zero following five consecutive 'One's) is
discarded, the extracted SS7 data stream is compared with the standard
SS7 packet. If thevalue of the 6-bit length indication is equal to `0', the
SS7 packet is FISU; if it is equal to `1' or `2', the SS7 packet is LSSU; if it
is more than `2', the SS7 packet is MSU.
The data stream between the opening flag and the FCS are divided
into blocks. Each block (except the last block) has 32 bytes. The block
will be pushed into a FIFO with one-byte overhead until any of the fol-
lowing invalid packet conditions occurs:
- A packet with error FCS;
- The data between the opening flag and the closing flag is less
than 5 bytes (including the FCS, excluding the flags);
- The extracted SS7 packet does not consist of an integral number
of octets;
- A 7F (Hex) abort sequence is received;
- If the SS7 packet is FISU, the data between the opening flag and
the closing flag is not 5 bytes (including the FCS, excluding the flags);
- If the SS7 packet is LSSU, the data between the opening flag and
the closing flag is not 6 or 7 bytes (including the FCS, excluding the
flags);
- If the SS7 packet is MSU, the data between the opening flag and
the closing flag is less than 8 bytes or more than 271 bytes (including
the FCS, excluding the flags).
If any of the above conditions is detected, the current block will be
discarded, but the one-byte overhead will still be written into the FIFO.
The overhead consists of the M[2:0] bits and the length indication bits as
shown in Figure 13. In FISU/LSSU, if the FISU/LSSU filter is set by the
FISUFIL/LSSUFIL bit respectively, the current FISU/LSSU will be dis-
carded if it is the same with the previous FISU/LSSU. In this condition,
no data and overhead of the current FISU/LSSU will be written into the
FIFO.
The FIFO depth is 128 bytes. The FIFO is accessed by the
DAT[7:0] bits. When the overhead is read from the FIFO, it will be indi-
cated by the PACK bit. When all valid SS7 blocks are pushed into the
FIFO or all the blocks are read from the FIFO, it will be indicated by the
EMP bit.
The interrupt sources in this block are summarized in the Table 30.
When there are conditions meeting the interrupt sources, the corre-
sponding Interrupt Indication bit will be set to `1' and the Interrupt Indica-
tion bit will be cleared by writing a `1'. A `1' in the Interrupt Indication bit
Flag
one byte
'01111110'
FCS
two bytes
Signaling Field
n bytes (n>1)
Flag
one byte
'01111110'
Service
Information
Octet
one byte
two
bits
Length
Indication
six bits
( > 2 )
Forward
Indication
Bit
one bit
Forward
Sequence
Number
seven
bits
seven
bits
Backward
Indication
Bit
one bit
Backward
Sequence
Number
Flag
one byte
'01111110'
two
bits
Length
Indication
six bits
( = 1 or 2 )
Forward
Indication
Bit
one bit
Forward
Sequence
Number
seven
bits
seven
bits
Backward
Indication
Bit
one bit
Backward
Sequence
Number
Flag
one byte
'01111110'
FCS
two bytes
Status
one or two bytes
Flag
one byte
'01111110'
two
bits
Length
Indication
six bits
( = 0 )
Forward
Indication
Bit
one bit
Forward
Sequence
Number
seven
bits
seven
bits
Backward
Indication
Bit
one bit
Backward
Sequence
Number
Flag
one byte
'01111110'
FCS
two bytes
Message Signaling Unit (MSU)
Link Status Signaling Unit (LSSU)
Fill In Signaling Unit (FISU)
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
48
April 25, 2003
Advance Information
means there is an interrupt. The interrupt will be reported by the INT pin
if its Interrupt Enable bit is `1'.
The HDLC Receiver will be reset when there is a transition from `0'
to `1' on the RRST bit. The reset will clear the FIFO, the PACK bit and
the EMP bit.
Table 31: Related Bit / Register In Chapter 3.11.2
Bit
Register
Address (Hex)
RHDLCM
RHDLC1 Control Register / RHDLC2 Control Register / RHDLC3 Control
Register
092, 192, 292, 392 / 093, 193, 293, 393 / 094, 194, 294, 394
ADRM[1:0]
RRST
FISUFIL
LSSUFIL
HA[7:0]
RHDLC1 High Address / RHDLC2 High Address / RHDLC3 High Address
0A1, 1A1, 2A1, 3A1 / 0A2, 1A2, 2A2, 3A2 / 0A3, 1A3, 2A3, 3A3
LA[7:0]
RHDLC1 Low Address / RHDLC2 Low Address / RHDLC3 Low Address
0A4, 1A4, 2A4, 3A4 / 0A5, 1A5, 2A5, 3A5 / 0A6, 1A6, 2A6, 3A6
DAT[7:0]
RHDLC1 Data / RHDLC2 Data / RHDLC3 Data
098, 198, 298, 398 / 099, 199, 299, 399 / 09A, 19A, 29A, 39A, 49A
PACK
RHDLC1 RFIFO Access Status /
095, 195, 295, 395 / 096, 196, 296, 396 / 097, 197, 297, 397
EMP
RMBEI
RHDLC1 Interrupt Indication / RHDLC2 Interrupt Indication / RHDLC3
Interrupt Indication
09E, 19E, 29E, 39E / 09F, 19F, 29F, 39F / 0A0, 1A0, 2A0, 3A0
OVFLI
RMBEE
RHDLC1 Interrupt Control / RHDLC2 Interrupt Control / RHDLC3 Interrupt
Control
09B, 19B, 29B, 39B / 09C, 19C, 29C, 39C / 09D, 19D, 29D, 39D
OVFLE
IDT82P2284
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April 25, 2003
Advance Information
3.12
BIT-ORIENTED MESSAGE RECEIVER (T1/J1
ONLY)
The Bit-Oriented Message (BOM) can only be received in the ESF
format in T1/J1 mode.
The BOM pattern is `111111110XXXXXX0' which occupies the DL of
the F-bit in the ESF format (refer to Table 13). The six `X's represent the
message. The BOM is declared only when the pattern is matched and
the received message is identical 4 out of 5 consecutive times or 8 out of
10 consecutive times and differs from the previous message. The identi-
fication time is selected by the AVC bit. After a new BOM is declared, the
message is loaded into the BOC[5:0] bits. Every time when the BOC[5:0]
bits are updated, it will be indicated by the BOCI bit. A `1' in the BOCI bit
means there is an interrupt. The interrupt will be reported by the INT pin
if the BOCE bit is `1'.
3.13
INBAND LOOPBACK CODE DETECTOR (T1/J1
ONLY)
The Inband Loopback Code Detector tracks the loopback activate/
deactivate codes only in framed or unframed T1/J1 data stream, and
meets ANSI T1.403 9.3.1.
The received data stream is compared with the target activate/
deactivate code whose length and content are programmed in the
ASEL[1:0]/DSEL[1:0] bits and the ACT[7:0]/DACT[7:0] bits respectively.
In framed mode, the F-bit is selected by the IBCDIDLE bit to compare
with the target activate/deactivate code or not. In unframed mode, all
193 bits are compared with the target activate/deactivate code.
After four consecutive correct activate/deactivate codes are found
in the received data stream, the Inband Loopback Code Detector keeps
on monitoring the bit error, i.e., the bit differs from the target activate/
deactivate code. If in more than 126 consecutive 39.8ms fixed periods,
less than 600 bit errors are detected in each 39.8ms, the activate/deacti-
vate code is detected and the corresponding LBA/LBD bit will indicate it.
Once more than 600 bit errors are detected in a 39.8ms fixed period, the
activate/deactivate code is out of synchronization and the corresponding
LBA/LBD bit will be cleared. However, even if the F-bit is compared,
whether it is matched or not, the result will not cause bit errors, that is,
the comparison result of the F-bit is discarded.
Any transition (from `0' to `1' or from `1' to `0') on the LBA/LBD bit
will set the LBAI/LBDI bit, which means there is an interrupt. The inter-
rupt will be reported by the INT pin if the corresponding LBAE/LBDE bit
is set to `1'.
Table 32: Related Bit / Register In Chapter 3.12
Bit
Register
T1/J1 Address (Hex)
AVC
BOC Control
081, 181, 281, 381
BOCE
BOC[5:0]
RBOC Code
083, 183, 283, 383
BOCI
BOC Interrupt Indication
082, 182, 282, 382
Table 33: Related Bit / Register In Chapter 3.13
Bit
Register
T1/J1 Address (Hex)
ASEL[1:0]
IBCD Detector Configuration
076, 176, 276, 376
DSEL[1:0]
IBCDIDLE
ACT[7:0]
IBCD Activate Code
078, 178, 278, 378
DACT[7:0]
IBCD Deactivate Code
079, 179, 279, 379
LBA
IBCD Detector Status
077, 177, 277, 377
LBD
LBAI
IBCD Interrupt Indication
07B, 17B, 27B, 37B
LBDI
LBAE
IBCD Interrupt Control
07A, 17A, 27A, 37A
LBDE
IDT82P2284
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Advance Information
3.14
ELASTIC STORE BUFFER
In Receive Clock Slave mode and Receive Multiplexed mode, a 2-
basic-frame depth Elastic Store Buffer is used to synchronize the incom-
ing frames to the (Multiplexed) Receive Side System Clock derived from
the RSCKn/MRSCK pin, and to the (Multiplexed) Receive Side System
Frame Pulse derived from the RSFSn/MRSFS pin. A write pointer is
used to write the data to the Elastic Store Buffer, while a read pointer is
used to read the data from the Elastic Store Buffer.
When the average frequency of the incoming data is greater than
the average frequency of the (Multiplexed) Receive Side System Clock
(RSCKn/MRSCK), the write pointer will be faster than the read pointer
and the Elastic Store Buffer will be filled. Until there is less than or equal
to 2 bytes between the write pointer and the read pointer, a frame will be
deleted after its prior frame is read. When the read pointer crosses the
frame boundary, a controlled slip will occur with a `1' indicated in the
SLIPD bit.
When the average frequency of the incoming data is less than the
average frequency of the RSCKn/MRSCK, the write pointer will be
slower than the read pointer and the Elastic Store Buffer will be empty.
Until there is less than or equal to 2 bytes between the write pointer and
the read pointer, the frame will be repeated after it is read. When the
read pointer crosses the next frame boundary, a controlled slip will occur
with a `0' indicated in the SLIPD bit.
When the slip occurs, the SLIPI bit will indicate it. An interrupt on
the INT pin will occur if the SLIPE bit is `1'.
In Receive Clock Slave mode and Receive Multiplexed mode, if it is
out of synchronization, the trunk code programmed in the TRK-
CODE[7:0] bits will be set to replace the data if the TRKEN bit is set to
`1'.
In Receive Clock Master mode, the Elastic Store Buffer is
bypassed unless the device is in the Payload Loopback diagnosis mode
(refer to Chapter 3.27.2.2 Payload Loopback).
3.15
RECEIVE CAS/RBS BUFFER
The Receive CAS/RBS Buffer extracts the signaling bits from the
received data stream.
3.15.1
T1/J1 MODE
In SF/ESF/SLC-96 format, the signaling bits are located in the Bit 8
of Frame 6n (n = 1,2 in SF format; 1
n 4 in ESF format; 1 n 12 in
SLC-96 format) (refer to Table 12, Table 13 and Table 15 respectively).
The signaling codewords (AB or ABCD) are clocked out on the RSIGn/
MRSIGA(MRSIGB) pins. They are in the lower nibble of the channel with
its corresponding data serializing on the RSDn/MRSDA(MRSIGB) pins
(as shown in Figure 15).
When the EXTRACT bit is set to `1', the signaling bits in its corre-
sponding channel are extracted to the A,B,C,D bits in the Extracted Sig-
naling Data/Extract Enable register. In SF format, the C,D bits in the
register are the repetition of the signaling bits A,B. The data in the
A,B,C,D bits in the Extracted Signaling Data/Extract Enable register are
the data to be output on the RSIGn/MRSIGA(MRSIGB) pins. However,
in T1-DM format, there is no signaling bits.
Signaling de-bounce will be executed when the DEB bit is set to `1'.
Thus, the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register are updated only if 2 consecutive received AB/ABCD codewords
of the same channel are identical.
Signaling freezing is performed automatically when it is out of
frame synchronization or when slips occurs in the Elastic Store Buffer. It
is also performed when the FREEZE bit is set to `1'. The signaling freez-
ing freezes the signaling data in the A,B,C,D bits in the Extracted Signal-
ing Data/Extract Enable register as the previous valid value.
In the ESF and SLC-96 format, if the SIGF bit is set to `0', the
extracted signaling bits are in 4 states signaling, i.e., the signaling bits
on Framer 6 & 18 of a signaling multi-frame are recognized as `A' and
the signaling bits on Framer 12 & 24 are recognized as `B'. Only the sig-
naling bits A & B will be saved in the Extracted Signaling Data/Extract
Enable register, and the C & D bits in the Extracted Signaling Data/
Extract Enable register are Don't-Care. If the SIGF bit is set to `1', the
extracted signaling bits are in 16 states signaling, i.e., four signaling bits
A, B, C & D are all saved in the Extracted Signaling Data/Extract Enable
register.
Each time the extracted signaling bits stored in the Extracted Sig-
naling Data/Extract Enable register are changed, it is captured by the
corresponding COSI[X] bit (1
X 24). When the SIGE bit is set to `1',
any one of the COSI[X] bits being `1' will generate an interrupt and will
be reported by the INT pin.
The EXTRACT bit and the A,B,C,D bits are in the indirect registers
of the Receive CAS/RBS Buffer. They are accessed by specifying the
address in the ADDRESS[6:0] bits. Whether the data is read from or
written into the specified indirect register is determined by the RWN bit
and the data is in the D[7:0] bits. The access status is indicated in the
BUSY bit. Refer to Chapter 4.5 Indirect Register Access Scheme for
details about the indirect registers write/read access.
Table 34: Related Bit / Register In Chapter 3.14
Bit
Register
Address (Hex)
SLIPD
ELST Configuration
07C, 17C, 27C, 37C
SLIPE
TRKEN
SLIPI
ELST Interrupt Indication
07D, 17D, 27D, 37D
TRKCODE[7:0]
ELST Trunk Code
07E, 17E, 27E, 37E
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
51
April 25, 2003
Advance Information
Figure 15. Signaling Output In T1/J1 Mode
3.15.2
E1 MODE
In Signaling Multi-Frame, the signaling bits are located in TS16
(refer to Figure 11), which are Channel Associated Signalings (CAS).
The signaling codewords (ABCD) are clocked out on the RSIGn/
MRSIGA(MRSIGB) pins. They are in the lower nibble of the timeslot with
its corresponding data serializing on the RSDn/MRSDA(MRSDB) pins
(as shown in Figure 16).
When the EXTRACT bit is set to `1', the signaling bits in its corre-
sponding timeslot are extracted to the A,B,C,D bits in the Extracted Sig-
naling Data/Extract Enable register. The data in the A,B,C,D bits in the
register are the data to be output on the RSIGn/MRSIGA(MRSIGB) pins.
The bits corresponding to TS0 and TS16 output on the RSIGn/
MRSIGA(MRSIGB) pins are Don't-Care.
Signaling de-bounce will be executed when the DEB bit is set to `1'.
Thus, the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register are updated only if 2 consecutive received ABCD codewords of
the same timeslot are identical.
Signaling freezing is performed automatically when it is out of Basic
frame synchronization, out of Signaling multi-frame synchronization or
slips occurs in the Elastic Store Buffer. It is also performed when the
FREEZE bit is set to `1'. The signaling freezing freezes the signaling
data in the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register as the previous valid value.
Each time the extracted signaling bits in the A,B,C,D bits in the
Extracted Signaling Data/Extract Enable register are changed, it is cap-
tured by the corresponding COSI[X] bit (1
X 30). When the SIGE bit
is set to `1', any one of the COSI[X] bits being `1' will generate an inter-
rupt and will be reported by the INT pin.
The EXTRACT bit and the A,B,C,D bits are in the indirect registers
of the Receive CAS/RBS Buffer. They are accessed by specifying the
address in the ADDRESS[6:0] bits. Whether the data is read from or
written into the specified indirect register is determined by the RWN bit
and the data is in the D[7:0] bits. The access status is indicated in the
BUSY bit. Refer to Chapter 4.5 Indirect Register Access Scheme for
details about the indirect registers write/read access.
Figure 16. Signaling Output In E1 Mode
Channel 24
Channel 1
Channel 2
Channel 24
A B C D
RSDn/
MRSDA(MRSDB)
RSIGn/
MRSIGA(MRSIGB)
F
1
2
3
4
5
6
7
8
Channel 1
F
F-bit
F-bit
1
2
3
4
5
6
7
8 1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
A B C D
A B C D
A B C D
A B C D
1
2
3
4
5
6
78
TS31
TS0
TS1
TS15
TS16
TS17
TS31
TS0
1
2
3
4
5
6
78 1
2
3
4
5
6
78
1
2
3
4
5
6
78 1
2
3
4
5
6
78 1
2
3
4
5
6
78
1
2
3
4
5
6
78 1
2
3
4
5
6
78
ABCD
ABCD
ABCD
ABCD
ABCD
RSDn/
MRSDA(MRSDB)
RSIGn/
MRSIGA(MRSIGB)
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
52
April 25, 2003
Advance Information
Table 35: Related Bit / Register In Chapter 3.15
Bit
Register
Address (Hex)
EXTRACT
ID* - Extracted Signaling Data/Extract Enable
RCRB ID - 01~18 (for T1/J1) / 01~0F & 11~1F (for E1)
A,B,C,D
DEB
RCRB Configuration
0D2, 1D2, 2D2, 3D2
FREEZE
SIGF (T1/J1 only)
SIGE
COSI[X] (1
X 24 in T1/J1) (1 X 30
in E1)
RCRB State Change Indication 3 (E1 only) & RCRB State
Change Indication 2 ~ 0
0D9, 1D9, 2D9, 3D9 (E1 only) & 0D8, 1D8, 2D8, 3D8 &
0D7, 1D7, 2D7, 3D7 & 0D6, 1D6, 2D6, 3D6
ADDRESS[6:0]
RCRB Access Control
0D4, 1D4, 2D4, 3D4
RWN
D[7:0]
RCRB Access Data
0D5, 1D5, 2D5, 3D5
BUSY
RCRB Access Status
0D3, 1D3, 2D3, 3D3
Note:
*
ID means Indirect Register in the Receive CAS/RBS Buffer function block.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
53
April 25, 2003
Advance Information
3.16
RECEIVE PAYLOAD CONTROL
Different test patterns can be inserted in the received data stream
or the received data stream can be extracted to the PRBS Generator/
Detector for test in this block.
To enable all the functions in the Receive Payload Control, the
PCCE bit must be set to `1'.
The following methods can be executed on the data to be output on
the RSDn/MRSDA(MRSDB) pins on a per-channel/per-TS basis or on a
global basis of the corresponding link (the methods are arranged from
the highest to the lowest in priority):
- When the TESTEN bit is enabled and the PRBSDIR bit is `0', the
received data will be extracted to the PRBS Generator/Detector. The
received data can be extracted in unframed mode, in 8-bit-based mode
or in 7-bit-based mode. This selection is made by the PRBSMODE[1:0]
bits. In unframed mode, all the received data stream is extracted and the
per-channel/per-TS configuration in the TEST bit is ignored. In 8-bit-
based mode or in 7-bit-based mode, the received data will only be
extracted on the channel/timeslot configured by the TEST bit. Refer to
Chapter 3.27.1 PRBS Generator / Detector for details.
- Selected by the GSUBST[2:0] bits, the data of all channels/
timeslots of the corresponding link will be replaced by the data trunk
code set in the DTRK[7:0] bits, or the milliwatt pattern defined in the
Table 36 and Table 37. When the GSUBST[2:0] bits are set to `000',
these replacements will be performed on a per-channel/per-TS basis by
setting the SUBST[2:0] bits in the corresponding channel/timeslot.
- When the SIGFIX bit is set to `1', the signaling bits (ABCD) will be
fixed to the value set in the POL bit. This function is only supported in
the SF, ESF and SLC-96 formats in T1/J1 mode.
- Invert the most significant bit, the even bits and/or the odd bits by
setting the SINV, OINV, EINV bits.
- When the TESTEN bit is enabled and the PRBSDIR bit is `1', the
received data will be replaced by the test pattern generated from the
PRBS Generator/Detector. The received data can be replaced in
unframed mode, in 8-bit-based mode or in 7-bit-based mode. This selec-
tion is made by the PRBSMODE[1:0] bits. In unframed mode, all the
received data stream is replaced and the per-channel/per-TS configura-
tion in the TEST bit is ignored. In 8-bit-based mode or in 7-bit-based
mode, the received data will only be replaced on the channel/timeslot
configured by the TEST bit. Refer to Chapter 3.27.1 PRBS Generator /
Detector for details.
The following methods can be executed on the signaling bits to be
output on the RSIGn/MRSIGA(MRSIGB) pins on a per-channel/per-TS
basis or on a global basis of the corresponding link (the methods are
arranged from the highest to the lowest in priority):
- Selected by the ABXX bit, the signaling bits can be valid in the
upper 2-bit positions of the lower nibble of each channel or in the lower
nibble of each channel. The other bits of the channel are Don't Care
conditions. This function is only supported in T1/J1 mode ESF/SLC-96
format.
- Enabled by the SIGSNAP bit, the signaling snapshot will be exe-
cuted. The signaling snapshot means that the signaling bits of the first
basic frame are locked and output as the signaling bits of the current
whole multi-frame. This function is not supported in T1 DM format.
- Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
channels/timeslots of the corresponding link will be replaced by the sig-
naling trunk conditioning code in the A,B,C,D bits. When the GSTRKEN
bit is `0', the replacement will be performed on a per-channel/per-TS
basis by setting the STRKEN bit in the corresponding channel/timeslot.
The indirect registers of the Receive Payload Control are accessed
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
Table 36: A-Law Digital Milliwatt Pattern
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Byte 1
0
0
1
1
0
1
0
0
Byte 2
0
0
1
0
0
0
0
1
Byte 3
0
0
1
0
0
0
0
1
Byte 4
0
0
1
1
0
1
0
0
Byte 5
1
0
1
1
0
1
0
0
Byte 6
1
0
1
0
0
0
0
1
Byte 7
1
0
1
0
0
0
0
1
Byte 8
1
0
1
1
0
1
0
0
Table 37: -Law Digital Milliwatt Pattern
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Byte 1
0
0
0
1
1
1
1
0
Byte 2
0
0
0
0
1
0
1
1
Byte 3
0
0
0
0
1
0
1
1
Byte 4
0
0
0
1
1
1
1
0
Byte 5
1
0
0
1
1
1
1
0
Byte 6
1
0
0
0
1
0
1
1
Byte 7
1
0
0
0
1
0
1
1
Byte 8
1
0
0
1
1
1
1
0
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
54
April 25, 2003
Advance Information
read from or written into the specified indirect register is determined by
the RWN bit and the data is in the D[7:0] bits. The access status is indi-
cated in the BUSY bit. Refer to Chapter 4.5 Indirect Register Access
Scheme for details about the indirect registers write/read access.
Table 38: Related Bit / Register In Chapter 3.16
Bit
Register
Address (Hex)
PCCE
RPLC Control Enable
0D1, 1D1, 2D1, 3D1
SIGFIX (T1/J1 only)
POL (T1/J1 only)
ABXX (T1/J1 only)
TESTEN
TPLC / RPLC / PRGD Test Configuration
0C7, 1C7, 2C7, 3C7
PRBSDIR
PRBSMODE[1:0]
TEST
ID * - Signaling Trunk Conditioning Code
RPLC ID - 41~58 (for T1/J1) / 41~4F & 51~5F (for E1)
STRKEN
A,B,C,D
GSUBST[2:0]
RPLC Configuration
0D0, 1D0, 2D0, 3D0
SIGSNAP
GSTRKEN
DTRK[7:0]
ID - Data Trunk Conditioning Code
RPLC ID - 21~38 (for T1/J1) / 20~3F (for E1)
SUBST[2:0]
ID - Channel Control (for T1/J1) / Timeslot Control (for E1)
RPLC ID - 01~18 (for T1/J1) / 00~1F (for E1)
SINV
OINV
EINV
ADDRESS[6:0]
RPLC Access Control
0CE, 1CE, 2CE, 3CE
RWN
D[7:0]
RPLC Access Data
0CF, 1CF, 2CF, 3CF
BUSY
RPLC Access Status
0CD, 1CD, 2CD, 3CD
Note:
*
ID means Indirect Register in the Receive Payload Control function block.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
55
April 25, 2003
Advance Information
3.17
RECEIVE SYSTEM INTERFACE
The Receive System Interface determines how to output the
received data stream to the system backplane. The data from the four
links can be aligned with each other or be output independently. The tim-
ing clocks and framing pulses can be provided by the system backplane
or obtained from the far end. The Receive System Interface supports
various configurations to meet various requirements in different applica-
tions.
3.17.1
T1/J1 MODE
In T1/J1 mode, the Receive System Interface can be set in Non-
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the RSDn pin is used to output the received data from each link at the bit
rate of 1.544 Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Mul-
tiplexed Mode, the received data from the four links is converted to
2.048 Mb/s format and byte interleaved to form one high speed data
stream and output on the MRSDA1 (MRSDB1) pins at the bit rate of
8.192 Mb/s.
In the Non-multiplexed Mode, if the receive system interface and
the receive line side are timed to a same clock source, the Receive Sys-
tem Interface is in Receive Clock Master mode. If the receive system
interface and the receive line side are timed to different clock sources,
the Receive System Interface is in Receive Clock Slave mode.
In the Receive Clock Master mode, if RSCKn outputs pulses during
the entire T1/J1 frame, the Receive System Interface is in Receive Clock
Master Full T1/J1 mode. If only the clocks aligned to the selected chan-
nels are output on RSCKn, the Receive System Interface is in Receive
Clock Master Fractional T1/J1 mode.
In the Receive Clock Slave mode, the backplane data rate may be
equal to 1.544 Mb/s (i.e., the line data rate) or 2.048 Mb/s. If the back-
plane data rate is 2.048 Mb/s, the Receive System Interface is in T1/J1
mode E1 rate and the received data stream (1.544 Mb/s) should be
mapped per 3 kinds of schemes.
In the Receive Multiplexed mode, since the received data from the
four links should be converted to 2.048 Mb/s format first and then multi-
plexed to 8.192 Mb/s, there are still 3 kinds of schemes to be selected.
Table 39 summarizes how to set the Receive System Interface of
each link into various operating modes and the pins' direction of the
Receive System Interface in different operating modes.
3.17.1.1
Receive Clock Master Mode
In the Receive Clock Master mode, each link uses its own timing
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are per-
channel aligned with the data on the RSDn pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCKn. The active edge of the RSCKn used to
update the pulse on the RSFSn is determined by the FE bit. The active
edge of the RSCKn used to update the data on the RSDn and RSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFSn is ahead.
In the Receive Clock Master mode, the RSFSn can indicate each
F-bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. In SF
format, the RSFSn can also indicate every second F-bit or the first F-bit
of every second SF multi-frame. All the indications are selected by the
CMFS bit and the ALTIFS bit. The active polarity of the RSFSn is
selected by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full T1/J1 mode and Receive Clock Master Fractional T1/
J1 mode.
3.17.1.1.1
Receive Clock Master Full T1/J1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked out by the RSCKn.
Table 39: Operating Modes Selection In T1/J1 Receive Path
RMUX RMODE
G56K, GAP /
FBITGAP
MAP[1:0]
2
Operating Mode
Receive System Interface Pin
Input
Output
0
0
00 / 0
X
Receive Clock Master Full T1/J1
X
RSCKn, RSFSn,
RSDn, RSIGn
not all 0s
1
Receive Clock Master Fractional T1/J1
1
X
00
Receive Clock Slave - T1/J1 Rate
RSCKn, RSFSn
RSDn, RSIGn
01
Receive Clock Slave - T1/J1 Mode E1 Rate per G.802
10
Receive Clock Slave - T1/J1 Mode E1 Rate per One Filler Every Four CHs
11
Receive Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
1
X
X
01
Receive Multiplexed - T1/J1 Mode E1 Rate per G.802
MRSCK, MRSFS
MRSDA[1],
MRSIGA[1]
(MRSDB[1],
MRSIGB[1])
3
10
Receive Multiplexed - T1/J1 Mode E1 Rate per One Filler Every Four CHs
11
Receive Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to `1'.
2. The MAP[1:0] bits can not be set to `00' in the Receive Multiplexed mode.
3. In Receive Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided. Their functions are the same. One is the backup for the other.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
56
April 25, 2003
Advance Information
3.17.1.1.2
Receive Clock Master Fractional T1/J1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
gapped 1.544 MHz clock (no clock signal during the selected position).
The RSCKn is gapped during the F-bit if the FBITGAP bit is set to
`1'. The RSCKn is also gapped during the channels or the Bit 8 duration
by selecting the G56K & GAP bits in the Receive Payload Control. The
data in the corresponding gapped duration is a don't care condition.
3.17.1.2
Receive Clock Slave Mode
In the Receive Clock Slave mode, the system data rate can be
1.544 Mb/s or 2.048 Mb/s. If the system data rate is 1.544 Mb/s, it works
in T1/J1 mode. If the system data rate is 2.048 Mb/s, the received data
stream (1.544 Mb/s) should be mapped to the same rate as the system
side, that is, to work in T1/J1 mode E1 rate. Three kinds of schemes are
provided by selecting the MAP[1:0] bits:
1. T1/J1 Mode E1 Rate per G.802 (refer to Figure 17): Channel 1 to
Channel 15 of Frame N from the device are converted into TS1 to TS15
of Frame N on the system side; Channel 16 to Channel 24 of Frame N
from the device are converted into TS17 to TS25 of Frame N on the sys-
tem side. The F-bit of Frame N from the device is converted into the first
bit of TS26 of Frame (N-1) on the system side. TS0, TS16, TS27~TS31
and the other 7 bits in TS26 on the system side are all filled with `0's and
they are meaningless.
2. T1/J1 Mode E1 Rate per One Filler Every Four CHs (refer to
Figure 18): One dummy byte is inserted on the system side before 3
bytes of Frame N from the device are converted. This process repeats 8
times and the conversion of Frame N of 1.544 Mb/s data rate to 2.048
Mb/s data rate is completed. However, the F-bit of Frame N of the 1.544
Mb/s data rate is inserted as the 8th bit of Frame N of the 2.048 Mb/s
data rate. The dummy bytes are filled with all `0's and they are meaning-
less.
3. T1/J1 Mode E1 Rate per Continuous CHs (refer to Figure 19):
Channel 1 to Channel 24 of Frame N from the device are converted into
TS1 to TS24 of Frame N on the system side. The F-bit of Frame N from
the device is converted into the 8th bit of Frame N on the system side.
The first 7 bits and TS25 to TS31 on the system side are all filled with
`0's and they are meaningless.
Figure 17. T1/J1 To E1 Format Mapping - G.802 Mode
Figure 18. T1/J1 To E1 Format Mapping - One Filler Every Four Channels Mode
1.544
Mb/s
2.048
Mb/s
CH1
CH2
CH14
F
CH15
CH16
CH17
CH23
CH24
CH1
CH2
F
CH23
TS0
TS2
TS1
TS14 TS15 TS16 TS17 TS18
TS24 TS25
TS26 TS27~TS31
TS0
TS1
the 1st bit
filler
filler
filler
filler
filler
1.544
Mb/s
2.048
Mb/s
CH1
CH2
CH3
F
CH4
CH5
CH6
CH22 CH23 CH24
CH1
F
CH2
TS0
TS2
TS1
TS4
TS5
TS6
TS7
TS8
TS28 TS29 TS30 TS31
TS1
TS0
the 8th bit
CH7
TS3
TS9
the 8th bit
filler
filler
filler
filler
filler
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
57
April 25, 2003
Advance Information
Figure 19. T1/J1 To E1 Format Mapping - Continuous Channels Mode
In the Receive Clock Slave mode, the timing signal on the RSCKn
pin and the framing pulse on the RSFSn pin to output the data on the
RSDn pin are provided by the system side. When the RSLVCK bit is set
to `0', each link uses its own RSCKn and RSFSn; when the RSLVCK bit
is set to `1' and all four links are in the Receive Clock Slave mode, the
four links use the RSCK[1] and RSFS[1] to output the data. The signal-
ing bits on the RSIGn pin are per-channel aligned with the data on the
RSDn pin.
In the Receive Clock Slave mode, the data on the system interface
is clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The data rate of the system side is 1.544 Mb/s
or 2.048 Mb/s. When it is 2.048 Mb/s, the RSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
MHz) or double the data rate (4.096 MHz). If all four links use the
RSCK[1] and RSFS[1] to output the data, the CMS bit of the four links
should be set to the same value. If the speed of the RSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to update the data on the
RSDn and RSIGn pins. The pulse on the RSFSn pin is always sampled
on its first active edge.
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125
s, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is `1'.
3.17.1.3
Receive Multiplexed Mode
In the Receive Multiplexed mode, since the received data from the
four links should be mapped to 2.048 Mb/s format first, the 3 kinds of
schemes should be selected by the MAP[1:0] bits. The mapping per
G.802, per One Filler Every Four CHs and per Continuous CHs are the
same as the description in Chapter 3.17.1.2 Receive Clock Slave Mode.
In the Receive Multiplexed mode, a multiplexed bus is used to out-
put the data from all four links. The data of Link 1 to Link 4 is byte-inter-
leaved output on the multiplexed bus 1. When the data from the four
links is output on one multiplexed bus, the sequence of the data is
arranged by setting the channel offset. The data from different links on
one multiplexed bus must be shifted at a different channel offset to avoid
data mixing.
In the Receive Multiplexed mode, the timing signal on the MRSCK
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to all four links. The signaling bits on the MRSIGA
(MRSIGB) pin are per-channel aligned with the corresponding data on
the MRSDA (MRSDB) pin.
In the Receive Multiplexed mode, the data on the system interface
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSDA (MRSDB)
and MRSIGA (MRSIGB) is determined by the DE bit. The FE bit and the
DE bit of the four links should be set to the same value respectively. If
the FE bit and the DE bit are not equal, the pulse on the MRSFS is
ahead. The MRSCK can be selected by the CMS bit to be the same rate
as the data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the four links should be set to the same
value. If the speed of the MRSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) pins. The pulse on the MRSFS pin is always sam-
pled on its first active edge.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
four links should be set to the same value. If the pulse on the MRSFS
pin is not an integer multiple of 125
s, this detection will be indicated by
the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be
reported by the INT pin when the RCOFAI bit is `1'.
3.17.1.4
Offset
Bit offset and channel offset are both supported in all the operating
modes. The offset is between the framing pulse on RSFSn/MRSFS pin
and the start of the corresponding frame output on the RSDn/
MRSDA(MRSDB) pin. The signaling bits on the RSIGn/
1.544
Mb/s
2.048
Mb/s
CH1
CH2
CH3
F
CH23
CH1
CH2
CH24
TS0
TS2
TS1
TS23
TS24
TS0
TS1
TS2
TS24
the 8th bit
CH24
TS3
TS25~TS31
the 8th bit
F
F CH1
filler
filler
filler
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MRSIGA(MRSIGB) pin are always per-channel aligned with the data on
the RSDn/MRSDA(MRSDB) pin.
Figure 20 to Figure 23 show the base line without offset.
Figure 20. No Offset When FE = 1 & DE = 1 In Receive Path
Figure 21. No Offset When FE = 0 & DE = 0 In Receive Path
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
Receive Clock Slave mode / Receive Multiplexed mode:
Receive Clock Master mode:
Bit 1 of CH1 / TS0
Bit 2
Bit 2
Bit 1 of CH1 / TS0
FE = 1, DE = 1
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
Bit 1 of CH1 / TS0
Bit 2
Bit 2
Bit 1 of CH1 / TS0
FE = 0, DE = 0
Receive Clock Slave mode / Receive Multiplexed mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
Receive Clock Master mode:
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
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April 25, 2003
Advance Information
Figure 22. No Offset When FE = 0 & DE = 1 In Receive Path
Figure 23. No Offset When FE = 1 & DE = 0 In Receive Path
The bit offset and channel offset are configured when the
BOFF[2:0] bits and the TSOFF[6:0] bits are not `0' respectively.
When the CMS bit is `0' and the BOFF[2:0] bits are set, the start of
the corresponding frame output on the RSDn/MRSDA(MRSDB) pin will
delay `N' clock cycles to the framing pulse on the RSFSn/MRSFS pin.
(Here `N' is defined by the BOFF[2:0] bits.) When the CMS bit is `0' and
the TSOFF[6:0] bits are set, the start of the corresponding frame output
on the RSDn/MRSDA(MRSDB) pin will delay `8 x M' clock cycles to the
framing pulse on the RSFSn/MRSFS pin. (Here `M' is defined by the
TSOFF[6:0].)
When the CMS bit is `1' (i.e., in double clock mode) and the
BOFF[2:0] bits are set, the start of the corresponding frame output on
the RSDn/MRSDA(MRSDB) pin will delay `2 x N' clock cycles to the
framing pulse on the RSFSn/MRSFS pin. (Here `N' is defined by the
BOFF[2:0] bits.) When the CMS bit is `1' (i.e., in double clock mode) and
the TSOFF[6:0] bits are set, the start of the corresponding frame output
on the RSDn/MRSDA(MRSDB) pin will delay `16 x M' clock cycles to the
framing pulse on the RSFSn/MRSFS pin. (Here `M' is defined by the
TSOFF[6:0].)
In Non-multiplexed mode, the channel offset can be configured
from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the
channel offset can be configured from 0 to 127 channels (0 & 127 are
included).
3.17.1.5
Output On RSDn/MRSDA(MRSDB) & RSIGn/
MRSIGA(MRSIGB)
The output on the RSDn/MRSDA(MRSDB) and the RSIGn/
MRSIGA(MRSIGB) pins can be configured by the TRI bit of the corre-
sponding link to be in high impedance state or to output the processed
data stream.
Bit 1 of CH1 / TS0
Bit 2
Bit 2
Bit 1 of CH1 / TS0
FE = 0, DE = 1
Receive Clock Slave mode / Receive Multiplexed mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
Receive Clock Master mode:
Bit 2
Bit 1 of CH1 / TS0
FE = 1, DE = 0
Bit 1 of CH1 / TS0
Bit 2
Receive Clock Slave mode / Receive Multiplexed mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
Receive Clock Master mode:
IDT82P2284
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Advance Information
3.17.2
E1 MODE
In E1 mode, the Receive System Interface can be set in Non-multi-
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
RSDn pin is used to output the received data from each link at the bit
rate of 2.048 Mb/s. While in the Multiplexed Mode, the received data
from the four links is byte interleaved to form one high speed data
stream and output on the MRSDA1 (MRSDB1) pins at the bit rate of
8.192 Mb/s.
In the Non-multiplexed Mode, if the receive system interface and
the receive line side are timed to a same clock source, the Receive Sys-
tem Interface is in Receive Clock Master mode. If the receive system
interface and the receive line side are timed to different clock sources,
the Receive System Interface is in Receive Clock Slave mode.
In the Receive Clock Master mode, if RSCKn outputs pulses during
the entire E1 frame, the Receive System Interface is in Receive Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on RSCKn, the Receive System Interface is in Receive Clock
Master Fractional E1 mode.
Table 40 summarizes how to set the receive system interface of
each link into various operating modes and the pins' direction of the
receive system interface in different operating modes.
3.17.2.1
Receive Clock Master Mode
In the Receive Clock Master mode, each link uses its own timing
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are per-
timeslot aligned with the data on the RSDn pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCKn. The active edge of the RSCKn used to
update the pulse on the RSFSn is determined by the FE bit. The active
edge of the RSCKn used to update the data on the RSDn and RSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFSn is ahead.
In the Receive Clock Master mode, the RSFSn can indicate the
Basic frame, CRC Multi-frame, Signaling Multi-frame, or both the CRC
Multi-frame and Signaling Multi-frame, or the TS1 and TS 16 overhead.
All the indications are selected by the OHD bit, the SMFS bit and the
CMFS bit. The active polarity of the RSFSn is selected by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full E1 mode and Receive Clock Master Fractional E1
mode.
3.17.2.1.1
Receive Clock Master Full E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame is clocked out by the RSCKn.
3.17.2.1.2
Receive Clock Master Fractional E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
The RSCKn is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Receive Payload Control. The data
in the corresponding gapped duration is a don't care condition.
3.17.2.2
Receive Clock Slave Mode
In the Receive Clock Slave mode, the timing signal on the RSCKn
pin and framing pulse on the RSFSn pin to output the data on the RSDn
pin are provided by the system side. When the RSLVCK bit is set to `0',
each link uses its own RSCKn and RSFSn; when the RSLVCK bit is set
to `1' and all four links are in the Receive Clock Slave mode, the four
links use the RSCK[1] and RSFS[1] to output the data. The signaling bits
on the RSIGn pin are per-timeslot aligned with the data on the RSDn
pin.
In the Receive Clock Slave mode, the data on the system interface
is clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The speed of the RSCKn can be selected by
the CMS bit to be the same rate as the data rate on the system side
(2.048 MHz) or double the data rate (4.096 MHz). If all four links use the
RSCK[1] and RSFS[1] to output the data, the CMS bit of the four links
should be set to the same value. If the speed of the RSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to update the data on the
Table 40: Operating Modes Selection In E1 Receive Path
RMUX RMODE G56K, GAP
Operating Mode
Receive System Interface Pin
Input
Output
0
0
00
Receive Clock Master Full E1
X
RSCKn, RSFSn, RSDn, RSIGn
not both 0s
1
Receive Clock Master Fractional E1
1
X
Receive Clock Slave
RSCKn, RSFSn
RSDn, RSIGn
1
X
X
Receive Multiplexed
MRSCK, MRSFS
MRSDA[1], MRSIGA[1] (MRSDB[1], MRSIGB[1])
2
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to `1'.
2. In Receive Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided. Their functions are the same. One is the backup for the other.
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
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April 25, 2003
Advance Information
RSDn and RSIGn pins. The pulse on the RSFSn pin is always sampled
on its first active edge.
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125
s, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is `1'.
3.17.2.3
Receive Multiplexed Mode
In the Receive Multiplexed mode, one multiplexed bus is used to
output the data from all four links. The data of Link 1 to Link 4 is byte-
interleaved output on the multiplexed bus 1. When the data from the four
links is output on one multiplexed bus, the sequence of the data is
arranged by setting the timeslot offset. The data from different links on
one multiplexed bus must be shifted at a different timeslot offset to avoid
data mixing.
In the Receive Multiplexed mode, the timing signal on the MRSCK
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to all four links. The signaling bits on the MRSIGA
(MRSIGB) pin are per-timeslot aligned with the corresponding data on
the MRSDA (MRSDB) pin.
In the Receive Multiplexed mode, the data on the system interface
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSDA (MRSDB)
and MRSIGA (MRSIGB) is determined by the DE bit. The FE bit and the
DE bit of the four links should be set to the same value respectively. If
the FE bit and the DE bit are not equal, the pulse on the MRSFS is
ahead. The MRSCK can be selected by the CMS bit to be the same rate
as the data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the four links should be set to the same
value. If the speed of the MRSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) pins. The pulse on the MRSFS pin is always sam-
pled on its first active edge.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
four links should be set to the same value. If the pulse on the MRSFS
pin is not an integer multiple of 125
s, this detection will be indicated by
the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be
reported by the INT pin when the RCOFAI bit is `1'.
3.17.2.4
Offset
Except that in the Receive Master mode, when the OHD bit, the
SMFS bit and the CMFS bit are set to TS1 and TS16 overhead indica-
tion, the bit offset and timeslot offset are both supported in all the other
conditions. The offset is between the framing pulse on RSFSn/MRSFS
pin and the start of the corresponding frame output on the RSDn/
MRSDA(MRSDB) pin. The signaling bits on the RSIGn/
MRSIGA(MRSIGB) pin are always per-timeslot aligned with the data on
the RSDn/MRSDA(MRSDB) pin.
Refer to Chapter 3.17.1.4 Offset for the base line without offset in
different operating modes and the configuration of the offset.
In Non-multiplexed mode, the timeslot offset can be configured
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
3.17.2.5
Output On RSDn/MRSDA(MRSDB) & RSIGn/
MRSIGA(MRSIGB)
The output on the RSDn/MRSDA(MRSDB) and the RSIGn/
MRSIGA(MRSIGB) pins can be configured by the TRI bit of the corre-
sponding link to be in high impedance state or to output the processed
data stream.
Table 41: Related Bit / Register In Chapter 3.17
Bit
Register
Address (Hex)
RMUX
Backplane Global Configuration
010
RSLVCK
RMODE
RBIF Mode
047, 147, 247, 347
MAP[1:0] (T1/J1
only)
G56K
ID * - Channel Control (for T1/
J1) / Timeslot Control (for E1)
RPLC ID - 01~18 (for
T1/J1) / 00~1F (for E1)
GAP
FBITGAP (T1/J1
only)
RBIF Operation
046, 146, 246, 346
FE
DE
CMS
TRI
PCCE
RPLC Control Enable
0D1, 1D1, 2D1, 3D1
CMFS
RBIF Frame Pulse
048, 148, 248, 348
ALTIFS (T1/J1 only)
FSINV
OHD (E1 only)
SMFS (E1 only)
EDGE
RBIF Bit Offset
04A, 14A, 24A, 34A
BOFF[2:0]
RCOFAI
RTSFS Change Indication
04BH, 14B, 24B, 34B
RCOFAE
RTSFS Interrupt Control
04C, 14C, 24C, 34C
TSOFF[6:0]
RBIT TS Offset
049, 149, 249, 349
Note:
*
ID means Indirect Register in the Receive Payload Control function block.
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Advance Information
3.18
TRANSMIT SYSTEM INTERFACE
The Transmit System Interface determines how to input the data to
the device. The data input to the four links can be aligned with each
other or input independently. The timing clocks and framing pulses can
be provided by the system backplane or obtained from the processed
data of each link. The Transmit System Interface supports various con-
figurations to meet various requirements in different applications.
3.18.1
T1/J1 MODE
In T1/J1 mode, the Transmit System Interface can be set in Non-
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the TSDn pin is used to input the data to each link at the bit rate of 1.544
Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed
Mode, the data is byte-interleaved from one high speed data stream and
inputs on the MTSDA1 (MTSDB1) pins at the bit rate of 8.192 Mb/s. The
demultiplexed data input to the four links is 2.048 Mb/s on the system
side and converted into 1.544 Mb/s format to the device.
In the Non-multiplexed mode, if the transmit system interface and
the transmit line side are timed to a same clock source, the Transmit
System Interface is in Transmit Clock Master mode. If the transmit sys-
tem interface and the transmit line side are timed to different clock
sources, the Transmit System Interface is in Transmit Clock Slave
mode.
In the Transmit Clock Master mode, if TSCKn outputs pulses during
the entire T1/J1 frame, the Transmit System Interface is in Transmit
Clock Master Full T1/J1 mode. If only the clocks aligned to the selected
channels are output on TSCKn, the Transmit System Interface is in
Transmit Clock Master Fractional T1/J1 mode.
In the Transmit Clock Slave mode, the backplane data rate may be
equal to 1.544 Mb/s (i.e., the line data rate) or 2.048 Mb/s. If the back-
plane data rate is 2.048 Mb/s, the Transmit System Interface is in T1/J1
mode E1 rate and the data to be transmitted should be mapped to 1.544
Mb/s per 3 kinds of schemes.
In the Transmit Multiplexed mode, since the demultiplexed data
rate on the system side (2.048 Mb/s) should be mapped to the data rate
in the line side (1.544 Mb/s), there are still 3 kinds of schemes to be
selected.
Table 42 summarizes how to set the transmit system interface of
each link into various operating modes and the pins' direction of the
transmit system interface in different operating modes.
3.18.1.1
Transmit Clock Master Mode
In the Transmit Clock Master mode, each link uses its own timing
signal on the TSCKn pin and framing pulse on the TSFSn pin to input
the data on each TSDn pin. The signaling bits on the TSIGn pin are per-
channel aligned with the data on the TSDn pin.
In the Transmit Clock Master mode, the data on the system inter-
face is clocked by the TSCKn. The active edge of the TSCKn used to
update the pulse on the TSFSn is determined by the FE bit. The active
edge of the TSCKn used to sample the data on the TSDn and TSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFSn is ahead.
In the Transmit Clock Master mode, the TSFSn can indicate each
F-bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFSn is selected by the FSINV bit.
The Transmit Clock Master mode includes two sub-modes: Trans-
mit Clock Master Full T1/J1 mode and Transmit Clock Master Fractional
T1/J1 mode.
Table 42: Operating Modes Selection In T1/J1 Transmit Path
TMUX TMODE
G56K, GAP /
FBITGAP
MAP[1:0]
2
Operating Mode
Transmit System Interface Pin
Input
Output
0
0
00 / 0
X
Transmit Clock Master Full T1/J1
TSDn, TSIGn
TSCKn, TSFSn
not all 0s
1
Transmit Clock Master Fractional T1/J1
1
X
00
Transmit Clock Slave - T1/J1 Rate
TSDn, TSIGn, TSCKn, TSFSn
X
01
Transmit Clock Slave - T1/J1 Mode E1 Rate per G.802
10
Transmit Clock Slave - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
11
Transmit Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
1
X
X
01
Transmit Multiplexed - T1/J1 Mode E1 Rate per G.802
MTSCK, MTSFS, MTSDA[1],
MTSIGA[1] (MTSDB[1],
MTSIGB[1])
3
X
10
Transmit Multiplexed - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
11
Transmit Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to `1'.
2. The MAP[1:0] bits can not be set to `00' in the Transmit Multiplexed mode.
3. In Transmit Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided for one multiplexed bus. Their functions are the same. One is the backup for the
other. One set is selected by the MTSDA bit when used.
IDT82P2284
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Advance Information
3.18.1.1.1
Transmit Clock Master Full T1/J1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked in by the TSCKn.
3.18.1.1.2
Transmit Clock Master Fractional T1/J1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
gapped 1.544 MHz clock (no clock signal during the selected channel).
The TSCKn is gapped during the F-bit if the FBITGAP bit is set to
`1'. The TSCKn is also gapped during the channels or the Bit 8 duration
by selecting the G56K & GAP bits in the Transmit Payload Control. The
data in the corresponding gapped duration is a Don't Care condition.
3.18.1.2
Transmit Clock Slave Mode
In the Transmit Clock Slave mode, the system data rate can be
1.544 Mb/s or 2.048 Mb/s. If the system data rate is 1.544 Mb/s, it works
in T1/J1 mode. If the system data rate is 2.048 Mb/s, the data stream to
be transmitted should be mapped to 1.544 Mb/s, that is, to work in T1/J1
mode E1 rate. Three kinds of schemes are provided by selecting the
MAP[1:0] bits:
1. T1/J1 Mode E1 Rate per G.802 (refer to Figure 24): TS1 to TS15
of Frame N on the system side are converted into Channel 1 to Channel
15 of Frame N to the device; TS17 to TS25 of Frame N on the system
side are converted into Channel 16 to Channel 24 of Frame N to the
device. The first bit of TS26 of Frame (N-1) on the system side is con-
verted into the F-bit of Frame N to the device. TS0, TS16, TS27~TS31
and the other 7 bits in TS26 on the system side are all discarded.
2. T1/J1 Mode E1 Rate per One Filler Every Four CHs (refer to
Figure 25): The 8th bit of Frame N on the system side is converted to the
F-bit of the Frame N to the device. Then one byte of the system side is
discarded after the previous three bytes are converted into the device.
This process repeats 8 times and the conversion of one frame is com-
pleted. Then the process goes on.
3. T1/J1 Mode E1 Rate per Continuous CHs (refer to Figure 26):
TS1 to TS24 of Frame N on the system side are converted into Channel
1 to Channel 24 of Frame N to the device. The 8th bit of Frame N on the
system side is converted into the F-bit of Frame N to the device. The first
7 bits and TS25 to TS31 on the system side are all discarded.
Figure 24. E1 To T1/J1 Format Mapping - G.802 Mode
Figure 25. E1 To T1/J1 Format Mapping - One Filler Every Four Channels Mode
1.544
Mb/s
2.048
Mb/s
CH1
CH2
CH14
F
CH15
CH16
CH17
CH23
CH24
CH1
CH2
F
CH23
TS0
TS2
TS1
TS14 TS15 TS16 TS17 TS18
TS24 TS25
TS26 TS27~TS31
TS0
TS1
the 1st bit
discarded
discarded
discardeddiscarded discarded
1.544
Mb/s
2.048
Mb/s
CH1
CH2
CH3
F
CH4
CH5
CH6
CH22 CH23 CH24
CH1
F
CH2
TS0
TS2
TS1
TS4
TS5
TS6
TS7
TS8
TS28 TS29 TS30 TS31
TS1
TS0
the 8th bit
CH7
TS3
TS9
the 8th bit
discarded
discarded
discarded
discarded
discarded
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Figure 26. E1 To T1/J1 Format Mapping - Continuous Channels Mode
In the Transmit Clock Slave mode, the timing signal on the TSCKn
pin and the framing pulse on the TSFSn pin to input the data on the
TSDn pin are provided by the system side. When the TSLVCK bit is set
to `0', each link uses its own TSCKn and TSFSn; when the TSLVCK bit
is set to `1' and all four links are in the Transmit Clock Slave mode, the
four links use the TSCK[1] and TSFS[1] to input the data. The signaling
bits on the TSIGn pin are per-channel aligned with the data on the TSDn
pin.
In the Transmit Clock Slave mode, the data on the system interface
is clocked by the TSCKn. The active edge of the TSCKn used to sample
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead. The data rate of the system side is 1.544 Mb/s
or 2.048 Mb/s. When it is 2.048 Mb/s, the TSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
MHz) or double the data rate (4.096 MHz). If all four links use the
TSCK[1] and TSFS[1] to input the data, the CMS bit of the four links
should be set to the same value. If the speed of the TSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to sample the data on the
TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled
on its first active edge.
In the Transmit Clock Slave mode, the TSFSn can indicate each F-
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFSn is selected by the FSINV bit. If the pulse on the TSFSn pin is not
an integer multiple of 125
s, this detection will be indicated by the
TCOFAI bit. If the TCOFAE bit is enabled, an interrupt will be reported by
the INT pin when the TCOFAI bit is `1'.
3.18.1.3
Transmit Multiplexed Mode
In the Transmit Multiplexed mode, since the demultiplexed data
rate on the system side (2.048 Mb/s) should be mapped to the data rate
in the line side (1.544 Mb/s), 3 kinds of schemes should be selected by
the MAP[1:0] bits. The schemes per G.802, per One Filler Every Four
CHs and per Continuous CHs are the same as the description in
Chapter 3.18.1.2 Transmit Clock Slave Mode.
In the Transmit Multiplexed mode, one multiplexed bus is used to
transmit the data to all four links. The data of Link 1 to Link 4 is byte-
interleaved input from the multiplexed bus 1. When the data on the mul-
tiplexed bus is input to four links, the sequence of the data is arranged
by setting the channel offset. The data to different links from one multi-
plexed bus must be shifted at a different channel offset to avoid data
mixing.
In the Transmit Multiplexed mode, the timing signal on the MTSCK
pin and the framing pulse on the MTSFS pin are provided by the system
side and common to all four links. The signaling bits on the MTSIGA
(MTSIGB) pin are per-channel aligned with the corresponding data on
the MTSDA (MTSDB) pin.
In the Transmit Multiplexed mode, the data on the system interface
is clocked by the MTSCK. The active edge of the MTSCK used to sam-
ple the pulse on the MTSFS is determined by the FE bit. The active
edge of the MTSCK used to sample the data on the MTSDA (MTSDB)
and MTSIGA (MTSIGB) is determined by the DE bit. The FE bit and the
DE bit of the four links should be set to the same value respectively. If
the FE bit and the DE bit are not equal, the pulse on the MTSFS is
ahead. The MTSCK can be selected by the CMS bit to be the same rate
as the data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the four links should be set to the same
value. If the speed of the MTSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to sample the data on the MTSDA (MTSDB) and
MTSIGA (MTSIGB) pins. The pulse on the MTSFS pin is always sam-
pled on its first active edge.
In the Transmit Multiplexed mode, the MTSFS can indicate each F-
bit of the first link or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-
frame of the first link. The indications are selected by the FSTYP bit. The
active polarity of the MTSFS is selected by the FSINV bit. The FSTYP
bit and the FSINV bit of the four links should be set to the same value. If
the pulse on the MTSFS pin is not an integer multiple of 125
s, this
detection will be indicated by the TCOFAI bit. If the TCOFAE bit is
enabled, an interrupt will be reported by the INT pin when the TCOFAI
bit is `1'.
1.544
Mb/s
2.048
Mb/s
CH1
CH2
CH3
F
CH23
CH1
CH2
CH24
TS0
TS2
TS1
TS23
TS24
TS0
TS1
TS2
TS24
the 8th bit
CH24
TS3
TS25~TS31
the 8th bit
F
F CH1
discarded
discarded
discarded
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3.18.1.4
Offset
Bit offset and channel offset are both supported in all the operating
modes. The offset is between the framing pulse on the TSFSn/MTSFS
pin and the start of the corresponding frame input on the TSDn/
MTSDA(MTSDB) pin. The signaling bits on the TSIGn/
MTSIGA(MTSIGB) pin are always per-channel aligned with the data on
the TSDn/MTSDA(MTSDB) pin.
Figure 27 to Figure 30 show the base line without offset.
Figure 27. No Offset When FE = 1 & DE = 1 In Transmit Path
Figure 28. No Offset When FE = 0 & DE = 0 In Transmit Path
Bit 2
Bit 2
Bit 1 of CH1 / TS0
Bit 1 of CH1 / TS0
FE = 1, DE = 1
Transmit Clock Slave mode / Transmit Multiplexed mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
Bit 2
Bit 2
Bit 1 of CH1 / TS0
Bit 1 of CH1 / TS0
FE = 0, DE = 0
Transmit Clock Slave mode / Transmit Multiplexed mode:
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
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Figure 29. No Offset When FE = 0 & DE = 1 In Transmit Path
Figure 30. No Offset When FE = 1 & DE = 0 In Transmit Path
The bit offset and channel offset are configured when the
BOFF[2:0] bits and the TSOFF[6:0] bits are not `0' respectively.
When the CMS bit is `0' and the BOFF[2:0] bits are set, the start of
the corresponding frame input on the TSDn/MTSDA(MTSDB) pin will
delay `N' clock cycles to the framing pulse on the TSFSn/MTSFS pin.
(Here `N' is defined by the BOFF[2:0] bits.) When the CMS bit is `0' and
the TSOFF[6:0] bits are set, the start of the corresponding frame input
on the TSDn/MTSDA(MTSDB) pin will delay `8 x M' clock cycles to the
framing pulse on the TSFSn/MTSFS pin. (Here `M' is defined by the
TSOFF[6:0].)
When the CMS bit is `1' (i.e., in double clock mode) and the
BOFF[2:0] bits are set, the start of the corresponding frame input on the
TSDn/MTSDA(MTSDB) pin will delay `2 x N' clock cycles to the framing
pulse on the TSFSn/MTSFS pin. (Here `N' is defined by the BOFF[2:0]
bits.) When the CMS bit is `1' (i.e., in double clock mode) and the
TSOFF[6:0] bits are set, the start of the corresponding frame input on
the TSDn/MTSDA(MTSDB) pin will delay `16 x M' clock cycles to the
framing pulse on the TSFSn/MTSFS pin. (Here `M' is defined by the
TSOFF[6:0].)
In Non-multiplexed mode, the channel offset can be configured
from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the
channel offset can be configured from 0 to 127 channels (0 & 127 are
included).
Bit 2
Bit 1 of CH1 / TS0
FE = 0, DE = 1
Bit 2
Bit 1 of CH1 / TS0
Transmit Clock Slave mode / Transmit Multiplexed mode:
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
Bit 2
Bit 2
Bit 1 of CH1 / TS0
Bit 1 of CH1 / TS0
FE = 1, DE = 0
Transmit Clock Slave mode / Transmit Multiplexed mode:
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
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Advance Information
3.18.2
E1 MODE
In E1 mode, the Transmit System Interface can be set in Non-multi-
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
TSDn pin is used to input the data to each link at the bit rate of 2.048
Mb/s. While in the Multiplexed Mode, the data is byte interleaved from
one high speed data stream and inputs on the MTSDA1 (MTSDB1) pins
at the bit rate of 8.192 Mb/s.
In the Non-multiplexed mode, if the transmit system interface and
the transmit line side are timed to a same clock source, the Transmit
System Interface is in Transmit Clock Master mode. If the transmit sys-
tem interface and the transmit line side are timed to different clock
sources, the Transmit System Interface is in Transmit Clock Slave
mode.
In the Transmit Clock Master mode, if TSCKn outputs pulses during
the entire E1 frame, the Transmit System Interface is in Transmit Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on TSCKn, the Transmit System Interface is in Transmit
Clock Master Fractional E1 mode.
Table 43 summarizes how to set the transmit system interface of
each link into various operating modes and the pins' direction of the
transmit system interface in different operating modes.
3.18.2.1
Transmit Clock Master Mode
In the Transmit Clock Master mode, each link uses its own timing
signal on the TSCKn pin and framing pulse on the TSFSn pin to input
the data on each TSDn pin. The signaling bits on the TSIGn pin are per-
timeslot aligned with the data on the TSDn pin.
In the Transmit Clock Master mode, the data on the system inter-
face is clocked by the TSCKn. The active edge of the TSCKn used to
update the pulse on the TSFSn is determined by the FE bit. The active
edge of the TSCKn used to sample the data on the TSDn and TSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFSn is ahead.
In the Transmit Clock Master mode, the TSFSn can indicate the
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indica-
tions are selected by the FSTYP bit. The active polarity of the TSFSn is
selected by the FSINV bit.
The Transmit Clock Master mode includes two sub-modes: Trans-
mit Clock Master Full E1 mode and Transmit Clock Master Fractional E1
mode.
3.18.2.1.1
Transmit Clock Master Full E1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame are clocked in by the TSCKn.
3.18.2.1.2
Transmit Clock Master Fractional E1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
The TSCKn is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Transmit Payload Control. The
data in the corresponding gapped duration is a don't care condition.
3.18.2.2
Transmit Clock Slave Mode
In the Transmit Clock Slave mode, the timing signal on the TSCKn
pin and the framing pulse on the TSFSn pin to input the data on the
TSDn pin are provided by the system side. When the TSLVCK bit is set
to `0', each link uses its own TSCKn and TSFSn; when the TSLVCK bit
is set to `1' and all four links are in the Transmit Clock Slave mode, the
four links use the TSCK[1] and TSFS[1] to input the data. The signaling
bits on the TSIGn pin are per-timeslot aligned with the data on the TSDn
pin.
In the Transmit Clock Slave mode, the data on the system interface
is clocked by the TSCKn. The active edge of the TSCKn used to sample
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead. The speed of the TSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
Mb/s) or double the data rate (4.096 Mb/s). If all four links use the
TSCK[1] and TSFS[1] to input the data, the CMS bit of the four links
should be set to the same value. If the speed of the TSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
Table 43: Operating Modes Selection In E1 Transmit Path
TMUX
TMODE
G56K, GAP
Operating Mode
Transmit System Interface Pin
Input
Output
0
0
00
Transmit Clock Master Full E1
TSDn, TSIGn
TSCKn, TSFSn
not both 0s
1
Transmit Clock Master Fractional E1
1
X
Transmit Clock Slave
TSCKn, TSFSn, TSDn, TSIGn
X
1
X
X
Transmit Multiplexed
MTSCK, MTSFS, MTSDA[1],
MTSIGA[1] (MTSDB[1], MTSIGB[1])
2
X
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to `1'.
2. In Transmit Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided for one multiplexed bus. Their functions are the same. One is the backup for the
other. One set is selected by the MTSDA bit when used.
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the EDGE bit determines the active edge to sample the data on the
TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled
on its first active edge.
In the Transmit Clock Slave mode, the TSFSn can indicate the
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indica-
tions are selected by the FSTYP bit. The active polarity of the TSFSn is
selected by the FSINV bit. If the pulse on the TSFSn pin is not an integer
multiple of 125
s, this detection will be indicated by the TCOFAI bit. If
the TCOFAE bit is enabled, an interrupt will be reported by the INT pin
when the TCOFAI bit is `1'.
3.18.2.3
Transmit Multiplexed Mode
In the Transmit Multiplexed mode, one multiplexed bus is used to
transmit the data to all four links. The data of Link 1 to Link 4 is byte-
interleaved input from the multiplexed bus 1. When the data on the mul-
tiplexed bus is input to four links, the sequence of the data is arranged
by setting the timeslot offset. The data to different links from one multi-
plexed bus must be shifted at a different timeslot offset to avoid data
mixing.
In the Transmit Multiplexed mode, the timing signal on the MTSCK
pin and the framing pulse on the MTSFS pin are provided by the system
side and common to all four links. The signaling bits on the MTSIGA
(MTSIGB) pin are per-timeslot aligned with the corresponding data on
the MTSDA (MTSDB) pin.
In the Transmit Multiplexed mode, the data on the system interface
is clocked by the MTSCK. The active edge of the MTSCK used to sam-
ple the pulse on the MTSFS is determined by the FE bit. The active
edge of the MTSCK used to sample the data on the MTSDA (MTSDB)
and MTSIGA (MTSIGB) is determined by the DE bit. The FE bit and the
DE bit of the four links should be set to the same value respectively. If
the FE bit and the DE bit are not equal, the pulse on the MTSFS is
ahead. The MTSCK can be selected by the CMS bit to be the same rate
as the data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the four links should be set to the same
value. If the speed of the MTSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to sample the data on the MTSDA (MTSDB) and
MTSIGA (MTSIGB) pins. The pulse on the MTSFS pin is always sam-
pled on its first active edge.
In the Transmit Multiplexed mode, the MTSFS can indicate the
Basic frame, CRC Multi-frame and/or Signaling Multi-frame of the first
link. The indications are selected by the FSTYP bit. The active polarity of
the MTSFS is selected by the FSINV bit. The FSTYP bit and the FSINV
bit of the four links should be set to the same value. If the pulse on the
MTSFS pin is not an integer multiple of 125
s, this detection will be
indicated by the TCOFAI bit. If the TCOFAE bit is enabled, an interrupt
will be reported by the INT pin when the TCOFAI bit is `1'.
3.18.2.4
Offset
Bit offset and timeslot offset are both supported in all the operating
modes. The offset is between the framing pulse on the TSFSn/MTSFS
pin and the start of the corresponding frame input on the TSDn/
MTSDA(MTSDB) pin. The signaling bits on the TSIGn/
MTSIGA(MTSIGB) pin are always per-timeslot aligned with the data on
the TSDn/MTSDA(MTSDB) pin.
Refer to Chapter 3.18.1.4 Offset for the base line without offset in
different operating modes and the configuration of the offset.
In Non-multiplexed mode, the timeslot offset can be configured
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
Table 44: Related Bit / Register In Chapter 3.18
Bit
Register
Address (Hex)
TMUX
Backplane Global Configuration
010
MTSDA
TSLVCK
TMODE
TBIF Operating Mode
043, 143, 243, 343
MAP[1:0]
(T1/J1 only)
G56K
ID * - Channel Control (for T1/J1) /
Timeslot Control (for E1)
TPLC ID * - 01~18 (for
T1/J1) / 00~1F (for E1)
GAP
PCCE
TPLC Control Enable
0CC, 1CC, 2CC, 3CC
FBITGAP
(T1/J1 only)
TBIF Option Register
042, 142, 242, 342
FE
DE
FSTYP
FSINV
CMS
EDGE
TBIF Bit Offset
045, 145, 245, 345
BOFF[2:0]
TCOFAI
RTSFS Change Indication
04B, 14B, 24B, 34B
TCOFAE
RTSFS Interrupt Control
04C, 14C, 24C, 34C
TSOFF[6:0]
TBIF TS Offset
044, 144, 244, 344
Note:
*
ID means Indirect Register in the Transmit Payload Control function block.
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Advance Information
3.19
TRANSMIT PAYLOAD CONTROL
Different test patterns can be inserted in the data stream to be
transmitted or the data stream to be transmitted can be extracted to the
PRBS Generator/Detector for test in this block.
To enable all the functions in the Transmit Payload Control, the
PCCE bit must be set to `1'.
The following methods can be executed on the data input from the
TSDn/MTSDA (MTSDB) pins on a per-channel/per-TS basis or on a glo-
bal basis of the corresponding link (the methods are arranged from the
highest to the lowest in priority):
- When the TESTEN bit is enabled and the PRBSDIR bit is `1', the
data to be transmitted will be extracted to the PRBS Generator/Detector.
The data to be transmitted can be extracted in unframed mode, in 8-bit-
based mode or in 7-bit-based mode. This selection is made by the PRB-
SMODE[1:0] bits. In unframed mode, all the data stream to be transmit-
ted is extracted and the per-channel/per-TS configuration in the TEST
bit is ignored. In 8-bit-based mode or in 7-bit-based mode, the data will
only be extracted on the channel/timeslot configured by the TEST bit.
Refer to Chapter 3.27.1 PRBS Generator / Detector for details.
- Configured by the ZCS[2:0] bits, four types of Zero Code Sup-
pression can be selected to implement to the data of all the channels of
the corresponding link. This function is only supported in T1/J1 mode.
- Selected by the GSUBST[2:0] bits, the data of all channels/
timeslots of the corresponding link will be replaced by the trunk code set
in the DTRK[7:0] bits, the milliwatt pattern defined in Table 38 and
Table 39, or the payload loopback data from the Elastic Store Buffer
(refer to Chapter 3.27.2.2 Payload Loopback). When the GSUBST[2:0]
bits are set to `000', these replacements will be performed on a per-
channel/per-TS basis by setting the SUBST[2:0] bits in the correspond-
ing channel/timeslot.
- Controlled by the SIGINS bit, the signaling bits input from the
TSIGn/MTSIGA (MTSIGB) pins (after processed by the signaling trunk
conditioning replacement and/or valid signaling bits selection) can be
inserted into its signaling bit position of the data stream to be transmit-
ted.
- Invert the most significant bit, the even bits and/or the odd bits by
setting the SINV, OINV, EINV bits.
- When the TESTEN bit is enabled and the PRBSDIR bit is `0', the
data to be transmitted will be replaced by the test pattern generated
from the PRBS Generator/Detector. The data to be transmitted can be
replaced in unframed mode, in 8-bit-based mode or in 7-bit-based
mode. This selection is made by the PRBSMODE[1:0] bits. In unframed
mode, all the data stream to be transmitted is replaced and the per-
channel/per-TS configuration in the TEST bit is ignored. In 8-bit-based
mode or in 7-bit-based mode, the data will only be replaced on the chan-
nel/timeslot configured by the TEST bit. Refer to Chapter 3.27.1 PRBS
Generator / Detector for details.
The following methods can be executed on the signaling bits input
from the TSIGn/MTSIGA (MTSIGB) pins on a per-channel/per-TS basis
or on a global basis of the corresponding link (the methods are arranged
from the highest to the lowest in priority):
- Selected by the ABXX bit, the signaling bits can be valid in the
upper 2-bit positions of the lower nibble of each channel or in the lower
nibble of each channel. The other bits of the channel are Don't Care
conditions. This function is only supported in T1/J1 mode ESF/SLC-96
format.
- Enabled by the SIGSNAP bit, the signaling snapshot will be exe-
cuted. The signaling snapshot means that the signaling bits of the first
basic frame are locked and output as the signaling bits of the current
whole multi-frame. This function is not supported in T1 DM format.
- Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
channels/timeslots of the corresponding link will be replaced by the sig-
naling trunk conditioning code in the A,B,C,D bits. When the GSTRKEN
bit is `0', the replacement can be performed on a per-channel/per-TS
basis by setting the STRKEN bit in the corresponding channel/timeslot.
The indirect registers of the Transmit Payload Control are accessed
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
read from or written into the specified indirect register is determined by
the RWN bit and the data is in the D[7:0] bits. The access status is indi-
cated in the BUSY bit. Refer to Chapter 4.5 Indirect Register Access
Scheme for details about the indirect registers write/read access.
Table 45: Related Bit / Register In Chapter 3.19
Bit
Register
Address (Hex)
PCCE
TPLC Control Enable
0CC, 1CC, 2CC, 3CC
ABXX (T1/J1 only)
TESTEN
TPLC / RPLC / PRGD Test
Configuration
0C7, 1C7, 2C7, 3C7
PRBSDIR
PRBSMODE[1:0]
TEST
ID * - Signaling Trunk Condi-
tioning Code
TPLC ID * - 41~58 (for
T1/J1) / 41~4F & 51~5F
(for E1)
SIGINS (T1/J1 only)
A,B,C,D
STRKEN
ZCS[2:0] (T1/J1 only)
TPLC Configuration
0CB, 1CB, 2CB, 3CB
GSUBST[2:0]
SIGSNAP
GSTRKEN
DTRK[7:0]
ID * - Data Trunk Conditioning
Code
TPLC ID * - 21~38 (for
T1/J1) / 20~3F (for E1)
SUBST[2:0]
ID * - Channel Control (for T1/
J1) / Timeslot Control (for E1)
TPLC ID * - 01~18 (for
T1/J1) / 00~1F (for E1)
SINV
OINV
EINV
ADDRESS[6:0]
TPLC Access Control
0C9, 1C9, 2C9, 3C9
RWN
D[7:0]
TPLC Access Data
0CA, 1CA, 2CA, 3CA
BUSY
TPLC Access Status
0C8, 1C8, 2C8, 3C8
Note:
*
ID means Indirect Register in the Transmit Payload Control function block.
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Advance Information
3.20
FRAME GENERATOR
3.20.1
GENERATION
3.20.1.1
T1 / J1 Mode
In T1/J1 mode, the data to be transmitted can be generated as
Super-Frame (SF), Extended Super-Frame (ESF), T1 Digital Multiplexer
(DM) or Switch Line Carrier - 96 (SLC-96) format.
3.20.1.1.1
Super Frame (SF) Format
The SF is generated when the FDIS bit is `0'.
The Frame Alignment Pattern (`100011011100' for T1 /
`10001101110X' for J1) will replace the F-bit of each frame if the FDIS bit
is set to `0'. The F-bit of the 12th frame in J1 mode should be `0' unless
Yellow alarm signal is transmitted.
When the FDIS bit is `0', one Ft bit (the F-bit in odd frame, refer to
Table 12) will be inverted if the FtINV bit is set; one Fs bit (the F-bit in
even frame, refer to Table 12) will be inverted if the FsINV bit is set.
When the FDIS bit is `0', configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The pattern
and the position of the Yellow alarm is different in T1 and J1 modes:
- In T1 mode, the Yellow alarm signal is logic 0 on the 2nd bit of
each channel;
- In J1 mode, the Yellow alarm signal is logic 1 on the 12th F-bit
position.
3.20.1.1.2
Extended Super Frame (ESF) Format
The ESF is generated when the FDIS bit is `0'.
The Frame Alignment Pattern (`001011') will replace the F-bit in
Frame (4n) (0<n<7) if the FDIS bit is set to `0'.
When the FDIS bit is `0', one Frame Alignment bit (refer to Table 13
for its position) will be inverted if the FsINV bit is set.
When the FDIS bit and the CRCBYP bit are both `0's, the calcu-
lated 6-bit CRC of the previous ESF frame will be inserted in the current
CRC-bit positions in every 4th frame starting with Frame 2 (refer to
Table 13) of the current ESF frame.
When the FDIS bit is `0', all the 6 CRC bits will be inverted if the
CRCINV bit is set.
When the FDIS bit is `0', the DL bit (refer to Table 13) can be
replaced with the Yellow alarm signal, the Bit-Oriented Code (refer to
Chapter 3.20.4 Bit-Oriented Message Transmitter (T1/J1 Only)), the
Automatic Performance Report Message (refer to Chapter 3.20.3 Auto-
matic Performance Report Message (T1/J1 Only)), the HDLC data (refer
to Chapter 3.20.2 HDLC Transmitter) or the idle code (`FFFF' for T1 /
`FF7E' for J1). The latter four kinds of replacements are enabled only if
the FDLBYP bit is set to `0'. When all of the five kinds of replacements
are enabled, the priority from highest to lowest is: Yellow alarm signal,
Bit-Oriented Code, Automatic Performance Report Message, HDLC
data and idle code.
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is transmitted in the DL bit position. Its pattern is `FF00' in
T1 mode or `FFFF' in J1 mode.
When the FDIS bit is `0', configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
3.20.1.1.3
T1 Digital Multiplexer (DM) Format (T1 only)
The T1 DM is generated when the FDIS bit is `0'.
The Frame Alignment Pattern (`100011011100') will replace the F-
bit of each frame if the FDIS bit is set to `0'.
When the FDIS bit is `0', one Ft bit (the F-bit in odd frame, refer to
Table 14) will be inverted if the FtINV bit is set; one Fs bit (the F-bit in
even frame, refer to Table 14) will be inverted if the FsINV bit is set.
When the FDIS bit is `0', configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
When the FDIS bit is `0', the DDS pattern (`0XX11101') will replace
the Bit 8 & 5~1 of each Channel 24 (refer to Table 14).
When the FDIS bit is `0', all the 6 DDS pattern bits will be inverted if
the DDSINV bit is set.
The `D' bit in Bit 7 of each Channel 24 can be replaced with the
HDLC data when the FDIS bit and the FDLBYP bit are both `0's. (Refer
to Chapter 3.20.2 HDLC Transmitter for details).
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is `0' transmitted in the `Y' bit in Bit 6 of each Channel 24.
The `Y' bit should be `1' when there is no Yellow alarm signal to be trans-
mitted.
3.20.1.1.4
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
The SLC-96 is generated when the FDIS bit is `0'.
The Frame Alignment Pattern (`001000110111001000110111'), the
Spoiler Bit and all the other Ft bits (the F-bit in odd frame) will replace
their F-bit (refer to Table 15 for their values and positions) if the FDIS bit
is set to `0'.
When the FDIS bit is `0', one Synchronization Fs bit will be inverted
if the FsINV bit is set; one Ft bit will be inverted if the FtINV bit is set.
When the FDIS bit and the FDLBYP bit are both `0's, the contents
in the XDL0, XDL1 & XDL2 registers will replace the Concentrator (C)
bits, the Maintenance (M) bits, the Alarm (A) bits and the Switch (S) bits
respectively (refer to Table 15).
When the FDIS bit is `0', configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
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Advance Information
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is logic 0 on the 2nd bit of each channel.
3.20.1.1.5
Interrupt Summary
At the first bit of each basic frame, the BFI bit will be set. In this con-
dition, if the BFE bit is enabled, an interrupt will be reported by the INT
pin.
At the first bit of each SF/ESF/T1 DM/SLC-96 multiframe, the MFI
bit will be set. In this condition, if the MFE bit is enabled, an interrupt will
be reported by the INT pin.
Table 46: Related Bit / Register In Chapter 3.20.1.1
Bit
Register
T1/J1 Address (Hex)
FDIS
T1/J1 Mode
062, 162, 262, 362
CRCBYP
FDLBYP
FtINV
Error Insertion
06F, 16F, 26F, 36F
FsINV
CRCINV
DDSINV
MIMICEN
FGEN Maintenance 1
06C, 16C, 26C, 36C
XYEL
FGEN Maintenance 0
06B, 16B, 26B, 36B
AUTOYELLOW
C[11:1]
XDL1 & XDL0
066, 166, 266, 366 & 065,
165, 265, 365
M[3:1]
XDL1
066, 166, 266, 366
A[2:1]
XDL2
067, 167, 267, 367
S[4:1]
BFI
FGEN Interrupt Indication
06E, 16E, 26E, 36E
MFI
BFE
FGEN Interrupt Control
06D, 16D, 26D, 36D
MFE
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3.20.1.2
E1 Mode
In E1 mode, the Frame Generator can generate Basic Frame,
CRC-4 Multi-Frame and Channel Associated Signaling (CAS) Multi-
Frame. The Frame Generator can also transmit alarm indication signal
when special conditions occurs in the received data stream. Interna-
tional bits, National bits and Extra bits replacements and data inversions
are all supported in the Frame Generator.
The generation of the Basic frame, CRC Multi-Frame and Channel
Associated Signaling (CAS) Multi-Frame are controlled by the FDIS bit,
the GENCRC bit, the CRCM bit and the SIGEN bit. Refer to Table 47 for
details.
When the Basic frame is generated, the Frame Alignment
Sequence (FAS) (`0011011') will replace the Bit 2 ~ Bit 8 of TS0 of each
even frame; the NFAS bit (`1') will replace the Bit 2 of TS0 of each odd
frame. If the FAS1INV bit is set, one FAS bit will be inverted; if the
FASALLINV bit is set, all 7 FAS bits will be inverted; if the NFASINV bit is
set, the NFAS bit will be inverted.
When the Basic frame is generated, if the SiDIS bit is `0', the value
set in the Si[1] and Si[0] bits will replace the International bit (Bit 1) of
FAS frame and NFAS frame respectively.
When the Basic frame is generated, the Remote Alarm Indication
(RAI) can be transmitted as logic 1 in the A bit position. It is transmitted
manually when the REMAIS bit is `1'. It can also be transmitted automat-
ically when the AUTOYELLOW bit is set to `1'. In this case, the RAI
transmission criteria are selected by the G706RAI bit.
When the Basic frame is generated, the setting in the SaX[1] bit will
be transmitted in the Sa bit position if enabled by the corresponding
SaXEN bit (`X' is from 4 to 8).
The CRC Multi-Frame is generated on the base of the Basic frame
generation. When it is generated, the CRC Multi-Frame alignment pat-
tern (`001011') will replace the Bit 1 of TS0 of the first 6 odd frames; the
calculated 4-bit CRC of the previous Sub-Multi-Frame will be inserted in
the CRC-bit positions of the current Sub-Multi-Frame. The CRC-bit posi-
tion is the Bit 1 of TS0 of each even frame. Refer to Table 18 for the
CRC Multi-Frame structure. If the CRCPINV bit is set, all 6 CRC Multi-
Frame alignment bits will be inverted; if the CRCINV bit is set, all 4 cal-
culated CRC bits will be inverted.
When the CRC Multi-Frame is generated, since 14 International bit
positions have been occupied by the CRC Multi-Frame alignment pat-
tern and CRC-4 checking bits, the remaining 2 International bit positions
are inserted by the E bits. The control over the E bits is illustrated in
Table 48.
When the CRC Multi-Frame is generated, the setting in the
SaX[1:4] bits will be transmitted in the Sa bit position if enabled by the
corresponding SaXEN bit (`X' is from 4 to 8).
The Channel Associated Signaling (CAS) Multi-Frame is generated
on the base of the Basic frame generation. When it is generated, the
Signaling Multi-Frame alignment pattern (`0000') will replace the high
nibble (Bit 1 ~ Bit 4) of TS16 of every 32 Basic frames. If the CASPINV
bit is set, all 4 Signaling Multi-Frame alignment bits will be inverted.
When the Signaling Multi-Frame is generated, if the XDIS bit is `0',
the value set in the FGEN Extra register will be inserted into the Extra
bits (the Bit 5, 7 & 8 of TS16 of Frame 0 of the Signaling Multi-Frame).
When the Signaling Multi-Frame is generated, the value in the
MFAIS bit will be continuously transmitted in the Y bit position (the Bit 6
of TS16 of Frame 0 of the Signaling Multi-Frame).
When the Signaling Multi-Frame is generated, all the bits in TS16
can be overwritten by all `Zero's or all 'One's by setting the TS16LOS bit
or the TS16AIS bit respectively. The all zeros overwritten takes a higher
priority.
When the Modified CRC Multi-Frame is generated, only the Sa bit
position and the calculated CRC-4 bit position can be changed. All the
other bits are transparently transmitted unless all 'One's or all `Zero's are
transmitted (refer to Chapter 3.20.6 All `Zero's & All `One's).
The frame can only be generated on the base of the FDIS bit being
`0'. If the FDIS bit is set to `1', the data received from the Transmit Pay-
load Control will be transmitted transparently to the HDLC Transmitter.
Table 47: E1 Frame Generation
Desired Frame Type
FDIS GENCRC CRCM SIGEN
Basic Frame
0
0
X
X
0
1
0
X
CRC Multi-Frame
0
1
0
X
Modified CRC Multi-Frame
0
1
1
X
Channel Associated Signaling (CAS) Multi-
Frame
0
0
X
1
0
1
0
1
Table 48: Control Over E Bits
FEBEDIS OOCMFV
SiDIS
E Bits Insertion
0
0
X
A single zero is inserted into the E bit when a CRC-4 Error event is detected in the receive path. (the E1 bit corresponds to SMFI
and the E2 bit corresponds to SMFII)
0
1
X
The value in the Si[1] bit is inserted into the E1 bit position. The value in the Si[0] bit is inserted into the E2 bit position.
1
X
0
The value in the Si[1] bit is inserted into the E1 bit position. The value in the Si[0] bit is inserted into the E2 bit position.
1
X
1
The E bit positions are unchanged.
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3.20.1.2.1
Interrupt Summary
In E1 mode, the interrupt is summarized in Table 49.
When there are conditions meeting the interrupt sources, the corre-
sponding Interrupt Indication bit will be set. When the Interrupt Indication
bit is `1', if enabled by the corresponding Interrupt Enable bit, an inter-
rupt will be reported by the INT pin.
Table 49: Interrupt Summary In E1 Mode
Interrupt Sources
Interrupt Indication Bit
Interrupt Enable Bit
At the first bit of each FAS.
FASI
FASE
At the first bit of each Basic frame.
BFI
BFE
At the first bit of each CRC Multi-Frame.
MFI
MFE
At the first bit of each CRC Sub Multi-Frame.
SMFI
SMFE
At the first bit of each Signaling Multi-Frame.
SIGMFI
SIGMFE
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Table 50: Related Bit / Register In Chapter 3.20.1.2
Bit
Register
E1 Address (Hex)
FDIS
E1 Mode
062, 162, 262, 362
GENCRC
CRCM
SIGEN
SiDIS
FEBEDIS
XDIS
FAS1INV
Error Insertion
06F, 16F, 26F, 36F
FASALLINV
NFASINV
CRCPINV
CASPINV
CRCINV
Si[1]
FGEN International Bit
063, 163, 263, 363
Si[0]
REMAIS
FGEN Maintenance 0
06B, 16B, 26B, 36B
AUTOYELLOW
G706RAI
MFAIS
TS16LOS
TS16AIS
SaX[1:4] (`X' is from 4 to 8)
Sa4 Code-word ~ Sa8 Code-word
065 ~ 069, 165 ~ 169, 265 ~ 269, 365 ~ 369
SaXEN (`X' is from 4 to 8)
FGEN Sa Control
064, 164, 264, 364
OOCMFV
FRMR Status
04F, 14F, 24F, 34F
X[0:2]
FGEN Extra
06A, 16A, 26A, 36A
FASI
FGEN Interrupt Indication
06E, 16E, 26E, 36E
BFI
MFI
SMFI
SIGMFI
FASE
FGEN Interrupt Control
06D, 16D, 26D, 36D
BFE
MFE
SMFE
SIGMFE
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3.20.2
HDLC TRANSMITTER
The HDLC Transmitter inserts the data into the selected position to
form HDLC or SS7 packet data stream.
3.20.2.1
HDLC Channel Configuration
In T1/J1 mode ESF & T1 DM formats, three HDLC Transmitters
(#1, #2 & #3) per link are provided for HDLC insertion to the data stream
to be transmitted. In T1/J1 mode SF & SLC-96 formats, two HDLC
Transmitters (#2 & #3) per link are provided for HDLC insertion. In E1
mode, three HDLC Transmitters (#1, #2 & #3) per link are provided for
HDLC insertion. Except in T1/J1 mode ESF & T1 DM formats, the HDLC
channel of HDLC Transmitter #1 is fixed in the DL bit (in ESF format)
and D bit in CH24 (in T1 DM format) respectively (refer to Table 13 &
Table 14), the other HDLC channel is configured as the follows:
1. Set the EVEN bit and/or the ODD bit to select the even and/or
odd frames;
2. Set the TS[4:0] bits to define the channel/timeslot of the
assigned frame;
3. Set the BITEN[7:0] bits to select the bits of the assigned channel/
timeslot.
Then all the functions of the HDLC Transmitter will be enabled only
if the corresponding TDLEN bit is set to `1'.
3.20.2.2
Two HDLC Modes
Two modes are selected by the THDLCM bit in the HDLC Transmit-
ter. The two modes are: HDLC mode (per Q.921) and SS7 (per Q.703).
3.20.2.2.1
HDLC Mode
A FIFO buffer is used to store the HDLC data written in the
DAT[7:0] bits. The FIFO depth is 128 bytes. When it is full, it will be indi-
cated by the FUL bit. When it is empty, it will be indicated by the EMP bit.
If an entire HDLC packet is stored in the FIFO indicated by the
EOM bit, or if the data in the FIFO exceeds the upper threshold set by
the HL[1:0] bits, the data in the FIFO will be transmitted. The opening
flag (`01111110') will be prepended before the data automatically. The
transmission will not stop until the entire HDLC data are transmitted.
Then the 2-byte FCS and the closing flag (`01111110') will be added to
the end of the HDLC data automatically. During the HDLC data trans-
mission, a zero is stuffed automatically into the serial output data if there
are five consecutive 'One's ahead.
The abort sequence (`01111111') will be inserted to the HDLC
packet anytime when the ABORT bit is set. Or when the FIFO is empty
and the transmitted last byte is not the end of the current HDLC packet,
the abort sequence will be transmitted automatically.
If the TDLEN bit is enabled and there is no HDLC packet in the
FIFO to be transmitted, the 7E (Hex) flag will always be transmitted.
3.20.2.2.2
SS7 Mode
A FIFO buffer is used to store the SS7 data written in the DAT[7:0]
bits. The FIFO depth is 128 bytes. When it is full, it will be indicated by
the FUL bit. When it is empty, it will be indicated by the EMP bit.
If an entire SS7 packet is stored in the FIFO indicated by the EOM
bit, or if the data in the FIFO exceeds the upper threshold set by the
HL[1:0] bits, the data in the FIFO will be transmitted. The opening flag
(`01111110') will be prepended before the data automatically. The trans-
mission will not stop until the entire SS7 data are transmitted. Then the
2-byte FCS and the closing flag (`01111110') will be added to the end of
the SS7 data automatically. During the SS7 data transmission, a zero is
stuffed automatically into the serial output data if there are five consecu-
tive 'One's ahead.
The abort sequence (`01111111') will be inserted to the SS7 packet
anytime when the ABORT bit is set. Or when the FIFO is empty and the
last transmitted byte is not the end of the current SS7 packet, the abort
sequence will be transmitted automatically.
When the FIFO is empty, if less than 16 bytes are written into the
FIFO and the XREP bit is set to `1', these bytes in the FIFO will be trans-
mitted repeatedly with the opening flag, FCS and closing flag, until the
XREP bit is disabled and the current packet transmission is finished.
However, during the cyclic transmission period, the data written into the
FIFO will not be transmitted.
If the AUTOFISU bit is set and there is no data in the FIFO to be
transmitted, the 7E (Hex) flags will be transmitted N times (the `N' is
determined by the FL[1:0] bits), then the FISU packet will be transmitted
(refer to Figure 14) with the BSN and FSN the same as the last transmit-
ted packet.
If the TDLEN bit is enabled and there is no SS7 packet in the FIFO
to be transmitted, the 7E (Hex) flag will always be transmitted.
Table 51: Related Bit / Register In Chapter 3.20.2.1
Bit
Register
Address (Hex)
EVEN
THDLC1 Assignment (E1
only) / THDLC2 Assign-
ment / THDLC3 Assignment
085, 185, 285, 385(E1 only) / 086,
186, 286, 386 / 087, 187, 287, 387
ODD
TS[4:0]
BITEN[7:0]
THDLC1 Bit Select (E1
only) / THDLC2 Bit Select /
THDLC3 Bit Select
088, 188, 288, 388 (E1 only) / 089,
189, 289, 389 / 08A, 18A, 28A,
38A
TDLEN3
THDLC Enable Control
084, 184, 284, 384
TDLEN2
TDLEN1
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3.20.2.3
Interrupt Summary
In both of the two HDLC modes, when the data in the FIFO is below
the lower threshold set by the LL[1:0] bits, it will be indicated by the RDY
bit. When there is a transition (from `0' to `1') on the RDY bit, the RDYI
bit will be set. In this case, if enabled by the RDYE bit, an interrupt will
be reported by the INT pin.
In both of the two HDLC modes, when the FIFO is empty and the
last transmitted byte is not the end of the current HDLC/SS7 packet, the
UDRUNI bit will be set. In this case, if enabled by the UDRUNE bit, an
interrupt will be reported by the INT pin.
3.20.2.4
Reset
The HDLC Transmitter will be reset when there is a transition from
`0' to `1' on the TRST bit. The reset will clear the FIFO.
Table 52: Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4
Bit
Register
Address (Hex)
THDLCM
THDLC1 Control / THDLC2 Control / THDLC3 Control
0A7, 1A7, 2A7, 3A7 / 0A8, 1A8, 2A8, 3A8 / 0A9, 1A9, 2A9, 3A9
EOM
ABORT
XREP
AUTOFISU
TRST
DAT[7:0]
THDLC1 Data / THDLC2 Data / THDLC3 Data
0AD, 1AD, 2AD, 3AD / 0AE, 1AE, 2AE, 3AE / 0AF, 1AF, 2AF, 3AF
FUL
TFIFO1 Status / TFIFO2 Status / TFIFO3 Status
0B0, 1B0, 2B0, 3B0 / 0B1, 1B1, 2B1, 3B1 / 0B2, 1B2, 2B2, 3B2
EMP
RDY
TDLEN3
THDLC Enable Control
084, 184, 284, 384
TDLEN2
TDLEN1
HL[1:0]
TFIFO1 Threshold / TFIFO2 Threshold / TFIFO3 Threshold
0AA, 1AA, 2AA, 3AA / 0AB, 1AB, 2AB, 3AB / 0AC, 1AC, 2AC, 3AC
FL[1:0]
LL[1:0]
RDYI
THDLC1 Interrupt Indication / THDLC2 Interrupt Indication /
THDLC3 Interrupt Indication
0B6, 1B6, 2B6, 3B6 / 0B7, 1B7, 2B7, 3B7 / 0B8, 1B8, 2B8, 3B8
UDRUNI
RDYE
THDLC1 Interrupt Control / THDLC2 Interrupt Control / THDLC3
Interrupt Control
0B3, 1B3, 2B3, 3B3 / 0B4, 1B4, 2B4, 3B4 / 0B5, 1B5, 2B5, 3B5
UDRUNE
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3.20.3
AUTOMATIC PERFORMANCE REPORT MESSAGE (T1/
J1 ONLY)
The Automatic Performance Report Message (APRM) can only be
transmitted in the ESF format in T1/J1 mode.
Five kinds of events are counted every second in the APRM:
1. The Bipolar Violation (BPV) Error / HDB3 Code Violation (CV)
Error and Excessive Zero (EXZ) Error event detected in the B8ZS/
HDL3/AMI Decoder;
2. The CRC-6 Error event detected in the Frame Processor;
3. The Frame Alignment Bit Error event detected in the Frame Pro-
cessor;
4. The Severely Frame Alignment Bit Error event detected in the
Frame Processor;
5. The Buffer Slip event occurred in the Elastic Store Buffer.
Enabled by the AUTOPRM bit, the Automatic Performance Report
Message is generated every one second and transmitted on the DL bit
positions. The APRM format is illustrated in Table 53.
The APRM is transmitted bit by bit from Bit 1 to Bit 8 and from Octet
No. 1 to Octet No. 14. In the above table, the value in the C/R bit posi-
tion, the R bit position, the U1 bit position, the U2 bit position and the LB
bit position are determined by the CRBIT bit, the RBIT bit, the U1BIT bit,
the U2BIT bit and the LBBIT bit in the APRM Control register respec-
tively.
The Nm and Ni bit position is a module 4 counter.
The remaining bits in Octet No.5 to Octet No. 12 interpret the event
numbers counted by the APRM. The details are listed in Table 54. Their
default value are `0's.
Table 53: APRM Message Format
Octet No.
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
Flag (`01111110')
2
SAPI (`001110C/R0')
3
TEI (`00000001')
4
Control (`00000011')
5
G3
LV
G4
U1
U2
G5
SL
G6
6
FE
SE
LB
G1
R
G2
Nm
Ni
7
G3
LV
G4
U1
U2
G5
SL
G6
8
FE
SE
LB
G1
R
G2
Nm
Ni
9
G3
LV
G4
U1
U2
G5
SL
G6
10
FE
SE
LB
G1
R
G2
Nm
Ni
11
G3
LV
G4
U1
U2
G5
SL
G6
12
FE
SE
LB
G1
R
G2
Nm
Ni
13
FCS
14
Table 54: APRM Interpretation
A Logic 1 In The Following Bit Position
Interpretation
G1
CRC-6 Error event = 1
G2
1 < CRC-6 Error event
5
G3
5 < CRC-6 Error event
10
G4
10 < CRC-6 Error event
100
G5
100 < CRC-6 Error event
319
G6
CRC-6 Error event > 320
SE
Severely Frame Alignment Bit Error event
1
FE
Frame Alignment Bit Error event
1
LV
Bipolar Violation (BPV) Error / HDB3 Code Violation (CV) Error and Excessive Zero (EXZ) Error event
1
SL
Buffer Slip event
1
IDT82P2284
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3.20.4
BIT-ORIENTED MESSAGE TRANSMITTER (T1/J1 ONLY)
The Bit Oriented Message (BOM) can only be transmitted in the
ESF format in T1/J1 mode.
The BOM pattern is `111111110XXXXXX0' which occupies the DL of
the F-bit in the ESF format. The six `X's represent the code that is pro-
grammed in the XBOC[5:0] bits. The BOM is transmitted only if the
XBOC[5:0] bits are not all 'One's.
3.20.5
INBAND LOOPBACK CODE GENERATOR (T1/J1 ONLY)
The Inband Loopback Code Generator can only transmit inband
loopback code in a framed or unframed T1/J1 data stream.
The length and the content of the inband loopback code are pro-
grammed in the CL[1:0] bits and the IBC[7:0] bits respectively. The code
can only be transmitted when the IBCDEN bit is enabled. In framed
mode, which is configured by the IBCDUNFM bit, the bits in all 24 chan-
nels are overwritten with the inband loopback code and the F-bit is not
changed. In unframed mode, which is configured by the IBCDUNFM bit,
all the bits in 24 channels and the F-bit are overwritten with the inband
loopback code.
3.20.6
ALL `ZERO'S & ALL `ONE'S
After all the above processes, all 'One's or all `Zero's will overwrite
all the data stream if the TAIS bit and the TXDIS bit are set. The all zeros
transmission takes a higher priority.
3.20.7
CHANGE OF FRAME ALIGNMENT
Any transition (from `0' to `1' or from `1' to `0') on the COFAEN bit
will lead to one-bit deletion or one-bit repetition in the data stream to be
transmitted, that is, to change the frame alignment position. The one-bit
deletion or repetition occurs randomly.
Table 55: Related Bit / Register In Chapter 3.20.3
Bit
Register
T1/J1 Address (Hex)
AUTOPRM
APRM Control
07F, 17F, 27F, 37F
CRBIT
RBIT
U1BIT
U2BIT
LBBIT
Table 56: Related Bit / Register In Chapter 3.20.4 & Chapter 3.20.5
Bit
Register
T1/J1 Address (Hex)
XBOC[5:0]
XBOC Code
080, 180, 280, 380
IBC[7:0]
XIBC Code
075, 175, 275, 375
CL[1:0]
XIBC Control
074, 174, 274, 374
IBCDEN
IBCDUNFM
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3.21
TRANSMIT BUFFER
Transmit Buffer can be used in the circumstances that backplane
timing is different from the line side timing in Transmit Slave mode.
The function of timing option is also integrated in this block. The
source of the transmit clock can be selected in the recovered clock from
the line side, the processed clock from the backplane or the master
clock generated by the clock generator.
In Transmit Master mode, the Transmit Buffer is bypassed automat-
ically. The source of the transmit clock can be selected between the
recovered clock from the line side and the master clock generated by
the internal clock generator (1.544 MHz in T1/J1 mode or 2.048 MHz in
E1 mode). The selection is made by the XTS bit.
In Transmit Clock Slave T1/J1 mode E1 rate, for the backplane tim-
ing is 2.048 MHz from backplane and the line timing is 1.544 MHz from
the internal clock generator, the Transmit Buffer is selected automati-
cally to absorb high frequency mapping jitter due to the E1 to T1/J1
mapping scheme. In this case, 1.544 MHz must be locked to 2.048 MHz
by PLL of the internal clock generator. The XTS bit in the Transmit Tim-
ing Option register does not take effect.
In other Transmit Clock Slave modes, whether the Transmit Buffer
is bypassed and the source of the transmit clock selection are selected
by the XTS bit. When the XTS bit is set to `1', line side timing is from
internal clock generator, but backplane timing is from backplane, so the
Transmit Buffer is selected to accommodate the different clocks. If these
two clocks are not locked, an internal slip will occur in the Transmit
Buffer. The source of the transmit clock is from the master clock gener-
ated by the internal clock generator (1.544 MHz in T1/J1 mode or 2.048
MHz in E1 mode). When the XTS bit is set to `0', the line side timing is
also from the backplane timing, so the Transmit Buffer is bypassed. The
source of the transmit clock is from the processed clock from the back-
plane.
In Transmit Multiplexed mode, whether the Transmit Buffer is
bypassed and the source of the transmit clock selection are the same as
that described in other Transmit Clock Slave modes.
In most applications of Transmit Clock Slave mode, the XTS bit can
be set to `0' to bypass the Transmit Buffer (The Transmit Buffer is
selected automatically in T1/J1 mode E1 rate).
3.22
ENCODER
3.22.1
LINE CODE RULE
3.22.1.1
T1/J1 Mode
In T1/J1 mode, the B8ZS line code rule or the AMI line code rule
can be selected by the T_MD bit.
3.22.1.2
E1 Mode
In E1 mode, the HDB3 line code rule or the AMI line code rule can
be selected by the T_MD bit.
3.22.2
BPV ERROR INSERTION
For test purpose, a BPV error can be inserted to the data stream to
be transmitted by a transition from `0' to `1' on the BPV_INS bit.
3.22.3
ALL `ONE'S INSERTION
When the LOS is detected in the receive path, all `One's will be
inserted automatically to the data stream to be transmitted by setting the
ATAO bit.
Table 57: Related Bit / Register In Chapter 3.20.6, Chapter 3.20.7 &
Chapter 3.21
Bit
Register
Address (Hex)
TAIS
FGEN Maintenance 1
06C, 16C, 26C, 36C
TXDIS
COFAEN
XTS
Transmit Timing Option
070, 170, 270, 370
Table 58: Related Bit / Register In Chapter 3.22
Bit
Register
Address (Hex)
T_MD
Transmit Configuration 0
022, 122, 222, 322
BPV_INS
Maintenance Function Control 2
031, 131, 231, 331
ATAO
Maintenance Function Control 1
02C, 12C, 22C, 32C
IDT82P2284
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3.23
TRANSMIT JITTER ATTENUATOR
The Transmit Jitter Attenuator of each link can be chosen to be
used or not. This selection is made by the TJA_E bit.
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
Figure 5.
The FIFO is used as a pool to buffer the jittered input data, then the
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the TJA_DP[1:0]
bits. Accordingly, the constant delay produced by the Jitter Attenuator is
16 bits, 32 bits or 64 bits. The 128-bit FIFO is used when large jitter tol-
erance is expected, and the 32-bit FIFO is used in delay sensitive appli-
cations.
The DPLL is used to generate a de-jittered clock to clock out the
data stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter which fre-
quency is lower than the CF passes through the DPLL without any atten-
uation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or 1.26
Hz, as selected by the TJA_BW bit. In E1 applications, the CF of the
DPLL can be 6.77 Hz or 0.87 Hz, as selected by the TJA_BW bit. The
lower the CF is, the longer time is needed to achieve synchronization.
If the incoming data moves faster than the outgoing data, the FIFO
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
TJA_IS bit. When the TJA_IS bit is `1', an interrupt will be reported on
the INT pin if enabled by the TJA_IE bit.
To avoid overflowing or underflowing, the JA-Limit function can be
enabled by setting the TJA_LIMT bit. When the JA-Limit function is
enabled, the speed of the outgoing data will be adjusted automatically if
the FIFO is close to its full or emptiness. The criteria of speed adjust-
ment start are listed in Table 6. Though the LA-Limit function can reduce
the possibility of FIFO overflow and underflow, the quality of jitter attenu-
ation is deteriorated.
Selected by the TJITT_TEST bit, the real time interval between the
read and write pointer of the FIFO or the peak-peak interval between the
read and write pointer of the FIFO can be indicated in the TJITT[6:0]
bits. When the TJITT_TEST bit is `0', the current interval between the
read and write pointer of the FIFO will be written into the TJITT[6:0] bits.
When the TJITT_TEST bit is `1', the current interval is compared with
the old one in the TJITT[6:0] bits and the larger one will be indicated by
the TJITT[6:0] bits.
The performance of Receive Jitter Attenuator meets the ITUT
I.431, G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/
13, AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.9 Jitter Tolerance and Chapter 7.10 Jitter
Transfer for details.
Table 59: Related Bit / Register In Chapter 3.23
Bit
Register
Address (Hex)
TJA_E
Transmit Jitter Attenuation Configuration 021, 121, 221, 321
TJA_DP[1:0]
TJA_BW
TJA_LIMT
TJITT_TEST
TJA_IS
Interrupt Status 1
03B, 13B, 23B, 33B
TJA_IE
Interrupt Enable Control 1
034, 134, 234, 334
TJITT[6:0]
Transmit Jitter Measure Value Indication 038, 138, 238, 338
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3.24
WAVEFORM SHAPER / LINE BUILD OUT
According to the various cables, configured by the PULS[3:0] bits,
three ways of manipulating the waveform shaper can be selected before
the data is transmitted:
1. Preset Waveform Template;
2. Line Build Out (LBO) Filter (T1 only);
3. User-Programmable Arbitrary Waveform.
3.24.1
PRESET WAVEFORM TEMPLATE
The preset waveform template is provided for short haul applica-
tions.
3.24.1.1
T1/J1 Mode
In T1/J1 applications, the waveform template is shown in Figure 31,
which meets T1.102 and G.703, and it is measured in the far end as
shown in Figure 32.
Figure 31. DSX-1 Waveform Template
Figure 32. T1/J1 Pulse Template Measurement Circuit
In T1 applications, to meet the template, five preset waveform tem-
plates are provided corresponding to five grades of cable length. The
selection is made by the PULS[3:0] bits. In J1 applications, the
PULS[3:0] bits should be set to `0111'. The details are listed in Table 60.
3.24.1.2
E1 Mode
In E1 applications, the waveform template is shown in Figure 33,
which meets G.703, and it is measured on the near line side as shown in
Figure 34.
Figure 33. E1 Waveform Template
Figure 34. E1 Pulse Template Measurement Circuit
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
0
250
500
750
1000
1250
Time (ns)
Nor
m
al
i
z
ed Ampl
i
t
ude
IDT82P2284
TTIPn
TRINGn
Cable
R
LOAD
V
OUT
Note: R
LOAD
= 100
+ 5%
Table 60: PULS[3:0] Setting In T1/J1 Mode
Cable Configuration
PULS[3:0]
T1 - 0 ~ 133 ft
0 0 1 0
T1 - 133 ~ 266 ft
0 0 1 1
T1 - 266 ~ 399 ft
0 1 0 0
T1 - 399 ~ 533 ft
0 1 0 1
T1 - 533 ~ 655 ft
0 1 1 0
J1 - 0 ~ 655 ft
0 1 1 1
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
1.20
Normal
ized A
m
p
litude
Time In Unit Intervals
IDT82P2284
V
OUT
R
LOAD
TTIPn
TRINGn
Note: R
LOAD
= 75
or 120 (+ 5%)
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To meet the template, two preset waveform templates are provided
corresponding to two kinds of cable impedance. The selection is made
by the PULS[3:0] bits. In internal impedance matching mode, if the cable
impedance is 75
, the PULS[3:0] bits should be set to `0000'; if the
cable impedance is 120
, the PULS[3:0] bits should be set to `0001'. In
external impedance matching mode, for both 75
and 120 cable
impedance, the PULS[3:0] bits should be set to `0001'.
3.24.2
LINE BUILD OUT (LBO) (T1 ONLY)
In long haul applications, the output on the TTIPn/TRINGn pins
should be attenuated before transmission to prevent the cross-talk in the
far end. Three LBOs are used to implement the pulse attenuation. Four
grades of attenuation with each step of 7.5 dB are specified in the FCC
Part 68 Regulations. The attenuation grade is selected by the PULS[3:0]
bits. The details are listed in Table 61.
3.24.3
USER-PROGRAMMABLE ARBITRARY WAVEFORM
User-programmable arbitrary waveform can be used in both short
haul applications and long haul applications if the PULS[3:0] bits are set
to `11XX' in the corresponding link. This allows the transmitter perfor-
mance to be tuned for a wide variety of line condition or special applica-
tion.
Each pulse shape can extend up to 4 UIs (Unit Interval) addressed
by the UI[1:0] bits, and each UI is divided into 16 sub-phases addressed
by the SAMP[3:0] bits. The pulse amplitude of each phase is repre-
sented by a binary byte, within the range from +63 to -63, stored in the
WDAT[6:0] bits in signed magnitude form. The maximum number +63
(D) represents the positive maximum amplitude of the transmit pulse
while the most negative number -63 (D) represents the maximum nega-
tive amplitude of the transmit pulse. Thus, up to 64 bytes are used. For
each channel, a 64 bytes RAM is available.
There are twelve standard templates which are stored in a local
ROM. One of them can be selected as reference and made some
changes to get the desired waveform.
To do this, the first step is to choose a set of waveform value, which
is the most similar to the desired pulse shape, from the following 12
tables (Table 62 to Table 73), and set the SCAL[5:0] bits to the corre-
sponding standard value. Table 62 to Table 73 list the sample data and
the standard scaling value of each of the 12 templates.
Modifying the corresponding sample data can get the desired
transmit pulse shape. By increasing or decreasing by `1' from the stan-
dard value in the SCAL[5:0] bits, the pulse amplitude can be scaled up
or down at the percentage ratio against the standard pulse amplitude if
necessary. For different pulse shapes, the value of the SCAL[5:0] bits
and the scaling percentage ratio are different. The values are listed in
Table 62 to Table 73.
Do the followings step by step, the desired waveform can be pro-
grammed based on the selected waveform template:
1. Select the UI by the UI[1:0] bits;
2. Specify the sample address in the selected UI by the SAMP[3:0]
bits;
3. Write sample data to the WDAT[6:0] bits. It contains the data to
be stored in the RAM, addressed by the selected UI and the correspond-
ing sample address;
4. Set the RW bit to `0' to write data to RAM, or to `1' to read data
from RAM;
5. Set the DONE bit to implement the read or write operation;
(Repeat the above steps until all the sample data are written to or
read from the internal RAM).
6. Write the scaling data to the SCAL[5:0] bits to scale the ampli-
tude of the waveform based on the selected standard pulse amplitude.
Table 62 to Table 73 give all the sample data based on preset pulse
templates and LBOs in details for reference. For preset pulse templates
and LBOs, scaling up/down against the pulse amplitude is not sup-
ported.
1. Table 62 - Transmit Waveform Value For E1 75
2. Table 63 - Transmit Waveform Value For E1 120
3. Table 64 - Transmit Waveform Value For T1 0~133 ft
4. Table 65 - Transmit Waveform Value For T1 133~266 ft
5. Table 66 - Transmit Waveform Value For T1 266~399 ft
6. Table 67 - Transmit Waveform Value For T1 399~533 ft
7. Table 68 - Transmit Waveform Value For T1 533~655 ft
8. Table 69 - Transmit Waveform Value For J1 0~655 ft
9. Table 70 - Transmit Waveform Value For DS1 0 dB LBO
10. Table 71 - Transmit Waveform Value For DS1 -7.5 dB LBO
11. Table 72 - Transmit Waveform Value For DS1 -15.0 dB LBO
12. Table 73 - Transmit Waveform Value For DS1 -22.5 dB LBO
Table 61: LBO PULS[3:0] Setting In T1 Mode
Cable Configuration
PULS[3:0]
0 dB LBO
1 0 0 0
-7.5 dB LBO
1 0 0 1
-15.0 dB LBO
1 0 1 0
-22.5 dB LBO
1 0 1 1
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Table 62: Transmit Waveform Value For E1 75
UI 1
UI 2
UI 3
UI 4
Sample 1
0000000
0000000
0000000
0000000
Sample 2
0000000
0000000
0000000
0000000
Sample 3
0000000
0000000
0000000
0000000
Sample 4
0001100
0000000
0000000
0000000
Sample 5
0110000
0000000
0000000
0000000
Sample 6
0110000
0000000
0000000
0000000
Sample 7
0110000
0000000
0000000
0000000
Sample 8
0110000
0000000
0000000
0000000
Sample 9
0110000
0000000
0000000
0000000
Sample 10
0110000
0000000
0000000
0000000
Sample 11
0110000
0000000
0000000
0000000
Sample 12
0110000
0000000
0000000
0000000
Sample 13
0000000
0000000
0000000
0000000
Sample 14
0000000
0000000
0000000
0000000
Sample 15
0000000
0000000
0000000
0000000
Sample 16
0000000
0000000
0000000
0000000
The standard value of the SCAL[5:0] bits is `100001'. One step change of this value
results in 3% scaling up/down against the pulse amplitude.
Table 63: Transmit Waveform Value For E1 120
UI 1
UI 2
UI 3
UI 4
Sample 1
0000000
0000000
0000000
0000000
Sample 2
0000000
0000000
0000000
0000000
Sample 3
0000000
0000000
0000000
0000000
Sample 4
0001111
0000000
0000000
0000000
Sample 5
0111100
0000000
0000000
0000000
Sample 6
0111100
0000000
0000000
0000000
Sample 7
0111100
0000000
0000000
0000000
Sample 8
0111100
0000000
0000000
0000000
Sample 9
0111100
0000000
0000000
0000000
Sample 10
0111100
0000000
0000000
0000000
Sample 11
0111100
0000000
0000000
0000000
Sample 12
0111100
0000000
0000000
0000000
Sample 13
0000000
0000000
0000000
0000000
Sample 14
0000000
0000000
0000000
0000000
Sample 15
0000000
0000000
0000000
0000000
Sample 16
0000000
0000000
0000000
0000000
The standard value of the SCAL[5:0] bits is `100001'. One step change of this value
results in 3% scaling up/down against the pulse amplitude.
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Table 64: Transmit Waveform Value For T1 0~133 ft
UI 1
UI 2
UI 3
UI 4
Sample 1
0011010
1000010
0000000
0000000
Sample 2
0100111
0000000
0000000
0000000
Sample 3
0100111
0000000
0000000
0000000
Sample 4
0100110
0000000
0000000
0000000
Sample 5
0100110
0000000
0000000
0000000
Sample 6
0100101
0000000
0000000
0000000
Sample 7
0100101
0000000
0000000
0000000
Sample 8
0100101
0000000
0000000
0000000
Sample 9
0100101
0000000
0000000
0000000
Sample 10
1001010
0000000
0000000
0000000
Sample 11
1001010
0000000
0000000
0000000
Sample 12
1001010
0000000
0000000
0000000
Sample 13
1000100
0000000
0000000
0000000
Sample 14
1000100
0000000
0000000
0000000
Sample 15
1000100
0000000
0000000
0000000
Sample 16
1000010
0000000
0000000
0000000
The standard value of the SCAL[5:0] bits is `110110'. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
Table 65: Transmit Waveform Value For T1 133~266 ft
UI 1
UI 2
UI 3
UI 4
Sample 1
0011110
1000010
0000000
0000000
Sample 2
0101100
0000000
0000000
0000000
Sample 3
0101100
0000000
0000000
0000000
Sample 4
0101001
0000000
0000000
0000000
Sample 5
0101000
0000000
0000000
0000000
Sample 6
0101000
0000000
0000000
0000000
Sample 7
0100111
0000000
0000000
0000000
Sample 8
0100111
0000000
0000000
0000000
Sample 9
0100111
0000000
0000000
0000000
Sample 10
1001101
0000000
0000000
0000000
Sample 11
1001101
0000000
0000000
0000000
Sample 12
1001101
0000000
0000000
0000000
Sample 13
1000101
0000000
0000000
0000000
Sample 14
1000101
0000000
0000000
0000000
Sample 15
1000101
0000000
0000000
0000000
Sample 16
1000010
0000000
0000000
0000000
The standard value of the SCAL[5:0] bits is `110110'. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
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Advance Information
Table 66: Transmit Waveform Value For T1 266~399 ft
UI 1
UI 2
UI 3
UI 4
Sample 1
0100100
1000010
0000000
0000000
Sample 2
0110001
0000000
0000000
0000000
Sample 3
0110001
0000000
0000000
0000000
Sample 4
0101110
0000000
0000000
0000000
Sample 5
0101011
0000000
0000000
0000000
Sample 6
0101010
0000000
0000000
0000000
Sample 7
0101010
0000000
0000000
0000000
Sample 8
0101001
0000000
0000000
0000000
Sample 9
0101001
0000000
0000000
0000000
Sample 10
1010010
0000000
0000000
0000000
Sample 11
1010010
0000000
0000000
0000000
Sample 12
1010010
0000000
0000000
0000000
Sample 13
1000111
0000000
0000000
0000000
Sample 14
1000111
0000000
0000000
0000000
Sample 15
1000111
0000000
0000000
0000000
Sample 16
1000010
0000000
0000000
0000000
The standard value of the SCAL[5:0] bits is `110110'. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
Table 67: Transmit Waveform Value For T1 399~533 ft
UI 1
UI 2
UI 3
UI 4
Sample 1
0101010
1000011
0000000
0000000
Sample 2
0110100
0000000
0000000
0000000
Sample 3
0110100
0000000
0000000
0000000
Sample 4
0110100
0000000
0000000
0000000
Sample 5
0101110
0000000
0000000
0000000
Sample 6
0101101
0000000
0000000
0000000
Sample 7
0101100
0000000
0000000
0000000
Sample 8
0101011
0000000
0000000
0000000