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Электронный компонент: 82V3011

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1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc.
JANUARY 9, 2003
DSC-6237/1
T1/E1/OC3 WAN PLL WITH
SINGLE REFERENCE INPUT
ADVANCE INFORMATION
IDT82V3011
FUNCTIONAL BLOCK DIAGRAM
TIE Control
Block
Input Frequency
Selection
F_sel0
F_sel1
Freerun
Normal Holdover
Fref
FLOCK
Invalid Input
Signal
Detection
MODE_sel0
MODE_sel1
TIE_en
Virtual
Reference
Feedback Signal
C16o
C8o
C4o
C2o
C3o
C1.5o
F0o
F8o
F16o
RSP
TSP
F19o
C6o
LOCK
F32o
C19POS
C19NEG
OSC
OSCi
TCLR
VDD
VSS
VSS
TDO TDI
JTAG
TMS
TRST
TCK
VDD
VSS
VDD
VDD VSS
RST
State Control Circuit
Reference
Input Monitor
MON_out
C32o
C19o
DPLL
C2/C1.5
FEATURES
Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum
4 Enhanced and Stratum 4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
Selectable input reference signal: 8 kHz, 1.544 MHz, 2.048 MHz
or 19.44 MHz
Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o
output clock signals
Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,
F32o, RSP and TSP
Provides a C2/C1.5 output clock signal with the frequency
controlled by the reference input Fref
Holdover frequency accuracy of 0.00625 ppm
Phase slope of 5 ns per 125 s
Attenuates wander from 2.1 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
MTIE of 600 ns
JTAG boundary scan
Holdover status indication
Freerun status indication
Normal status indication
Lock status indication
Input reference quality indication
3.3 V operation with 5 V tolerant I/O
Package available: 56 pin SSOP
2
IDT82V3011 T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION
The IDT82V3011 is a T1/E1/OC3 WAN PLL with single reference
input. It contains a Digital Phase-Locked Loop (DPLL), which generates
low jitter ST-BUS and 19.44 MHz clocks and framing signals that are
phase locked to 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input
reference.
The IDT82V3011 provides 9 types of clock signals (C1.5o, C3o, C6o,
C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o,
F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3
links.
The IDT82V3011 is compliant with AT&T TR62411, Telcordia GR-
1244-CORE Stratum 4 Enhanced and Stratum 4, and ETSI ETS 300
011. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic
jitter/wander, frequency accuracy, capture range, phase change slope,
holdover frequency accuracy and MTIE (Maximum Time Interval Error)
requirements for these specifications.
The IDT82V3011 can be used in synchronization and timing control
for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse
sources. It also can be used in access switch, access routers, ATM
edge switches, wireless base station controllers, or IADs (Integrated
Access Devices), PBXs, line cards and SONET/SDH equipments.
PIN CONFIGURATION
IDT82V3011
14
15
16
17
18
19
20
21
22
23
24
RST
MON_out
IC
Fref
F19o
OSCi
F8o
C1.5o
LOCK
C2o
C4o
FLOCK
F_sel1
F_sel0
C3o
C8o
C16o
C32o
F0o
F16o
1
2
3
4
5
6
7
8
9
10
11
12
13
56
55
54
RSP
TSP
C6o
V
DD
TDI
TMS
TRST
TDO
TCK
IC0
HOLDOVER
FREERUN
NORMAL
TIE_en
V
DD
V
SS
V
SS
C19o
MODE_sel0
MODE_sel1
TCLR
IC
25
26
27
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
28
29
V
DD
V
SS
V
DD
V
SS
F32o
V
SS
V
DD
C2/C1.5
IC2
IC
IC
C19NEG
C19POS
IC
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IDT82V3011 T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT INDUSTRIAL TEMPERATURE RANGE
TABLE OF CONTENTS
1
Pin Description...................................................................................................................................................................................................7
2
Functional Description ......................................................................................................................................................................................9
2.1
State Control Circuit ..................................................................................................................................................................................9
2.1.1
Normal Mode..............................................................................................................................................................................10
2.1.2
Fast Lock Mode..........................................................................................................................................................................10
2.1.3
Holdover Mode ...........................................................................................................................................................................10
2.1.4
Freerun Mode.............................................................................................................................................................................10
2.2
Frequency Select Circuit .........................................................................................................................................................................10
2.3
Reference Input Monitor ..........................................................................................................................................................................10
2.4
Invalid Input Signal Detection ..................................................................................................................................................................10
2.5
TIE Control Block.....................................................................................................................................................................................11
2.6
DPLL Block..............................................................................................................................................................................................13
2.6.1
Phase Detector (PHD)................................................................................................................................................................13
2.6.2
Limiter.........................................................................................................................................................................................13
2.6.3
Loop Filter ..................................................................................................................................................................................13
2.6.4
Fraction Block.............................................................................................................................................................................13
2.6.5
Digital Control Oscillator (DCO)..................................................................................................................................................13
2.6.6
Lock Indicator .............................................................................................................................................................................13
2.6.7
Output Interface..........................................................................................................................................................................13
2.7
OSC.........................................................................................................................................................................................................13
2.7.1
Clock Oscillator ..........................................................................................................................................................................13
2.8
JTAG .......................................................................................................................................................................................................14
2.9
Reset Circuit ............................................................................................................................................................................................14
3
Measures of Performance ...............................................................................................................................................................................15
3.1
Intrinsic Jitter ...........................................................................................................................................................................................15
3.2
Jitter Tolerance........................................................................................................................................................................................15
3.3
Jitter Transfer ..........................................................................................................................................................................................15
3.4
Frequency Accuracy................................................................................................................................................................................15
3.5
Holdover Accuracy ..................................................................................................................................................................................15
3.6
Capture Range ........................................................................................................................................................................................15
3.7
Lock Range .............................................................................................................................................................................................15
3.8
Phase Slope ............................................................................................................................................................................................15
3.9
Time Interval Error (TIE)..........................................................................................................................................................................15
3.10 Maximum Time Interval Error (MTIE) ......................................................................................................................................................15
3.11 Phase Continuity .....................................................................................................................................................................................16
3.12 Phase Lock Time.....................................................................................................................................................................................16
4
Absolute Maximum Ratings ............................................................................................................................................................................17
5
Recommended DC Operating Conditions .....................................................................................................................................................17
6
DC Electrical Characteristics..........................................................................................................................................................................17
6.1
Single End Input/Output Ports .................................................................................................................................................................17
6.2
Differential Output Port (LVDS) ...............................................................................................................................................................18
7
AC Electrical Characteristics..........................................................................................................................................................................19
7.1
Performance ............................................................................................................................................................................................19
7.2
Intrinsic Jitter Unfiltered ...........................................................................................................................................................................20
7.3
C1.5o (1.544 MHz) Intrinsic Jitter Filtered ...............................................................................................................................................20
7.4
C2o (2.048 MHz) Intrinsic Jitter Filtered ..................................................................................................................................................20
7.5
C19o (19.44 MHz) Intrinsic Jitter Filtered ................................................................................................................................................20
7.6
8 kHz Input to 8 kHz Output Jitter Transfer .............................................................................................................................................21
7.7
1.544 MHz Input to 1.544 MHz Output Jitter Transfer.............................................................................................................................21
7.8
2.048 MHz Input to 2.048 MHz Output Jitter Transfer.............................................................................................................................21
7.9
19.44 MHz Input to 19.44 MHz Output Jitter Transfer.............................................................................................................................22
7.10 8 kHz Input Jitter Tolerance.....................................................................................................................................................................22
4
IDT82V3011 T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT INDUSTRIAL TEMPERATURE RANGE
7.11 1.544 MHz Input Jitter Tolerance ............................................................................................................................................................22
7.12 2.048 MHz Input Jitter Tolerance ............................................................................................................................................................23
7.13 19.44 MHz Input Jitter Tolerance ............................................................................................................................................................23
8
Timing Characteristics ....................................................................................................................................................................................25
8.1
Timing Parameter Measurement Voltage Levels ....................................................................................................................................25
8.2
Input/Output Timing .................................................................................................................................................................................25
9
Ordering Information .......................................................................................................................................................................................30
5
IDT82V3011 T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT INDUSTRIAL TEMPERATURE RANGE
LIST OF FIGURES
Figure - 1
State Control Circuit ............................................................................................................................................................................ 9
Figure - 2
State Control Diagram......................................................................................................................................................................... 9
Figure - 3
TIE Control Block Diagram................................................................................................................................................................ 11
Figure - 4
Reference Switch with TIE Control Block Enabled............................................................................................................................ 11
Figure - 5
Reference Switch with TIE Control Block Disabled........................................................................................................................... 12
Figure - 6
DPLL Block Diagram......................................................................................................................................................................... 12
Figure - 7
Clock Oscillator Circuit ...................................................................................................................................................................... 14
Figure - 8
Power-Up Reset Circuit..................................................................................................................................................................... 14
Figure - 9
Timing Parameter Measurement Voltage Levels .............................................................................................................................. 25
Figure - 10
Input to Output Timing (Normal Mode).............................................................................................................................................. 27
Figure - 11
Output Timing 1................................................................................................................................................................................. 28
Figure - 12
Output Timing 2................................................................................................................................................................................. 29
Figure - 13
Input Control Setup and Hold Timing ................................................................................................................................................ 29