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Электронный компонент: 82V3012

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1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc.
JANUARY 9, 2003
DSC-6238/1
T1/E1/OC3 WAN PLL WITH
DUAL REFERENCE INPUTS
ADVANCE INFORMATION
IDT82V3012
FUNCTIONAL BLOCK DIAGRAM
OSC
Reference Input
Switch
TIE Control
Block
Reference Input
Monitor 0
OSCi
TCLR
VDD
VSS
VSS
C16o
C8o
C4o
C2o
C3o
C1.5o
F0o
F8o
F16o
RSP
TSP
F0_sel0
F0_sel1
Freerun
Normal Holdover
TDO TDI
MON_out0
Fref1
Fref0
IN_sel
Virtual
Reference
FLOCK
Invalid Input
Signal Detection
F19o
C6o
JTAG
LOCK
MODE_sel0
MODE_sel1
TIE_en
TMS
TRST
TCK
VDD
VSS
VDD
VDD VSS
RST
F32o
Feedback Signal
State Control Circuit
Reference Input
Monitor 1
MON_out1
C19POS
C19NEG
Frequency
Select Circuit 0
Frequency
Select Circuit 1
F1_sel0
F1_sel1
C32o
C19o
DPLL
C2/C1.5
FEATURES
Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum
3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces
Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface
and 2048 kbit/s interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz
Accepts two independent reference inputs which may have
same or different nominal frequencies applied to them
Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o
output clock signals
Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,
F32o, RSP and TSP
Provides a C2/C1.5 output clock signal with the frequency
controlled by the selected reference input Fref0 or Fref1
Holdover frequency accuracy of 0.00625 ppm
Phase slope of 5 ns per 125 s
Attenuates wander from 2.1 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
MTIE of 600 ns
JTAG boundary scan
Holdover status indication
Freerun status indication
Normal status indication
Lock status indication
Input reference quality indication
3.3 V operation with 5 V tolerant I/O
Package available: 56 pin SSOP
2
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION
The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference
inputs. It contains a Digital Phase-Locked Loop (DPLL), which
generates low jitter ST-BUS and 19.44 MHz clock and framing signals
that are phase locked to 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz
input reference.
The IDT82V3012 provides 9 types of clock signals (C1.5o, C3o, C6o,
C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o,
F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3
links.
The IDT82V3012 is compliant with AT&T TR62411, Telcordia GR-
1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4, ETSI ETS
300 011, ITU-T G.813 Option 1 for 2048 kbit/s interface, and ITU-T
G.812 Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interface.
It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/
wander, frequency accuracy, capture range, phase change slope,
holdover frequency accuracy and MTIE (Maximum Time Interval Error)
requirements for these specifications.
The IDT82V3012 can be used in synchronization and timing control
for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse
sources. It also can be used in access switch, access routers, ATM
edge switches, wireless base station controllers, or IADs (Integrated
Access Devices), PBXs, line cards and SONET/SDH equipments.
PIN CONFIGURATION
IDT82V3012
14
15
16
17
18
19
20
21
22
23
24
RST
MON_out0
Fref1
Fref0
F19o
OSCi
F8o
C1.5o
LOCK
C2o
C4o
FLOCK
F0_sel1
F0_sel0
C3o
C8o
C16o
C32o
F0o
F16o
1
2
3
4
5
6
7
8
9
10
11
12
13
56
55
54
RSP
TSP
C6o
V
DD
TDI
TMS
TRST
TDO
TCK
IC0
HOLDOVER
FREERUN
NORMAL
TIE_en
V
DD
V
SS
V
SS
C19o
MODE_sel0
MODE_sel1
TCLR
IN_sel
25
26
27
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
28
29
V
DD
V
SS
V
DD
V
SS
F32o
V
SS
V
DD
C2/C1.5
IC2
F1_sel0
F1_sel1
C19NEG
C19POS
MON_out1
3
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
TABLE OF CONTENTS
1
Pin Description...................................................................................................................................................................................................7
2
Functional Description ......................................................................................................................................................................................9
2.1
State Control Circuit ..................................................................................................................................................................................9
2.1.1
Normal Mode..............................................................................................................................................................................10
2.1.2
Fast Lock Mode..........................................................................................................................................................................10
2.1.3
Holdover Mode ...........................................................................................................................................................................10
2.1.4
Freerun Mode.............................................................................................................................................................................10
2.2
Frequency Select Circuit .........................................................................................................................................................................10
2.3
Reference Input Switch ...........................................................................................................................................................................10
2.4
Reference Input Monitor ..........................................................................................................................................................................11
2.5
Invalid Input Signal Detection ..................................................................................................................................................................11
2.6
TIE Control Block.....................................................................................................................................................................................11
2.7
DPLL Block..............................................................................................................................................................................................12
2.7.1
Phase Detector (PHD)................................................................................................................................................................12
2.7.2
Limiter.........................................................................................................................................................................................12
2.7.3
Loop Filter ..................................................................................................................................................................................13
2.7.4
Fraction Block.............................................................................................................................................................................13
2.7.5
Digital Control Oscillator (DCO)..................................................................................................................................................13
2.7.6
Lock Indicator .............................................................................................................................................................................13
2.7.7
Output Interface..........................................................................................................................................................................13
2.8
OSC.........................................................................................................................................................................................................14
2.8.1
Clock Oscillator ..........................................................................................................................................................................14
2.9
JTAG .......................................................................................................................................................................................................14
2.10 Reset Circuit ............................................................................................................................................................................................14
3
Measures of Performance ...............................................................................................................................................................................15
3.1
Intrinsic Jitter ...........................................................................................................................................................................................15
3.2
Jitter Tolerance........................................................................................................................................................................................15
3.3
Jitter Transfer ..........................................................................................................................................................................................15
3.4
Frequency Accuracy................................................................................................................................................................................15
3.5
Holdover Accuracy ..................................................................................................................................................................................15
3.6
Capture Range ........................................................................................................................................................................................15
3.7
Lock Range .............................................................................................................................................................................................15
3.8
Phase Slope ............................................................................................................................................................................................15
3.9
Time Interval Error (TIE)..........................................................................................................................................................................15
3.10 Maximum Time Interval Error (MTIE) ......................................................................................................................................................15
3.11 Phase Continuity .....................................................................................................................................................................................16
3.12 Phase Lock Time.....................................................................................................................................................................................16
4
Absolute Maximum Ratings ............................................................................................................................................................................17
5
Recommended DC Operating Conditions .....................................................................................................................................................17
6
DC Electrical Characteristics..........................................................................................................................................................................17
6.1
Single End Input/Output PortS ................................................................................................................................................................17
6.2
Differential Output Port (LVDS) ...............................................................................................................................................................18
7
AC Electrical Characteristics.........................................................................................................................................................................19
7.1
Performance ............................................................................................................................................................................................19
7.2
Intrinsic Jitter Unfiltered ...........................................................................................................................................................................20
7.3
C1.5o (1.544 MHz) Intrinsic Jitter Filtered ...............................................................................................................................................20
7.4
C2o (2.048 MHz) Intrinsic Jitter Filtered ..................................................................................................................................................20
7.5
C19o (19.44 MHz) Intrinsic Jitter Filtered ................................................................................................................................................20
7.6
8 kHz Input to 8 kHz Output Jitter Transfer .............................................................................................................................................21
7.7
1.544 MHz Input to 1.544 MHz Output Jitter Transfer.............................................................................................................................21
7.8
2.048 MHz Input to 2.048 MHz Output Jitter Transfer.............................................................................................................................21
7.9
19.44 MHz Input to 19.44 MHz Output Jitter Transfer.............................................................................................................................22
4
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
7.10 8 kHz Input Jitter Tolerance.....................................................................................................................................................................22
7.11 1.544 MHz Input Jitter Tolerance ............................................................................................................................................................22
7.12 2.048 MHz Input Jitter Tolerance ............................................................................................................................................................23
7.13 19.44 MHz Input Jitter Tolerance ............................................................................................................................................................23
8
Timing Characteristics ....................................................................................................................................................................................25
8.1
Timing Parameter Measurement Voltage Levels ....................................................................................................................................25
8.2
Input/Output Timing .................................................................................................................................................................................25
9
Ordering Information .......................................................................................................................................................................................30
5
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
LIST OF FIGURES
Figure - 1
State Control Circuit ............................................................................................................................................................................ 9
Figure - 2
State Control Diagram......................................................................................................................................................................... 9
Figure - 3
TIE Control Block Diagram................................................................................................................................................................ 11
Figure - 4
Reference Switch with TIE Control Block Enabled............................................................................................................................ 12
Figure - 5
Reference Switch with TIE Control Block Disabled........................................................................................................................... 12
Figure - 6
DPLL Block Diagram......................................................................................................................................................................... 13
Figure - 7
Clock Oscillator Circuit ...................................................................................................................................................................... 14
Figure - 8
Power-Up Reset Circuit..................................................................................................................................................................... 14
Figure - 9
Timing Parameter Measurement Voltage Levels .............................................................................................................................. 25
Figure - 10
Input to Output Timing (Normal Mode).............................................................................................................................................. 27
Figure - 11
Output Timing 1................................................................................................................................................................................. 28
Figure - 12
Output Timing 2................................................................................................................................................................................. 29
Figure - 13
Input Control Setup and Hold Timing ................................................................................................................................................ 29
6
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
LIST OF TABLES
Table - 1
Operating Modes Selection..................................................................................................................................................................9
Table - 2
Fref0 Frequency Selection .................................................................................................................................................................10
Table - 3
Fref1 Frequency Selection .................................................................................................................................................................10
Table - 4
Input Reference Selection..................................................................................................................................................................11
Table - 5
C2/C1.5 Output Frequency Control....................................................................................................................................................14
7
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
1
PIN DESCRIPTION
Name
Type
Pin Number
Description
V
SS
Power
12, 18, 27
38, 47
Ground.
0 V. All V
SS
pins should be connected to the ground.
V
DD
Power
13, 19, 26
37, 48
Positive Supply Voltage.
All V
DD
pins should be connected to +3.3 V (nominal).
OSCi
(CMOS) I
50
Oscillator Master Clock Input.
This pin is connected to a clock source.
Fref0
Fref1
I
5
6
Reference Input 0 and Reference Input 1.
These are two input reference sources (falling edge of 8 kHz, 1.544 MHz and 2.048 MHz or rising edge of 19.44
MHz) used for synchronization. The IN_sel pin selects one of the two reference inputs to be used. See
Table - 4
for
details.
The frequency of the reference inputs can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. These two pins are
internally pulled up to V
DD
.
IN_sel
I
11
Input Reference Selection.
A logic low at this pin selects Reference Input 0 (Fref0) and a logic high at this pin selects Reference Input 1 (Fref1).
The logic level on this input is gated in by the rising edges of F8o. This Pin is internally pulled down to V
SS
.
F0_sel0
F0_sel1
I
9
10
Frequency Selection Inputs for Fref0.
These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the
Reference Input 0 (Fref0). See
Table - 2
for details.
F1_sel0
F1_sel1
I
35
34
Frequency Selection Inputs for Fref1.
These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the
Reference Input 1 (Fref1). See
Table - 3
for details.
MODE_sel0
MODE_sel1
I
1
2
Mode Selection Inputs.
These two inputs determine the operating mode of the IDT82V3012 (Normal, Holdover or Freerun). See
Table - 1
for
details.
The logic levels on these two pins are gated in by the rising edges of F8o. These two pins are internally pulled down
to V
SS
.
RST
I
4
Reset Input.
Pulling this pin to logic low for at least 300 ns will reset the IDT82V3012. While the RST pin is low, all framing and
clock outputs are at logic high.
To ensure proper operation, the device must be reset after it is powered up.
TCLR
I
3
TIE Control Block Reset.
Pulling this pin to logic low for at least 300 ns will reset the TIE (Maximum Time Interval Error) control block and
result in a realignment of the output phase with the input phase. This pin is internally pulled up to V
DD
.
TIE_en
I
56
TIE Control Block Enable.
A logic high at this pin enables the TIE control block while a logic low disables it. The logic level on this input is gated
in by the rising edges of F8o. This pin is internally pulled up to V
DD
.
FLOCK
I
45
Fast Lock Mode Enable.
When setting this pin to logic high, the DPLL will quickly lock to the input reference within 500 ms.
LOCK
(CMOS) O
44
Lock Indicator.
This output pin goes high when the DPLL is frequency locked to the input reference.
HOLDOVER
(CMOS) O
52
Holdover Indicator.
This output pin goes high whenever the DPLL enters Holdover mode.
NORMAL
(CMOS) O
46
Normal Indicator.
This output pin goes high whenever the DPLL enters Normal mode.
FREERUN
(CMOS) O
51
Freerun Indicator.
This output pin goes high whenever the DPLL enters Freerun mode.
MON_out0
O
7
Frequency Out-of-range Indicator for Fref0.
A logic high at this pin indicates that Fref0 is off the nominal frequency by more than 12ppm.
MON_out1
O
8
Frequency Out-of-range Indicator for Fref1.
A logic high at this pin indicates that Fref1 is off the nominal frequency by more than 12ppm.
C19POS
C19NEG
(LVDS) O
21
22
19.44 MHz Clock Output (LVDS Level).
This pair of outputs are used for OC3/STS3 applications.
C19o
(CMOS) O
43
19.44 MHz Clock Output (CMOS Level).
This output is used for OC3/STS3 applications.
8
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
C32o
(CMOS) O
25
32.768 MHz Clock Output.
This output is used for ST-BUS operation with a 32.768 MHz clock.
C16o
(CMOS) O
24
16.384 MHz Clock Output.
This output is used for ST-BUS operation with a 16.384 MHz clock.
C8o
(CMOS) O
23
8.192 MHz Clock Output.
This output is used for ST-BUS operation with an 8.192 MHz clock.
C4o
(CMOS) O
20
4.096 MHz Clock Output.
This output is used for ST-BUS operation with a 4.096 MHz clock.
C2o
(CMOS) O
17
2.048 MHz Clock Output.
This output is used for ST-BUS operation with a 2.048 MHz clock.
C3o
(CMOS) O
16
3.088 MHz Clock Output.
This output is used for T1 applications.
C1.5o
(CMOS) O
15
1.544 MHz Clock Output.
This output is used for T1 applications.
C6o
(CMOS) O
14
6.312 MHz Clock Output.
This output is used for DS2 applications.
C2/C1.5
(CMOS) O
54
2.048 MHz or 1.544 MHz Clock Output.
This output is a 2.048 MHz or 1.544 MHz clock signal. If the frequency of the selected reference input (Fref0 or
Fref1) is 8 kHz, 2.048 MHz, or 19.44 MHz, the C2/C1.5 pin outputs a 2.048 MHz clock signal. If the frequency of the
selected reference input (Fref0 or Fref1) is 1.544 MHz, the C2/C1.5 pin outputs a 1.544 MHz clock signal. Refer to
Table - 5
for details.
F19o
(CMOS) O
49
8 kHz Frame Signal with 19.44 MHz Pulse Width.
This output is used for OC3/STS3 applications.
F32o
(CMOS) O
40
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 30 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing signal
is typically used for ST-BUS operation at 8.192 Mb/s.
F16o
(CMOS) O
39
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing signal
is typically used for ST-BUS operation at 8.192 Mb/s.
F8o
(CMOS) O
36
Frame Pulse.
This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame.
F0o
(CMOS) O
33
Frame Pulse ST-BUS 2.048 Mb/s.
This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing
signal is typically used for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s.
RSP
(CMOS) O
41
Receive Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of a ST-BUS frame. This framing
signal is typically used for connection to the Siemens MUNICH-32 device.
TSP
(CMOS) O
42
Transmit Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This framing is
typically used for connection to the Siemens MUNICH-32 device.
TDO
(CMOS) O
29
Test Serial Data Out.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when
JTAG scan is not enabled.
TDI
I
32
Test Serial Data In.
JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to V
DD
.
TRST
I
30
Test Reset.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is internally
pulled up to V
DD
. It is connected to the ground for normal applications.
TCK
I
28
Test Clock.
Provides the clock for the JTAG test logic. This pin is internally pulled up to V
DD
.
TMS
I
31
Test Mode Select.
JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to V
DD
.
IC0, IC2
-
53, 55
These pins should be connected to V
SS
.
Name
Type
Pin Number
Description
9
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
2
FUNCTIONAL DESCRIPTION
The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference
inputs, providing timing (clock) and synchronization (framing) signals to
interface circuits for multitrunk T1/E1 and STS3/OC3 links. The details
are described in the following sections.
2.1
STATE CONTROL CIRCUIT
The State Control Circuit is an important part in the IDT82V3012. It is
used to control the TIE block and the DPLL block as shown in
Figure - 1.
The control is based on the result of Invalid Input Signal Detection and
the logic levels on the inputs MODE_sel0, MODE_sel1, IN_sel and
TIE_en.
The IDT82V3012 can be operated in three different modes: Normal,
Holdover and Freerun. The operating mode is selected by the
MODE_sel1 and MODE_sel0 pins as shown in
Table - 1.
Figure - 2
shows the state control diagram. All state changes occur
synchronously on the rising edge of F8o. The three operating modes,
Normal (S1), Holdover (S3) and Freerun (S0) can be switched from one
to another by changing the logic levels on the MODE_sel0 and
MODE_sel1 pins.
Figure - 1 State Control Circuit
Figure - 2 State Control Diagram
Table - 1 Operating Modes Selection
Mode Selection Pins
Operating Mode
MODE_sel1
MODE_sel0
0
0
Normal
0
1
Holdover
1
0
Freerun
1
1
Reserved
State Control Circuit
MODE_sel1 MODE_sel0
TIE_en
Output of the
Invalid Input
Signal Detection
F8o
TIE Block
Enable/Disable
DPLL Block
Mode Control
IN_sel
S1
Normal
Mode_sel1 = 0
Mode_sel0 = 0
S3
Holdover
Mode_sel1 = 0
Mode_sel0 = 1
S0
Freerun
Mode_sel1 = 1
Mode_sel0 = 0
(Invalid Input Reference Signal)
(Valid Input Reference Signal)
Aut
o T
IE D
isab
le
Aut
o T
IE D
isab
le
TIE Enable (TIE_en = H)
AutoT
IE Dis
able
AutoTIE
Disable
Au
to
TIE
Di
sab
le
TIE
Dis
able
(TIE
_en
= L
)
AutoT
IE Dis
able
TIE E
nable
(TIE
_en =
H)
Reset *
S4
Short Time Holdover
Mode_sel1 = 0
Mode_sel0 = 0
IN_
sel T
ran
sie
nt
Auto
TIE
Dis
able
No IN
_sel T
ransie
nt
TIE E
nable
(TIE
_en =
H)
No
IN
_s
el T
ran
sie
nt
TIE
D
isa
ble
(T
IE
_e
n =
L)
IN_s
el Tra
nsien
t
Auto
TIE D
isable
S2
Auto - Holdover
Mode_sel1 = 0
Mode_sel0 = 0
* Note: After reset, the Mode_sel1 and Mode_sel0 should be initially set to '10' or '00'.
Auto TIE Disable
(Valid Input Reference Signal)
TIE Disable (TIE_en = L)
10
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
The mode changes between Normal (S1) and Auto-Holdover (S2)
are triggered by the Invalid Input Reference Detection Circuit and
irrelative to the logic levels on the MODE_sel0 and MODE_sel1 pins. At
the stage of S1, if the input reference is invalid (out of the capture
range), the operating mode will be changed to Auto-Holdover (S2)
automatically. At the stage of S2, if no IN_sel transient occurs and the
input reference becomes valid, the operating mode will be changed back
to Normal (S1) automatically. If an IN_sel transient is detected at the
stage of S2, the operating mode will be changed to Short Time Holdover
(S4) with the TIE Control Block automatically disabled. Refer to
"2.5
Invalid Input Signal Detection"
for more information.
The mode changes between Normal (S1) and Short Time Holdover
(S4) are triggered by the IN_sel transient. At the stage of S1, if a voltage
transient occurs on the IN_sel pin, the operating mode will be changed
to Short Time Holdover (S4) automatically. At the stage of S4, if no
voltage transient occurs on the IN_sel pin, the operating mode will be
changed back to S1 automatically. See
"2.3 Reference Input Switch"
for
details.
When changing the operating mode, the TIE control block is enabled/
disabled automatically by the state control circuit as shown along the
lines in
Figure - 2
, except for the changes from Normal (S1) to Auto-
Holdover (S2), and from Auto-Holdover (S2), Holdover (S3) and Short
Time Holdover (S4) to Normal (S1). During these four changes, the TIE
control block can be enabled or disabled, depending on the logic level
on the TIE_en pin.
2.1.1
NORMAL MODE
The Normal mode is typically used when a slave clock source
synchronized to the network is required.
In this mode, the IDT82V3012 provides timing (C1.5o, C3o, C2o,
C4o, C8o, C16o, C19o, C32o) and synchronization (F0o, F8o, F16o,
F19o, F32o, TSP, RSP) signals. All these signals are synchronous to
one of the two input references. The nominal frequency of the input
reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz.
After reset, the IDT82V3012 will take maximum 30 seconds to make
the output signals synchronous (phase locked) to the input reference.
Whenever the IDT82V3012 enters Normal mode, the NORMAL pin is
set to logic high.
2.1.2
FAST LOCK MODE
The Fast Lock mode is a submode of the Normal mode. It allows the
DPLL to lock to a reference more quickly than in the Normal mode.
Typically, the locking time in the Fast Lock mode is less than 500 ms.
When the FLOCK pin is set to high, the Fast Lock mode will be
enabled.
2.1.3
HOLDOVER MODE
The Holdover mode is typically used for short duration (e.g., 2
seconds) while network synchronization is temporarily disrupted.
In the Holdover mode, the IDT82V3012 provides timing and
synchronization signals that are not locked to an external reference
signal, but are based on storage techniques. In the Normal mode, when
the output frequency is locked to the input reference signal, a numerical
value corresponding to the output frequency is stored alternately in two
memory locations every 30 ms. When the device is switched to the
Holdover mode, the stored value from between 30 ms and 60 ms is used
to set the output frequency of the device.
The frequency accuracy of the Holdover mode is 0.00625 ppm,
which corresponds to a worst case of 18 frame (125 s per frame) slips
in 24 hours. This meets the AT&T TR62411 and Telcordia GR-1244-
CORE Stratum 3 requirement of 0.37 ppm (255 frame slips per 24
hours).
Whenever the IDT82V3012 goes into the Holdover mode, the
HOLDOVER pin is set to logic high.
2.1.4
FREERUN MODE
The Freerun mode is typically used when a master clock source is
required, or used when a system is just powered up and the network
synchronization has not been achieved.
In this mode, the IDT82V3012 provides timing and synchronization
signals which are based on the master clock frequency (OSCi) only, and
are not synchronized to the input reference signal.
The accuracy of the output clock is equal to the accuracy of the
master clock (OSCi). So if a 32 ppm output clock is required, the
master clock must also be 32 ppm. Refer to
"2.8 OSC"
for more
information.
Whenever the IDT82V3012 enters the Freerun mode, the FREERUN
pin is set to logic high.
2.2
FREQUENCY SELECT CIRCUIT
The frequency of the input reference can be 8 kHz, 1.544 MHz, 2.048
MHz or 19.44 MHz. The F0_sel1 and F0_sel0 pins select one of the four
frequencies for the reference input 0 (Fref0). The F1_sel1 and F1_sel0
pins select one of the four frequencies for the reference input 1 (Fref1).
See
Table - 2
and
Table - 3
for details.
The reference inputs Fref0 and Fref1 may have different frequencies
applied to them. Every time the frequency selection is changed, the
device must be reset to make the change effective.
2.3
REFERENCE INPUT SWITCH
The IDT82V3012 accepts two simultaneous reference signals Fref0
Table - 2 Fref0 Frequency Selection
Frequency Selection Pins
Fref0 Input Frequency
F0_sel1
F0_sel0
0
0
19.44 MHz
0
1
8 kHz
1
0
1.544 MHz
1
1
2.048 MHz
Table - 3 Fref1 Frequency Selection
Frequency Selection Pins
Fref1 Input Frequency
F1_sel1
F1_sel0
0
0
19.44 MHz
0
1
8 kHz
1
0
1.544 MHz
1
1
2.048 MHz
11
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
and Fref1, and operates on the falling edge (8 kHZ, 1.544 MHz and
2.048 MHz) or rising edge (19.44 MHz). The IN_sel pin selects one of
the two reference signals as input to the device. See
Table - 4
. The
selected reference signal is sent to the TIE control block, Reference
Input Monitor and Invalid Input Signal Detection block for further
processing.
When a transient voltage occurs at the IN_sel pin, the operating
mode will be changed to Short Time Holdover (S4) with the TIE Control
Block automatically disabled. At the stage of S4, if no IN_sel transient
occurs, the reference signal will be switched from one to the other, and
the operating mode will be changed back to Normal (S1) automatically.
During the change from S4 to S1, the TIE Control Block can be enabled
or disabled, depending on the logic level on the TIE_en pin. See
Figure -
2
for details.
2.4
REFERENCE INPUT MONITOR
The Telcordia GR-1244-CORE standard recommends that the DPLL
should be able to reject the references that are off the nominal
frequency by more than 12 ppm. The IDT82V3012 monitors the Fref0
and Fref1 frequencies and outputs two signals (MON_out0 and
MON_out1) to indicate the monitoring results. Whenever the Fref0
frequency is off the nominal frequency by more than 12 ppm, the
MON_out0 pin goes high. The MON_out1 pin indicates the monitoring
result of Fref1 in the same way. The MON_out0 and MON_out1 signals
are updated every 2 second.
2.5
INVALID INPUT SIGNAL DETECTION
This circuit is used to detect if the selected input reference (Fref0 or
Fref1) is out of the capture range (refer to
"3.6 Capture Range"
for
details). This includes a complete loss of the input reference and a large
frequency shift in the input reference.
If the input reference is invalid (out of the capture range), the
IDT82V3012 will be automatically switched to the Holdover mode (Auto-
Holdover). When the input reference becomes valid, the device will be
switched back to the Normal mode and the output signals will be locked
to the input reference.
In the Holdover mode, the output signals are based on the input
reference signal 30 ms to 60 ms prior to entering the Holdover mode.
The amount of phase drift while in holdover can be negligible because
the Holdover mode is very accurate (e.g., 0.00625 ppm). Consequently,
the phase delay between the input and output after switching back to the
Normal mode is preserved.
2.6
TIE CONTROL BLOCK
If the current reference is badly damaged or lost, it is necessary to
use the other reference or the one generated by storage techniques
instead. But, when switching the reference, a step change in phase on
the input reference will occur. A step change in phase in the DPLL input
may lead to an unacceptable phase change on the output signals. The
TIE control block, when enabled, prevents a step change in phase on
the input reference signals from causing a step change in phase on the
output of the DPLL block.
Figure - 3
shows the TIE Control Block
diagram.
Figure - 3 TIE Control Block Diagram
When the TIE Control Block is enabled (by the TIE_en pin or TIE
auto-enable logic generated by the State Control Circuit), it works under
the control of the Step Generation circuit.
At the Measure Circuit stage, the selected reference signal (Fref) is
compared with the feedback signal (current output, fed back from the
Frequency Select Circuit). The phase difference between the Fref and
the feedback signal is stored in the Storage Circuit for TIE correction.
Based on the value of the phase difference, the Trigger Circuit
generates a virtual reference with the same phase as the previous
reference. In this way, the reference can be switched without generating
a step change in phase.
Figure - 4
shows the phase transient that will result if a reference
switch is performed with the TIE Control Block enabled.
The value of the phase difference in the Storage Circuit can be
cleared by applying a logic low reset signal to the TCLR pin. The
minimum width of the reset pulse should be 300 ns.
When the IDT82V3012 primarily enters the Holdover mode for a
short time period and then returns back to the Normal mode, the TIE
Control Circuit should not be enabled. This will prevent unwanted
accumulated phase change between the input and output.
If the TIE Control Block is disabled (by the TIE_en pin or TIE auto-
disable logic generated by the State Control Circuit), a reference switch
will result in a phase alignment between the input signal and the output
signal as shown in
Figure - 5
. The slope of the phase adjustment is
limited to 5 ns per 125 s.
Table - 4 Input Reference Selection
IN_sel
Input Reference
0
Fref0
1
Fref1
Step Generation
TIE_en
Reference
Select Circuit
Fref0
Fref1
IN_sel
Measure
Circuit
Storage
Circuit
Trigger
Circuit
Feedback
Signal
TCLR
Fref
Virtual
Reference
Signal
12
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
Figure - 4 Reference Switch with TIE Control Block Enabled
Figure - 5 Reference Switch with TIE Control Block Disabled
2.7
DPLL BLOCK
As shown in
Figure - 6
, the DPLL Block consists of a Phase Detector,
a Limiter, a Loop Filter, a Digital Control Oscillator and Divider Circuits.
2.7.1
PHASE DETECTOR (PHD)
In the Normal mode, the Phase Detector compares the virtual
reference signal from the TIE Control Circuit with the feedback signal
from the Frequency Select Circuit, and outputs an error signal
corresponding to the phase difference. This error signal is sent to the
Limiter circuit for phase slope control.
In the Freerun or Holdover mode, the Frequency Select Circuit, the
Phase Detector and the Limiter are inactive, and the input reference
signal is not used.
2.7.2
LIMITER
The Limiter is used to limit the phase slope. It ensures that the
maximum output phase slope is limited to 5ns per 125
s for all input
transient conditions. This well meets the AT&T TR62411 and Telcordia
GR-1244-CORE specifications, which specify the maximum phase slope
of 7.6 ns per 125 s and 81 ns per 1.326 ms, respectively.
Input Clock
125
s
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
Input Clock
125
s
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
13
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
Figure - 6 DPLL Block Diagram
In the Normal mode, the Limiter receives the error signal from the
Phase Detector, limits the phase slope within 5 ns per 125 s and sends
the limited signal to the Loop Filter.
In the Fast Lock mode, the Limiter is disabled, and the DPLL locks to
the input reference within 500 ms, which is much shorter than that in the
Normal mode.
2.7.3
LOOP FILTER
The Loop Filter ensures that the jitter transfer meets the ETS 300
011 and AT&T TR624411 requirements. It works similarly to a first order
low pass filter with 2.1 Hz cutoff frequency for the four valid input
frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz).
The output of the Loop Filter goes directly or through the Fraction
blocks to the Digital Control Oscillator, where E1, T1, C6 and C19
signals are generated.
2.7.4
FRACTION BLOCK
By applying some algorithms on the incoming E1 signal, the
Fraction_C19, Fraction_C6 and Fraction_T1 blocks generate C19, C6
and T1 signals respectively.
2.7.5
DIGITAL CONTROL OSCILLATOR (DCO)
In the Normal mode, the DCO receives the four limited and filtered
signals from Loop Filter or Fraction blocks. Based on the values of the
received signals, the DCO generates four digital outputs: 19.44 MHz,
25.248 MHz, 32.768 MHz and 24.704 MHz for C19, C6, E1 and T1
dividers, respectively.
In the Holdover mode, the DCO is running with the signal generated
by storage techniques.
In the Freerun mode, the DCO is running with the master frequency
signal generated by OSC.
2.7.6
LOCK INDICATOR
If the output frequency of the DPLL is identical to the input frequency,
and the input phase offset is small enough so that no slope limiting is
exhibited, the LOCK pin will be set high.
2.7.7
OUTPUT INTERFACE
The Output Interface uses the three output signals of the DCO to
generate totally 9 types of clock signals and 7 types of framing signals
All these output signals are synchronous to F8o.
Digit
a
l Co
nt
ro
l Os
cilla
tor
C32o
C16o
C8o
C4o
C2o
C3o
C6o
F0o
F8o
RSP
TSP
F16o
C1.5o
F32o
Output Interface
T1_Divider
E1_Divider
C6_Divider
Frequency
Selection
Circuit 1
Phase
Detector
Virtual Reference
Fraction_C6
Fraction_T1
24.704 MHz
32.768 MHz
25.248 MHz
Feedback Signal
Limiter
FLOCK
F1_sel1 F1_sel0
C19_Divider
155.52 MHz
F19o
C19o
APLL
19.44 MHz
Fraction_C19
C19NEG
C19POS
IN_sel
F0_sel1 F0_sel0
Frequency
Selection
Circuit 0
C2/C1.5
Loop Filter
Fx_sel1 Fx_sel0 (x = 0 or 1)
14
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
The 32.768 MHz signal is used by the E1_divider circuit to generate
five types of clock signals (C2o, C4o, C8o, C16o and C32o) with
nominal 50% duty cycle and six types of framing signals (F0o, F8o,
F16o, F32o, RSP and TSP).
The 24.704 MHz signal is used by the T1_divider circuit to generate
two types of T1 signals (C1.5o and C3o) with nominal 50% duty cycle.
The 25.248 MHz signal is used by the C6_divider circuit to generate
a C6o signal with nominal 50% duty cycle.
The 19.44 MHz signal is sent to an APLL, which outputs a 155.52
MHz signal. The 155.52 MHz signal is used by the C19_divider circuit to
generate 19.44 MHz clock signals (C19o, C19POS and C19NEG) with
nominal 50% duty cycle and a framing signal F19o.
Additionally, the IDT82V3012 provides an output clock (C2/C1.5)
with the frequency controlled by the frequency selection pins Fx_sel0
and Fx_sel1 (see
Table - 5
for details). If the frequency of the selected
reference input (Fref0 or Fref1) is 8 kHz, 2.048 MHz or 19.44 MHz, the
C2/C1.5 pin outputs a 2.048 MHz clock signal. If the frequency of the
selected reference input (Fref0 or Fref1) is 1.544 MHz, the C2/C1.5 pin
outputs a 1.544 MHz clock signal. The electrical and timing
characteristics of this output (2.048MHz or 1.544 MHz) is as same as
that of C2o or C1.5o.
2.8
OSC
The IDT82V3012 can use a clock as the master timing source. In the
Freerun mode, the frequency tolerance of the clock outputs is identical
to the frequency tolerance of the source at the OSCi pin. For
applications not requiring an accurate Freerun mode, the tolerance of
the master timing source may be 100 ppm. For applications requiring
an accurate Freerun mode, such as AT&T TR62411, the tolerance of the
master timing source must be no greater than 32 ppm.
Another consideration in determining the accuracy of the master
timing source is the desired capture range. The sum of the accuracy of
the master timing source and the capture range of the IDT82V3012 will
always equal 230 ppm. For example, if the master timing source is 100
ppm, then the capture range will be 130 ppm.
2.8.1
CLOCK OSCILLATOR
When selecting a Clock Oscillator, numerous parameters must be
considered. This includes absolute frequency, frequency change over
temperature, output rise and fall times, output levels and duty cycle.
For applications requiring 32 ppm clock accuracy, the following
clock oscillator module may be used.
FOX F7C-2E3-20.0 MHz
Frequency:
20.0 MHz
Tolerance:
25 ppm 0
C to 70C
Rise & Fall Time: 10 ns (0.33 V, 2.97 V, 15 pF)
Duty Cycle:
40% to 60%
For Stratum 3 application, the clock oscillator should meet the
following requirements:
Frequency:
20.0 MHz
Tolerance:
4.6 ppm over 20 years life time
Drift:
0.04 ppm per day @ constant temperature
0.3 ppm over temperature range of 0 to 70
C
The output clock should be connected directly (not AC coupled) to
the OSCi input of the IDT82V3012, as shown in
Figure - 7
.
Figure - 7 Clock Oscillator Circuit
2.9
JTAG
The IDT82V3012 supports IEEE 1149.1 JTAG Scan.
2.10
RESET CIRCUIT
A simple power-up reset circuit with about 50 s logic low reset pulse
is shown in
Figure - 8
.
The resistor Rp is for protection only and limits current into the RST
pin during power down conditions. The logic low reset pulse width is not
critical but should be greater than 300 ns.
Figure - 8 Power-Up Reset Circuit
Table - 5 C2/C1.5 Output Frequency Control
Frequency Selection Pins
Frefx Input
Frequency
C2/C1.5 Output
Frequency
Fx_sel1
Fx_sel0
0
0
19.44 MHz
2.048 MHz
0
1
8 kHz
2.048 MHz
1
0
1.544 MHz
1.544 MHz
1
1
2.048 MHz
2.048 MHz
Note: `x' is 0 or 1, selected by the IN_sel pin.
IN_sel = 0: x = 0, Fref0 is the selected reference input. The frequency of Fref0
is selected by F0_sel0 and F0_sel1.
IN_sel = 1: x = 1, Fref1 is the selected reference input. The frequency of Fref1
is selected by F1_sel0 and F1_sel1.
+3.3 V
20 MHz OUT
GND
+3.3 V
OSCi
IDT82V3012
0.1
F
3.3 V
R
10 k
Rp
1 k
C
1
F
RST
IDT82V3012
15
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
3
MEASURES OF PERFOR-
MANCE
The following are some synchronizer performance indicators and
their corresponding definitions.
3.1
INTRINSIC JITTER
Intrinsic jitter is the jitter produced by the synchronizing circuit and is
measured at its output. It is measured by applying a reference signal
with no jitter to the input of the device, and measuring its output jitter.
Intrinsic jitter may also be measured when the device is in a non-
synchronizing mode, such as free running or holdover, by measuring the
output jitter of the device. Intrinsic jitter is usually measured with various
band limiting filters depending on the applicable standards. For the
IDT82V3012, the intrinsic Jitter is limited to less than 0.02 UI on the
2.048 MHz and 1.544 MHz clocks.
3.2
JITTER TOLERANCE
Jitter tolerance is a measure of the ability of a DPLL to operate
properly (i.e., remain in lock and or regain lock in the presence of large
jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and jitter frequency depends on
the applicable standards.
3.3
JITTER TRANSFER
Jitter transfer or jitter attenuation refers to the magnitude of jitter at
the output of a device for a given amount of jitter at the input of the
device. Input jitter is applied at various amplitudes and frequencies, and
output jitter is measured with various filters depending on the applicable
standards.
For the IDT82V3012, two internal elements determine the jitter
attenuation. This includes the internal 2.1 Hz low pass loop filter and the
phase slope limiter. The phase slope limiter limits the output phase
slope to 5 ns per 125 s. Therefore, if the input signal exceeds this rate,
such as for very large amplitude, low frequency input jitter, the maximum
output phase slope will be limited (i.e., attenuated) to 5 ns per 125 s.
The IDT82V3012 has 16 outputs with 4 possible input frequencies for
a total of 39 possible jitter transfer functions. Since all outputs are
derived from the same signal, the jitter transfer values for the four cases,
8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz, 2.048 MHz to 2.048 MHz and
19.44 MHz to 19.44 MHz can be applied to all outputs.
It should be noted that 1 UI at 1.544 MHz is 644 ns, which is not
equal to 1 UI at 2.048 MHz, which is 488 ns. Consequently, a transfer
value using different input and output frequencies must be calculated in
common units (e.g., seconds).
Using the above method, the jitter attenuation can be calculated for
all combinations of inputs and outputs based on the four jitter transfer
functions provided. Note that the resulting jitter transfer functions for all
combinations of inputs (8 kHz, 1.544 MHz, 2.048 MHz, 19.44 MHz) and
outputs (8 kHz, 1.544 MHz, 3.088 MHz, 6.312 MHz, 2.048 MHz, 4.096
MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz, 32.768 MHz) for a given
input signal (jitter frequency and jitter amplitude) are the same.
Since intrinsic jitter is always present, jitter attenuation will appear to
be lower for small input jitter signals than for large ones. Consequently,
accurate jitter transfer function measurements are usually made with
large input jitter signals (e.g., 75% of the specified maximum jitter
tolerance).
3.4
FREQUENCY ACCURACY
Frequency accuracy is defined as the absolute tolerance of an output
clock signal when it is not locked to an external reference, but is
operating in a free running mode. For the IDT82V3012, the Freerun
accuracy is equal to the Master Clock (OSCi) accuracy.
3.5
HOLDOVER ACCURACY
Holdover accuracy is defined as the absolute tolerance of an output
clock signal, when it is not locked to an external reference signal, but is
operating using storage techniques. For the IDT82V3012, the storage
value is determined while the device is in Normal mode and locked to an
external reference signal.
The absolute Master Clock (OSCi) accuracy of the IDT82V3012 does
not affect Holdover accuracy, but the change in OSCi accuracy while in
Holdover mode does.
3.6
CAPTURE RANGE
Also referred to as pull-in range. This is the input frequency range
over which the synchronizer must be able to pull into synchronization.
The IDT82V3012 capture range is equal to 230 ppm minus the
accuracy of the master clock (OSCi). For example, a 32 ppm master
clock results in a capture range of 198 ppm.
The Telcordia GR-1244-CORE standard, recommends that the DPLL
should be able to reject references that are off the nominal frequency by
more than 12 ppm. The IDT82V3012 provides two pins, MON_out0
and MON_out1, to respectively indicate whether the reference inputs
Fref0 and Fref1 are within the 12 ppm of the nominal frequency.
3.7
LOCK RANGE
This is the input frequency range over which the synchronizer must
be able to maintain synchronization. The lock range is equal to the
capture range for the IDT82V3012.
3.8
PHASE SLOPE
Phase slope is measured in seconds per second and is the rate at
which a given signal changes phase with respect to an ideal signal. The
given signal is typically the output signal. The ideal signal is of constant
frequency and is nominally equal to the value of the final output signal or
final input signal.
3.9
TIME INTERVAL ERROR (TIE)
TIE is the time delay between a given timing signal and an ideal
timing signal.
3.10
MAXIMUM TIME INTERVAL ERROR (MTIE)
MTIE is the maximum peak to peak delay between a given timing
signal and an ideal timing signal within a particular observation period.
16
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
3.11
PHASE CONTINUITY
Phase continuity is the phase difference between a given timing
signal and an ideal timing signal at the end of a particular observation
period. Usually, the given timing signal and the ideal timing signal are of
the same frequency. Phase continuity applies to the output of the
synchronizer after a signal disturbance due to a mode change. The
observation period is usually the time from the disturbance, to just after
the synchronizer has settled to a steady state.
In the case of the IDT82V3012, the output signal phase continuity is
maintained to within 5 ns at the instance (over one frame) of all mode
changes. The total phase shift, depending on the type of mode change,
may accumulate up to 200 ns over many frames. The rate of change of
the 200 ns phase shift is limited to a maximum phase slope of
approximately 5 ns per 125 s. This meets the AT&T TR62411
maximum phase slope requirement of 7.6 ns per 125 s and Telcordia
GR-1244-CORE (81 ns per 1.326 ms).
3.12
PHASE LOCK TIME
This is the time it takes the synchronizer to phase lock to the input
signal. Phase lock occurs when the input signal and output signal are
not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many
factors including:
1. Initial input to output phase difference
2. Initial input to output frequency difference
3. Synchronizer loop filter
4. Synchronizer limiter
Although a short lock time is desirable, it is not always possible to
achieve due to other synchronizer requirements. For instance, better
jitter transfer performance is achieved with a lower frequency loop filter
which increases lock time. And better (smaller) phase slope
performance (limiter) results in longer lock times. The IDT82V3012 loop
filter and limiter are optimized to meet the AT&T TR62411 jitter transfer
and phase slope requirements. Consequently, phase lock time, which is
not a standard requirement, may be longer than in other applications.
See
"7.1 Performance"
for details.
The IDT82V3012 provides a FLOCK pin to enable a Fast Lock mode.
When this pin is set to high, the DPLL will lock to an input reference
within approximately 500 ms.
17
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
4
ABSOLUTE MAXIMUM RATINGS
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
5
RECOMMENDED DC OPERATING CONDITIONS
6
DC ELECTRICAL CHARACTERISTICS
6.1
SINGLE END INPUT/OUTPUT PORTS
* Note:
1. Voltages are with respect to ground (V
SS
) unless otherwise stated.
2. Supply voltage and operating temperature are as per Recommended Operating Conditions.
Ratings
Min.
Max.
Unit
Power supply voltage
-0.5
5.0
V
Voltage on any pin with respect to ground
-0.5
5.5
V
Package power dissipation
200
mW
Storage temperature
-55
125
C
Parameter
Min.
Max.
Unit
Operating temperature
-40
+85
C
Power supply voltage
3.0
3.6
V
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions *
I
DDS
Supply current with OSCi = 0 V
300
A
Outputs unloaded
I
DD
Supply current with OSCi = Clock
45
60
mA
Outputs unloaded
V
CIH
CMOS high-level input voltage
0.7V
DD
V
OSCi, Fref0 and Fref1
V
CIL
CMOS low-level input voltage
0.3V
DD
V
OSCi, Fref0 and Fref1
V
TIH
TTL high-level input voltage
2.0
V
All input pins except for OSCi, Fref0 and Fref1
V
TIL
TTL low-level input voltage
0.8
V
All input pins except for OSCi, Fref0 and Fref1
I
IL
Input leakage current:
A
V
I
= V
DD
or 0 V
Normal (low level)
-15
15
Normal (high level)
-15
15
Pull up (low level)
-100
0
Pull up (high level)
-15
15
Pull down (low level)
-15
15
Pull down (high level)
0
100
V
OH
High-level output voltage
2.4
V
I
OH
= 8 mA
V
OL
Low-level output voltage
0.4
V
I
OL
= 8 mA
18
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
6.2
DIFFERENTIAL OUTPUT PORT (LVDS)
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
VOD
Differential Output Voltage
250
350
450
mV
RL = 100
VOD
Change in Magnitude of VOD for
Complementary Output States
4
35
mV
RL = 100
VOS
Offset Voltage
1.125
1.25
1.375
V
RL = 100
VOS
Change in Magnitude of VOS for
Complementary Output States
5
25
mV
RL = 100
VOH
Output Voltage High
1.38
1.6
V
RL = 100
VOL
Output Voltage Low
0.9
1.03
V
RL = 100
t
TLH
Output Rise time
0.38
1.5
ns
RL = 100
t
THL
Output Fall time
0.40
1.5
ns
RL = 100
IOS
Output Short Circuit Current
6.0
TBD
mA
IOSD
Differential Output Short Circuit Current
6.0
10
mA
19
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
7
AC ELECTRICAL CHARACTERISTICS
7.1
PERFORMANCE
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Freerun Mode accuracy with OSCi at: 0 ppm
-0
+0
ppm
5-9
Freerun Mode accuracy with OSCi at: 32 ppm
-32
+32
ppm
5-9
Freerun Mode accuracy with OSCi at: 100 ppm
-100
+100
ppm
5-9
Holdover Mode accuracy with OSCi at: 0 ppm
-0.00625
+0.00625
ppm
1, 2, 4, 6-9, 43, 44
Holdover Mode accuracy with OSCi at: 32 ppm
-0.00625
+0.00625
ppm
1, 2, 4, 6-9, 43, 44
Holdover Mode accuracy with OSCi at: 100 ppm
-0.00625
+0.00625
ppm
1, 2, 4, 6-9, 43, 44
Capture range with OSCi at: 0 ppm
-230
+230
ppm
1-3, 6-9
Capture range with OSCi at: 32 ppm
-198
+198
ppm
1-3, 6-9
Capture range with OSCi at: 100 ppm
-130
+130
ppm
1-3, 6-9
Phase lock time
50
s
1-3, 6-15, 45
Output phase continuity with reference switch
200
ns
1-3, 6-15
Output phase continuity with mode switch to Normal
200
ns
1-2, 4-15
Output phase continuity with mode switch to Freerun
200
ns
1-4, 6-15
Output phase continuity with mode switch to Holdover
50
ns
1-3, 6-15
Fref0 Frequency accuracy when MON_out0 is logic low
-12
+12
ppm
Fref1 Frequency accuracy when MON_out1 is logic low
-12
+12
ppm
MTIE (maximum time interval error)
600
ns
1-15, 28
Output phase slope
40
s/s
1-15, 28
Reference input for Auto-Holdover with 8 kHz
-18 k
+18 k
ppm
1-3, 6, 10-12
Reference input for Auto-Holdover with 1.544 MHz
-36 k
+36 k
ppm
1-3, 7, 10-12
Reference input for Auto-Holdover with 2.048 MHz
-36 k
+36 k
ppm
1-3, 8, 10-12
Reference input for Auto-Holdover with 19.44 MHz
-36 k
+36 k
ppm
1-3, 9, 10-12
20
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
7.2
INTRINSIC JITTER UNFILTERED
7.3
C1.5o (1.544 MHZ) INTRINSIC JITTER FILTERED
7.4
C2o (2.048 MHZ) INTRINSIC JITTER FILTERED
7.5
C19o (19.44 MHZ) INTRINSIC JITTER FILTERED
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Intrinsic jitter at F8o (8 kHz)
0.0001
UIpp
1-15, 22-25, 29
Intrinsic jitter at F0o (8 kHz)
0.0001
UIpp
1-15, 22-25, 29
Intrinsic jitter at F16o (8 kHz)
0.0001
UIpp
1-15, 22-25, 29
Intrinsic jitter at C1.5o (1.544 MHz)
0.015
UIpp
1-15, 22-25, 30
Intrinsic jitter at C3o (3.088 MHz)
0.03
UIpp
1-15, 22-25, 32
Intrinsic jitter at C2o (2.048 MHz)
0.01
UIpp
1-15, 22-25, 31
Intrinsic jitter at C6o (6.312 MHz)
0.06
UIpp
1-15, 22-25, 34
Intrinsic jitter at C4o (4.096 MHz)
0.02
UIpp
1-15, 22-25, 33
Intrinsic jitter at C8o (8.192 MHz)
0.04
UIpp
1-15, 22-25, 35
Intrinsic jitter at C16o (16.834 MHz)
0.04
UIpp
1-15, 22-25, 36
Intrinsic jitter at TSP (8 kHz)
0.0001
UIpp
1-15, 22-25, 29
Intrinsic jitter at RSP (8 kHz)
0.0001
UIpp
1-15, 22-25, 29
Intrinsic jitter at C32o (32.768 MHz)
0.08
UIpp
1-15, 22-25, 38
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Intrinsic jitter (4 Hz to 100 kHz filter)
0.008
UIpp
1-15, 22-25, 30
Intrinsic jitter (10 Hz to 40 kHz filter)
0.006
UIpp
1-15, 22-25, 30
Intrinsic jitter (8 kHz to 40 kHz filter)
0.006
UIpp
1-15, 22-25, 30
Intrinsic jitter (10 Hz to 8 kHz filter)
0.003
UIpp
1-15, 22-25, 30
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Intrinsic jitter (4 Hz to 100 kHz filter)
0.005
UIpp
1-15, 22-25, 31
Intrinsic jitter (10 Hz to 40 kHz filter)
0.004
UIpp
1-15, 22-25, 31
Intrinsic jitter (8 kHz to 40 kHz filter)
0.003
UIpp
1-15, 22-25, 31
Intrinsic jitter (10 Hz to 8 kHz filter)
0.002
UIpp
1-15, 22-25, 31
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Intrinsic jitter (500 Hz to 1.3 MHz filter)
2
nspp
1-15, 22-25, 37
Intrinsic jitter (65 kHz to 1.3 MHz filter)
0.5
nspp
1-15, 22-25, 37
21
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
7.6
8 KHZ INPUT TO 8 KHZ OUTPUT JITTER TRANSFER
7.7
1.544 MHZ INPUT TO 1.544 MHZ OUTPUT JITTER TRANSFER
7.8
2.048 MHZ INPUT TO 2.048 MHZ OUTPUT JITTER TRANSFER
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Jitter attenuation for 1 Hz@0.01 UIpp input
0
6
dB
1-3, 6, 10-15, 22-23, 25, 29, 39
Jitter attenuation for 1 Hz@0.54 UIpp input
6
16
dB
1-3, 6, 10-15, 22-23, 25, 29, 39
Jitter attenuation for 10 Hz@0.10 UIpp input
15
22
dB
1-3, 6, 10-15, 22-23, 25, 29, 39
Jitter attenuation for 60 Hz@0.10 UIpp input
32
38
dB
1-3, 6, 10-15, 22-23, 25, 29, 39
Jitter attenuation for 300 Hz@0.10 UIpp input
42
dB
1-3, 6, 10-15, 22-23, 25, 29, 39
Jitter attenuation for 3600 Hz@0.005 UIpp input
50
dB
1-3, 6, 10-15, 22-23, 25, 29, 39
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Jitter attenuation for 1 Hz@20 UIpp input
0
6
dB
1-3, 7, 10-15, 22-23, 25, 30, 39
Jitter attenuation for 1 Hz@104 UIpp input
6
16
dB
1-3, 7, 10-15, 22-23, 25, 30, 39
Jitter attenuation for 10 Hz@20 UIpp input
17
22
dB
1-3, 7, 10-15, 22-23, 25, 30, 39
Jitter attenuation for 60 Hz@20 UIpp input
33
38
dB
1-3, 7, 10-15, 22-23, 25, 30, 39
Jitter attenuation for 300 Hz@20 UIpp input
45
dB
1-3, 7, 10-15, 22-23, 25, 30, 39
Jitter attenuation for 10 kHz@0.3 UIpp input
48
dB
1-3, 7, 10-15, 22-23, 25, 30, 39
Jitter attenuation for 40 kHz@0.3 UIpp input
50
dB
1-3, 7, 10-15, 22-23, 25, 30, 39
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Jitter at output for 1 Hz@3.00 UIpp input
2.5
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 39
Jitter at output for 1 Hz@3.00 UIpp input with 40 Hz to 100 kHz filter
0.07
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 40
Jitter at output for 3 Hz@2.33 UIpp input
1.4
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 39
Jitter at output for 3 Hz@2.33 UIpp input with 40 Hz to 100 kHz filter
0.10
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 40
Jitter at output for 5 Hz@2.07 UIpp input
0.90
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 39
Jitter at output for 5 Hz@2.07 UIpp input with 40 Hz to 100 kHz filter
0.10
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 40
Jitter at output for 10 Hz@1.76 UIpp input
0.40
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 39
Jitter at output for 10 Hz@1.76 UIpp input with 40 Hz to 100 kHz filter
0.10
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 40
Jitter at output for 100 Hz@1.50 UIpp input
0.06
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 39
Jitter at output for 100 Hz@1.50 UIpp input with 40 Hz to 100 kHz filter
0.05
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 40
Jitter at output for 2400 Hz@1.50 UIpp input
0.04
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 39
Jitter at output for 2400 Hz@1.50 UIpp input with 40 Hz to 100 kHz filter
0.03
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 40
Jitter at output for 100 kHz@0.20 UIpp input
0.04
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 39
Jitter at output for 100 kHz@0.20 UIpp input with 40 Hz to 100 kHz filter
0.02
UIpp
1-3, 8, 10-15, 22-23, 25, 31, 40
22
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
7.9
19.44 MHZ INPUT TO 19.44 MHZ OUTPUT JITTER TRANSFER
7.10
8 KHZ INPUT JITTER TOLERANCE
7.11
1.544 MHZ INPUT JITTER TOLERANCE
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Jitter attenuation for 1 Hz@20 UIpp input
0
6
dB
1-3, 9-15, 22-23, 25, 37, 39
Jitter attenuation for 1 Hz@104 UIpp input
6
16
dB
1-3, 9-15, 22-23, 25, 37, 39
Jitter attenuation for 10 Hz@20 UIpp input
17
22
dB
1-3, 9-15, 22-23, 25, 37, 39
Jitter attenuation for 60 Hz@20 UIpp input
33
38
dB
1-3, 9-15, 22-23, 25, 37, 39
Jitter attenuation for 300 Hz@20 UIpp input
45
dB
1-3, 9-15, 22-23, 25, 37, 39
Jitter attenuation for 10 kHz@0.3 UIpp input
48
dB
1-3, 9-15, 22-23, 25, 37, 39
Jitter attenuation for 40 kHz@0.3 UIpp input
50
dB
1-3, 9-15, 22-23, 25, 37, 39
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Jitter tolerance for 1 Hz input
0.80
UIpp
1-3, 6, 10-15, 22-23, 25-27, 29
Jitter tolerance for 5 Hz input
0.70
UIpp
1-3, 6, 10-15, 22-23, 25-27, 29
Jitter tolerance for 20 Hz input
0.60
UIpp
1-3, 6, 10-15, 22-23, 25-27, 29
Jitter tolerance for 300 Hz input
0.16
UIpp
1-3, 6, 10-15, 22-23, 25-27, 29
Jitter tolerance for 400 Hz input
0.14
UIpp
1-3, 6, 10-15, 22-23, 25-27, 29
Jitter tolerance for 700 Hz input
0.07
UIpp
1-3, 6, 10-15, 22-23, 25-27, 29
Jitter tolerance for 2400 Hz input
0.02
UIpp
1-3, 6, 10-15, 22-23, 25-27, 29
Jitter tolerance for 3600 Hz input
0.01
UIpp
1-3, 6, 10-15, 22-23, 25-27, 29
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Jitter tolerance for 1 Hz input
150
UIpp
1-3, 7, 10-15, 22-23, 25-27, 30
Jitter tolerance for 5 Hz input
140
UIpp
1-3, 7, 10-15, 22-23, 25-27, 30
Jitter tolerance for 20 Hz input
130
UIpp
1-3, 7, 10-15, 22-23, 25-27, 30
Jitter tolerance for 300 Hz input
38
UIpp
1-3, 7, 10-15, 22-23, 25-27, 30
Jitter tolerance for 400 Hz input
25
UIpp
1-3, 7, 10-15, 22-23, 25-27, 30
Jitter tolerance for 700 Hz input
15
UIpp
1-3, 7, 10-15, 22-23, 25-27, 30
Jitter tolerance for 2400 Hz input
5
UIpp
1-3, 7, 10-15, 22-23, 25-27, 30
Jitter tolerance for 10 kHz input
1.2
UIpp
1-3, 7, 10-15, 22-23, 25-27, 30
Jitter tolerance for 40 kHz input
0.5
UIpp
1-3, 7, 10-15, 22-23, 25-27, 30
23
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
7.12
2.048 MHZ INPUT JITTER TOLERANCE
7.13
19.44 MHZ INPUT JITTER TOLERANCE
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Jitter tolerance for 1 Hz input
150
UIpp
1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 5 Hz input
140
UIpp
1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 20 Hz input
130
UIpp
1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 300 Hz input
40
UIpp
1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 400 Hz input
33
UIpp
1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 700 Hz input
18
UIpp
1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 2400 Hz input
5.5
UIpp
1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 10 kHz input
1.3
UIpp
1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 100 kHz input
0.4
UIpp
1-3, 8, 10-15, 22-23, 25-27, 31
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see "Notes" on page 24)
Jitter tolerance for 12 Hz input
2800
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 178 Hz input
2800
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 0.0016 Hz input
311
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 0.0156 Hz input
311
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 0.125 Hz input
39
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 19.3 Hz input
39
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 500 Hz input
1.5
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 6.5 kHz input
1.5
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 65 kHz input
0.15
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 1.3 MHz input
0.15
UIpp
1-3, 9-15, 22-23, 25-27, 37
24
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
Notes:
Voltages are with respect to ground (V
SS
) unless otherwise stated. Supply voltage and
operating temperature are as per Recommended Operating Conditions. Timing
parameters are as per Timing Parameter Measurement Voltage Levels.
1. Fref0 reference input selected.
2. Fref1 reference input selected.
3. Normal mode selected.
4. Holdover mode selected.
5. Freerun mode selected.
6. 8 kHz frequency mode selected.
7. 1.544 MHz frequency mode selected.
8. 2.048 MHz frequency mode selected.
9. 19.44 MHz frequency mode selected.
10. Master clock input OSCi at 20 MHz 0 ppm.
11. Master clock input OSCi at 20 MHz 32 ppm.
12. Master clock input OSCi at 20 MHz 100 ppm.
13. Selected reference input at 0 ppm.
14. Selected reference input at 32 ppm.
15. Selected reference input at 100 ppm.
16. For Freerun mode of 0 ppm.
17. For Freerun mode of 32 ppm.
18. For Freerun mode of 100 ppm.
19. For capture range of 230 ppm.
20. For capture range of 198 ppm.
21. For capture range of 130 ppm.
22. 25 pF capacitive load.
23. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where 1 UIpp = 1/20 MHz.
24. Jitter on reference input is less than 7 nspp.
25. Applied jitter is sinusoidal.
26. Minimum applied input jitter magnitude to regain synchronization.
27. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
28. Within 10 ms of the state, reference or input change.
29. 1 UIpp = 125 s for 8 kHz signals.
30. 1 UIpp = 648 ns for 1.544 MHz signals.
31. 1 UIpp = 488 ns for 2.048 MHz signals.
32. 1 UIpp = 323 ns for 3.088 MHz signals.
33. 1 UIpp = 244 ns for 4.096 MHz signals.
34. 1 UIpp = 158 ns for 6.312 MHz signals.
35. 1 UIpp = 122 ns for 8.192 MHz signals.
36. 1 UIpp = 61 ns for 16.484 MHz signals.
37. 1 UIpp = 51 ns for 19.44 MHz signals.
38. 1 UIpp = 30 ns for 32.968 MHz signals.
39. No filter.
40. 40 Hz to 100 kHz bandpass filter.
41. With respect to reference input signal frequency.
42. After a RST or TCLR.
43. Master clock duty 40% to 60%.
44. Prior to Holdover mode, device as in Normal mode and phase locked.
45. With input frequency offset of 100 ppm.
25
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
8
TIMING CHARACTERISTICS
8.1
TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS
Figure - 9 Timing Parameter Measurement Voltage Levels
Notes:
1. Voltages are with respect to ground (V
SS
) unless otherwise stated.
2. Supply voltage and operating temperature are as per Recommended Operating Conditions.
3. Timing for input and output signals is based on the worst case result of the CMOS thresholds.
8.2
INPUT/OUTPUT TIMING
Parameter
Description
CMOS
Units
V
T
Threshold Voltage
0.5V
DD
V
V
HM
Rise and Fall Threshold Voltage High
0.7V
DD
V
V
LM
Rise and Fall Threshold Voltage Low
0.3V
DD
V
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
t
RW
Reference input pulse width high or low
100
ns
8 kHz, 1.544 MHz or 2.048 MHz
reference input
5
ns
19.44 MHz reference input
t
IRF
Reference input rise or fall time
10
ns
t
R8D
8 kHz reference input to F8o delay
0
25
ns
t
R15D
1.544 MHz reference input to F8o delay
326
342
ns
t
R2D
2.048 MHz reference input to F8o delay
248
264
ns
t
R19D
19.44 MHz reference input to F8o delay
5
ns
t
FOD
F8o to F0o delay
111
130
ns
t
F16S
F16o setup to C16o falling
25
40
ns
t
F16H
F16o hold to C16o falling
25
40
ns
t
F19S
F19o setup to C19o falling
25
ns
t
F19H
F19o hold to C19o falling
25
ns
t
C15D
F8o to C1.5o delay
-10
10
ns
t
C3D
F8o to C3o delay
-10
10
ns
t
C6D
F8o to C6o delay
-10
10
ns
t
C2D
F8o to C2o
-11
5
ns
t
C4D
F8o to C4o
-11
5
ns
t
C8D
F8o to C8o delay
-11
5
ns
t
C16D
F8o to C16o delay
-11
5
ns
Timing Reference Points
t
IRF,
t
ORF
t
IRF,
t
ORF
V
HM
V
T
V
LM
All Siganls
26
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
t
C19D
F8o to C19o delay
-11
5
ns
t
C32D
F8o to C32o delay
-11
5
ns
t
TSPD
F8o to TSP delay
-6
10
ns
t
RSPD
F8o to RSP delay
-8
8
ns
t
C15W
C1.5o pulse width high or low
309
339
ns
t
C3W
C3o pulse width high or low
154
169
ns
t
C6W
C6o pulse width high or low
70
86
ns
t
C2W
C2o pulse width high or low
232
258
ns
t
C4W
C4o pulse width high or low
111
133
ns
t
C8W
C8o pulse width high or low
52
70
ns
t
C16W
C16o pulse width high or low
24
35
ns
t
C19W
C19o pulse width high or low
25
ns
t
C32W
C32o pulse width high or low
14
16.78
ns
t
TSPW
TSP pulse width high
478
494
ns
t
RSPW
RSP pulse width high
474
491
ns
t
F0WL
F0o pulse width low
234
254
ns
t
F8WH
F8o pulse width high
109
135
ns
t
F16WL
F16o pulse width low
47
72
ns
t
F19WH
F19o pulse width low
25
ns
t
0RF
Output clock and frame pulse rise or fall time
9
ns
t
S
Input controls setup Time
100
ns
t
H
Input controls hold Time
100
ns
t
F16D
F8o to F16o delay
24
38
ns
t
F19D
F8o to F19o delay
25
ns
t
F32D
F8o to F32o delay
12
19
ns
t
F32S
F32o setup to C32o falling
11
ns
t
F32H
F32o hold to C32o falling
11
ns
t
F32WL
F32o pulse width low
15
31
ns
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
27
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
Figure - 10 Input to Output Timing (Normal Mode)
t
R8D
t
RW
t
R15D
t
RW
Fref0/Fref1
8 kHz
Fref0/Fref1
1.544 MHz
Fref0/Fref1
2.048 MHz
F8o
Fref0/Fref1
19.44 MHz
t
R2D
t
RW
t
RW
t
R19D
V
T
V
T
V
T
V
T
V
T
28
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
Figure - 11 Output Timing 1
t
F8WH
t
F0D
t
F0W
L
t
F16D
t
F16WL
t
F16H
t
F16S
t
C16D
t
C16W
t
C8W
t
C4W
t
C2W
t
C2D
t
C6W
t
C6D
t
C15D
t
C15W
t
C8D
t
C4D
V
T
V
T
V
T
V
T
V
T
V
T
V
T
V
T
V
T
C1.5o
C6o
C2o
C4o
C8o
C16o
F16o
F0o
F8o
C32o
C3o
t
C32D
t
C3D
t
C3W
t
C32W
V
T
V
T
F32o
t
F32WL
t
F32D
V
T
t
F32S
t
F32H
t
C6W
t
C4W
t
C8W
V
T
C19o
C19POS
C19NEG
V
T
V
T
t
C19D
t
C19W
V
T
t
F19WH
t
F19D
t
F19S
t
F19H
F19o
t
C19W
t
C19D
t
C19D
t
C19W
(see Note 1)
(see Note 1)
29
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
Figure - 12 Output Timing 2
Note 1: The timing characteristic of C2/C1.5 (2.048 MHz or 1.544 MHz) is as same as that of C2o or C1.5o.
Figure - 13 Input Control Setup and Hold Timing
t
TSPD
t
TSPW
V
T
C2o
F8o
t
RSPD
t
RSPW
V
T
V
T
V
T
RSP
TSP
V
T
V
T
t
H
t
S
F8o
MODE_sel0
MODE_sel1
TIE_en
IN_sel
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
30
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9
ORDERING INFORMATION
IDT
XXXXXXX
XX
X
Device Type
Blank
Process/
Temperature
Range
82V3012
Industrial (-40 C to +85 C)
T1/E1/OC3 WAN PLL with Dual
Reference Inputs
Package
PV
Shrink Small Outline Package (SSOP, PV56)