Document Outline

• Version -
• March 14, 2003
• 3.3 VOLT M13 MULTIPLEXER
• IDT82V8313
  • 2975 Stender Way, Santa Clara, California 95054
  • Telephone: (800) 345-7015 . . FAX: (408) 492-8674
  • Printed in U.S.A.
  • � 2003 Integrated Device Technology, Inc.
  • DISCLAIMER
  • LIFE SUPPORT POLICY
    • FEATURES 1
    • PACKAGE 2-4
    • PIN DESCRIPTIONS 5-12
    • REGISTER MEMORY MAP 13-16
    • REGISTER DESCRIPTIONS 17
    • FUNCTIONAL DESCRIPTION 57-76
    • DATA LINK 77-90
    • FUNCTIONAL TIMING 91-92
    • LOOPBACK MODES 93-98
    • DC ELECTRICAL CHARACTERISTICS 99
    • AC ELECTRICAL CHARACTERISTICS 101
    • JTAG 113
    • ORDERING INFORMATION 119
    • GLOSSARY 121-124
    • STANDARDS 125-126
    • INDEX 127-128
      • 3.3 VOLT M13 MULTIPLEXER
      • FEATURES:
      • PACKAGE
      • IDT82V8313
      • Preliminary
  • I
  • 26
  • H1
  • I
  • 29
  • J2
  • I
  • 30
  • J1
  • O
  • 10
  • D2
  • O
  • 7
  • D1
  • O
  • 11
  • D3
  • O
  • 16
  • F1
  • O
  • 12
  • E1
  • O
  • 21
  • G2
  • O
  • 20
  • G1
  • O
  • 19
  • F4
  • O
  • 22
  • G3
  • O
  • 25
  • J3
  • O
  • 4
  • C3
  • O
  • 24
  • H2
  • O
  • 23
  • H3
  • O
  • 31
  • D4
  • O
  • 32
  • E4
  • O
  • O
  • I
  • I
  • O
  • 6
  • B2
  • I
  • 206
  • A2
  • O
  • 205
  • C5
  • O
  • 207
  • C4
  • I
  • 204
  • D5
  • I
  • 1
  • C2
  • I
  • 208
  • B3
  • I
  • 17
  • F2
  • I
  • 18
  • F3
  • O
  • 15
  • E3
  • O
  • 14
  • E2
  • O
  • 2
  • A1
  • O
  • 3
  • B1
  • O
  • 5
  • C1
  • O
  • 33
  • K3
  • I
  • 45
  • M2
  • I
  • 57
  • R3
  • I
  • 56
  • T3
  • I/O
  • I
  • I
  • 58
  • P3
  • I
  • 46
  • M1
  • I
  • *See TQFP table below for details
  • *See BGA table below for details
  • I
  • I
  • I
  • P5
  • O
  • R7
  • I
  • T4
  • I
  • P11
  • I
  • R9
  • 7
  • 6
  • 5
  • 4-1
  • 0
  • 7-0
  • 7
  • 6-0
    • 1. A nominally 6.312 MHz clock is expected on TD1CLK(4n).
    • 2. A data stream synchronous to TD1CLK(4n) is expected on TD1DAT(4n).
    • 3. The clocks on TD1CLK(4n-1), TD1CLK(4n-2) and TD1CLK(4n-3) have no effect and should be tied to ground.
    • 4. The data streams in TD1DAT(4n-1), TD1CLK(4n-2) and TD1CLK(4n-3) are ignored and should be tied to ground.
    • 5. A nominally 6.312 MHz clock is presented on RD1CLK(4n).
    • 6. A data stream synchronous to RD1CLK(4n) is presented on RD1DAT(4n).
    • 7. The signals on RD1CLK(4n-1), RD1CLK(4n-2),RD1CLK(4n-3), RD1DAT(4n-1), RD1DAT(4n-2) and RD1DAT(4n-3) are always LOW.
  • 7
  • 6
  • 5-4
  • 3
  • 2
  • 1
  • 0
  • 7-4
  • 3-2
  • 1
  • 0
  • 7-5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7-4
  • 3
  • 2
  • 1- 0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7
  • 6-0
  • 7
  • 6-0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2-1
  • 0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7-3
  • 2
  • 1
  • 0
  • 7-0
  • 7-0
  • 7-0
  • 7-2
  • 1-0
  • 7-0
  • 7-0
  • 7-0
  • 7-0
  • 7-0
  • 7-6
  • 5-0
  • 7-0
  • 7-0
  • 7-5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7-2
  • 1
  • 0
  • 7-0
  • 7-2
  • 1
  • 0
  • 7-3
  • 2, 1
  • 0
  • 7
  • 6
  • 5
  • 4
    • 1. The last byte in the LAPD frame (EOM) is being read from the Receive Data Register.
    • 2. An abort sequence is detected while not in the receiving all-ones state and the byte, written to the FIFO due to the detection of the abort sequence, is being read from the FIFO,
    • 3. Immediately on detection of FIFO overrun.
  • 3
  • 2-0
  • 7-0
  • 7-4
  • 3-2
  • 1
  • 0
  • 7
  • 6-0
  • 7
  • 6-0
  • 7
  • 6-0
  • 7
  • 6-0
  • 7
  • 6-0
  • 7
  • 6-0
  • 7-6
  • 5-0
  • 7-3
  • 2
  • 1
  • 0
  • 7
  • 6
  • 5-0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7-6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1-0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7-6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7-3
  • 2
  • 1
  • 0
  • 7-0
  • 7-0
  • 7-5
  • 4-0
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1
  • 0
  • 7-2
  • 1-0
  • 7-4
  • 3-0
  • 7-4
  • 3-0
  • 7-4
  • 3-0
  • 7-4
  • 3-0
    • Figure 1 DS3 Framer Block
    • Figure 2 DS3 Frame
    • Figure 3 B3ZS Coding
    • 1. Applicable to B2ZS-coded signal. DS1 Equipment Failure (Nsa) (3) 0 000011 0 11111111
    • 2. Network equipment must not respond to or generate these codewords.
    • 3. Applicable to all type of loopbacks.
    • 4. Code must be transmitted 10 times, followed immediately by 10 repetitions of the DS3 or DS1 line codeword.
    • 5. For Unchannelized DS3 applications, DS1s are unassigned.
      • Figure 4 Transmit BOC
      • Figure 5 Receive BOC
    • 1. Sa-Service affecting
    • 2. Nsa-Non Service Affecting
    • 3. Applicable to B3ZS - coded signal
    • 4. Newtork equipment must not respond to or generate these code words.
    • 5. Applicable to all types of loopbacks
    • 6. Code must be transmitted 10 times, followed immediately by 10 repetition of the DS3 or DS1 line code word.
    • 7. For unchannelized DS3 applications, DS1 are unassigned.
    • 1. C/R = 0 if DTE (from user side)
    • 2. C/R = 1 if Carrier (from network side)
    • 3. FCS: is the Frame Check Sequence CRC16 (can be disabled) Polynomial = x16 + x12 + x5 + 1
    • 4. Type: identify type of message (1 byte) with the following value
    • 5. EIC: identify the specific piece of equipment (10 bytes).
    • 6. LIC: identify a particular location (11 bytes).
    • 7. FIC: identify where the equipment is located with in a building (10 bytes).
    • 8. UNIT: identify the equipment location with in a bay (6 bytes).
    • 9. Final field (38 bytes):
    • 1. Step 1 continues until the all bytes for the frame are written.
    • 2. Transmit data bytes are written to the Transmit Data register.
    • 3. The XDL prepares the byte by performing a serial-to-parallel conversion of the byte.
    • 4. An interrupt is generated to signal the controller to write the next byte.
    • 5. After the last byte is written to the transmit data register, the EOM bit in the XDL configuration register should be set or the TDLEOMI pin should be set to indicate the end of message.
    • 6. The XDL sends the last data byte and then the CRC word is sent (if enabled) or a flag (if CRC is not enabled).
    • 7. Once complete, the flag character is sent.
      • Figure 6 Jitter Definition
      • Figure 7 Maximum Jitter Tolerance on DSn Interface Inputs
      • Figure 8 M23 Mulitplexer Block
      • Figure 9 DS3 Stuff Block
      • Figure 10 DS2 Framer Block
      • Figure 11 DS2 Frame
      • Figure 12 G.747 Frame Format
      • Figure 13 M12 Block
      • Figure 14 DS2 Stuff Block
    • Internal Data Link Transmitter:
    • Internal Data Link Receiver:
    • Interrupt Driven Mode:
    • Polled Mode:
      • Figure 15. XFDL
    • Polled Mode:
      • Figure 16. XFDL Polled Mode
    • Interrupt Driven Mode:
      • Figure 17. XFDL Interrupt Mode
      • Figure 18. XFDL Interrupt Service Routine
    • DMA Mode:
      • Figure 19. XFDL DMA Mode
      • Figure 20. XFDL Normal Data Sequence
      • Figure 21. XFDL Underrun Sequence
      • Figure 22. TDLINT Timing Normal Data TX
      • Figure 23. TDLEOMI Timing EOMI After CRC
      • Figure 24. RFDL
      • Figure 25. RFDL Polled Mode
      • Figure 26. RFDL Interrupt Driven Mode
      • Figure 27. RFDL Interrupt Service Routine
      • Figure 28. RFDL DMA Mode
      • Figure 29. RFDL Normal Data And Abort Sequence
    • DMA Mode:
    • RFDL Normal Data and Abort Sequence:
    • TDLEOMI Timing:
    • XFDL Normal Data Sequence:
    • XFDL Underrun Sequence:
    • TDLINT Timing Normal Data Transmission:
      • Figure 30. Receive DS3 OH Serial Stream
      • Figure 31. Transmit DS3 OH Serial Stream
      • Figure 32. Functional Receive OH Timing Low Speed
      • Figure 33. Functional Receive Timing PMON
      • Figure 34. Functional Receive OH Timing High-Speed
    • Loopback Modes:
    • DS3 Diagnostic Loopback
      • Figure 35. DS3 Diagnostic Loopback
    • DS3 Line Loopback
      • Figure 36. DS3 Line Loopback
    • DS2/G.747 Demultiplex Loopback
      • Figure 37. DS2 / G.747 Demultiplex Loopback
    • DS1/E1 Demultiplex Loopback
      • Figure 38. DS1/E1 Demultiplex Loopback6+
  • -0.5
  • +43.0
  • V
  • GND -0.3
  • Vcc +0.3
  • V
  • -50
  • 50
  • mA
  • -55
  • +125
  • �C
  • -
  • 2
  • W
  • -40
  • +85
  • �C
  • -500
  • +500
  • V
  • -100
  • +100
  • mA
  • -
  • +300
  • �C
  • -
  • +150
  • �C
  • Vcc
  • 3.0
  • 3.3
  • 3.6
  • V
  • Vih(1)
  • 2.0
  • -
  • Vcc
  • V
  • Vil
  • -0.3
  • -
  • 0.8
  • V
  • Top
  • -40
  • 25
  • +85
  • C
  • -
  • -
  • ?
  • -10
  • -
  • 60
  • -10
  • 60
  • -
  • -
  • 60
  • 2.4
  • -
  • -
  • -
  • -
  • 0.4
    • Figure 39 Microprocessor Read Access Timing
    • Notes on Microprocessor Read Timing:
    • 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
    • 2. Maximum output propagation delays are measured with a 100 pF load on the microprocessor data bus, (D 7-0).
    • 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
    • 4. Microprocessor timing applies to normal mode register accesses only.
    • 5. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
    • 6. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
    • 7. In non-multiplexed address/data bus architectures, ALE should be held high, parameters tsalr, thalr, tvl, thlr and tslr are not applicable.
    • 8. Parameters thar and tsar are not applicable of address latching is used.
      • Figure 40 Microprocessor Write Access Timing
      • Notes on Microprocessor Write Timing:
    • 1. A valid write cycle is defined as a logical OR of the CSB and the WDB signals.
    • 2. Microprocessor timing applies to normal mode register accesses only.
    • 3. In non-multiplexed address/data bus architectures, ALE should be held high, parameters tsalw, thalw, tvl, thlw and tslw are not applicable.
    • 4. Parameters thaw and tsaw are not applicable of address latching is used.
    • 5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
    • 6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
    • 7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
      • Figure 41 Receive DS3 Input Timing
      • Figure 42 Transmit DS3 Input Timing
      • Figure 43 Transmit Overhead Input Timing
      • Figure 44 Transmit Tributary Input Timing
      • Figure 45 Transmit Data Link Input Timing
      • Figure 46 Transmit Data Link EOM Input Timing
      • Notes on Input Timing:
    • 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
    • 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
    • 3. TD1CLK frequency, TD2CLK frequency, ts1teomi, ts2teomi, ts3teomi and tvteomi values are guaranteed by design - not measured.
      • Figure 47 Transmit DS3 Output Timing
      • Figure 48 Receive DS3 Output Timing
      • Figure 49 Receive Overhead Output Timing
      • Figure 50 Transmit Overhead Output Timing
      • Figure 51 Receive Tributary Output Timing
      • Figure 52 Receive Data Link Output Timing
      • Notes on Output Timing:
    • 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
    • 2. Maximum output propagation delays are measured with a 20 pF load on the high-speed DS3 outputs (TCLK, TPOS/TDAT, TNEG/TMFP, ROCLK, RODAT, RMFP, RMSFP, and ROHP) and a 50 pF load on the remaining outputs.
      • Figure 53 Standard JTAG Timing
      • Notes:
    • 1. Device inputs = All device inputs except TDI, TMS, and TRST.
    • 2. Device outputs = All device outputs except TDO
      • Notes:
    • 1. Guaranteed by design.
    • 2. 30pF loading on external output signals.
    • 3. Refer to AC Electrical Test Conditions stated earlier in this document.
    • 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
      • Note:
    • 1. Device ID forIDT82V8313 is 0x0313.
      • Notes:
    • 1. Device outputs = All device outputs except TDO.
    • 2. Device inputs = All device inputs except TDI, TMS, and TRST
    • 3. The Boundary Scan Description Language (BSDL) file for this device is available on the IDT website (www.idt.com), or b y contacting you local IDT sales representative.
    • JTAG Information
    • GLOSSARY
    • STANDARDS
    • INDEX
  • A
  • B
  • C
  • E
  • F
  • H
  • I
  • L
  • O
  • P
  • R
  • U