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Электронный компонент: IDT70V15L25J

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1
2002 Integrated Device Technology, Inc.
AUGUST 2002
DSC 5669/1
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
W
L
CE
L
OE
L
BUSY
L
A
13L
(1)
A
0L
5669 drw 01
I/O
0L
- I/O
8L
CE
L
OE
L
R/
W
L
SEM
L
INT
L
M/
S
BUSY
R
A
13R
(1)
A
0R
SEM
R
INT
R
CE
R
OE
R
(3)
(2,3)
(3)
R/
W
R
CE
R
OE
R
R/
W
R
14
14
I/O
0R
-I/O
8R
(2,3)
.unctional Block Diagram
more using the Master/Slave select when cascading more
than one device
x
M/
S = V
IH
for
BUSY output flag on Master
M/
S = V
IL
for
BUSY input on Slave
x
Busy and Interrupt Flag
x
On-chip port arbitration logic
x
Full on-chip hardware support of semaphore signaling
between ports
x
Fully asynchronous operation from either port
x
LVTTL-compatible, single 3.3V (+0.3V) power supply
x
Available in 68-pin PLCC and an 80-pin TQFP
x
Industrial temperature range (40C to +85C) is available
for selected speeds
.eatures
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x
High-speed access
Commercial:15/20/25ns (max.)
Industrial: 20ns (max.)
x
Low-power operation
IDT70V16/5S
Active: 430mW (typ.)
Standby: 3.3mW (typ.)
IDT70V16/5L
Active: 415mW (typ.)
Standby: 660W (typ.)
x
IDT70V16/5 easily expands data bus width to 18 bits or
HIGH-SPEED 3.3V
16/8K X 9 DUAL-PORT
STATIC RAM
IDT70V16/5S/L
NOTES:
1. A
13
is a NC for IDT70V15.
2. In MASTER mode:
BUSY is an output and is a push-pull driver
In SLAVE mode:
BUSY is input.
3.
BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
PRELIMINARY
6.42
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
5669 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
9
8
7
6
5
4
3
2
1 68 67 66 65
27 28 29 30 31 32 33 34 35 36 37 38 39
V
D
D
V
DD
I/O
1R
I/O
2R
I/O
3R
I/O
4R
INT
L
V
SS
A
4L
A
3L
A
2L
A
1L
A
0L
A
3R
A
0R
A
1R
A
2R
I/O
2L
A
5L
11
10
M/
S
23
24
25
26
40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O
3L
V
SS
I/O
0R
V
DD
A
4R
BUSY
L
V
SS
BUSY
R
INT
R
A
1
2
R
I
/
O
7
R
I
/
O
8
R
V
S
S
O
E
R
R
/
W
R
S
E
M
R
C
E
R
O
E
L
C
E
L
I
/
O
8
L
I
/
O
0
L
I
/
O
1
L
IDT70V16/5J
J68-1(5)
68-Pin PLCC
Top View(6)
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
5R
I/O
6R
N
/
C
A
1
2
L
N
/
C
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
A
6
L
A
1
3
R
(
1
)
S
E
M
L
R
/
W
L
A
1
3
L
(
1
)
,
08/26/02
Description
The IDT70V16/5 is a high-speed 16/8K x 9 Dual-Port Static RAM.
The IDT70V16/5 is designed to be used as stand-alone Dual-Port RAMs
or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more
wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM ap-
proach in 18-bit or wider memory system applications results in full-speed,
error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 430mW of power.
The IDT70V16/5 is packaged in a 64-pin PLCC (Plastic Leaded
Chip Carriers) and an 80-pinTQFP (Thin Quad Flatpack).
Pin Configurations
(1,2,3,4)
NOTES:
1. A
13
is a NC for IDT70V15.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately .95 in x .95 in x .17 in.
5. This package code is used to reference the package diagram.
6. This text does not imply orientation of Part-marking.
6.42
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
E
L
I
M
I
N
A
R
Y
PRELIMINARY
Pin Configurations
(1,2,3,4)
(con't.)
INDEX
IDT70V16/5PF
PN80-1(5)
80-Pin TQFP
Top View(6)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
58
57
56
55
54
53
52
51
50
49
48
47
46
59
60
45
6
5
6
6
6
7
6
8
7
9
7
8
7
7
7
6
7
5
7
4
7
3
7
2
7
1
7
0
6
9
8
0
I/O
2L
V
SS
V
SS
A
4R
BUSY
L
BUSY
R
INT
R
INT
L
V
SS
M/
S
O
E
L
N
C
R
/
W
L
C
E
L
S
E
M
L
V
D
D
N
C
O
E
R
C
E
R
R
/
W
R
S
E
M
R
V
S
S
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I
/
O
8
R
A
1
2
R
A
1
1
R
A
1
0
R
A
9
R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6
L
A
7
L
A
8
L
A
9
L
A
1
0
L
A
1
1
L
A
1
2
L
I
/
O
0
L
17
18
19
20
I/O
6R
I
/
O
7
R
NC
V
DD
2
3
2
4
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
4
0
3
9
3
8
3
7
A
8
R
A
7
R
A
6
R
N
C
44
43
42
41
NC
A
5L
NC
6
1
6
2
6
3
6
4
I
/
O
8
L
I
/
O
1
L
5669 drw 03
N
C
N
C
N
C
N
C
NC
A
5
R
NC
NC
N
C
2
1
2
2
A
1
3
L
(
1
)
A
1
3
R
(
1
)
08/26/02
NOTES:
1. A
13
is a NC for IDT70V15.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
Truth Table II: Semaphore Read/Write Control
(1)
Truth Table I: Non-Contention Read/Write Control
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O
s
(I/O
0
-I/O
8
). These eight semaphores are addressed by A
0
- A
2.
NOTE:
1. Condition: A
0L
-- A
13L
A
0R
-- A
13R
Inputs
(1)
Outputs
Mode
CE
R/
W
OE
SEM
I/O
0-8
H
X
X
H
High-Z
Deselcted: Power-Down
L
L
X
H
DATA
IN
Write to Memory
L
H
L
H
DATA
OUT
Read Memory
X
X
H
X
High-Z
Outputs Disabled
5669 tbl 02
Inputs
Outputs
Mode
CE
R/
W
OE
SEM
I/O
0-8
H
H
L
L
DATA
OUT
Read Semaphore Flag Data Out (I/O
0
- I/O
8
)
H
X
L
DATA
IN
Write I/O
0
into Semaphore Flag
L
X
X
L
____
Not Allowed
5669 tbl 03
Pin Names
Left Port
Right Port
Names
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
13L
(1)
A
0R
- A
13R
(1)
Address
I/O
0L
- I/O
8L
I/O
0R
- I/O
8R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S
Master or Slave Select
V
CC
Power (3.3V)
GND
Ground (0V)
5669 tbl 01
NOTE:
1. A
13
is a NC for IDT70V15.
6.42
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
E
L
I
M
I
N
A
R
Y
PRELIMINARY
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(V
DD
= 3.3V 0.3V)
NOTE:
1.
At V
DD
< 2.0V, Input leakages are undefined.
Symbol
Parameter
Test Conditions
70V16/5S
70V16/5L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
DD
= 3.6V, V
IN
= 0V t
o
V
DD
___
10
___
5
A
|I
LO
|
Output Leakage Currentt
(1)
CE = V
IH
, V
OUT
= 0V t
o
V
DD
___
10
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
5669 tbl 08
Recommended DC Operating
Conditions
Maximum Operating
Temperature and Supply Voltage
(1)
Absolute Maximum Ratings
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. V
TERM
must not exceed V
DD
+ 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
DD
+ 0.3V.
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect to GND
-0.5 to +3.6
V
T
BIAS
(3)
Temperature Under Bias
-55 to +125
o
C
T
STG
Storage Temperature
-65 to +150
o
C
T
JN
Junction Temperature
+150
o
C
I
OUT
DC Output Current
50
mA
5669 tbl 04
Grade
Ambient
Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
5669 tbl 05
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
3.0
3.3
3.6
V
V
SS
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
DD
+0.3
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
5669 tbl 06
Capacitance
(1)
(T
A
= +25C, f = 1.0MHz)
NOTES:
1. This parameter is determined by device characteristics but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V .
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
10
pF
5669 tbl 07