Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Bus switches provide zero delay paths
Extended commercial range of 40
C to +85
C
Low switch on-resistance:
FST163xxx 5
FST1632xxx -- 28
TTL-compatible input and output levels
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Available in SSOP, TSSOP and TVSOP
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 1997
1997 Integrated Device Technology, Inc.
DSC-3473/4
1
IDT74FST163384
IDT74FST1632384
ADVANCE INFORMATION
20-BIT BUS SWITCH
current sink or source capability. Thus they generate little or
no noise of their own while providing a low resistance path for
an external driver. These devices connect input and output
ports through an n-channel FET. When the gate-to-source
junction of this FET is adequately forward-biased the device
conducts and the resistance between input and output ports
is small. Without adequate bias on the gate-to-source junction
of the FET, the FET is turned off, therefore with no V
CC
applied, the device has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST1632xxx integrates terminating resistors in the
device, thus eliminating the need for external 25
series
resistors.
The FST163384 and FST1632384 are 20-bit TTL-compat-
ible bus switches. The BEx pins provide enable control.
A
0
B
0
A
4
B
4
B
5
B
9
A
5
A
9
BEA
BEB
A
10
B
10
A
14
B
14
B
15
B
19
A
15
A
19
BEC
BED
PIN DESCRIPTION
Pin Names
I/O
Description
A
0-19
I/O
Bus A
B
0-19
I/O
Bus B
BEA
,
BEB
,
BEC
,
BED
,
I
Bus Switch Enable (Active LOW)
3473 drw 01
3473 tbl 01
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The FST163384/1632384 belong to IDT's family of Bus
switches. Bus switch devices perform the function of connect-
ing or isolating two ports without providing any inherent
2
IDT74FST163384, IDT74FST1632384
20-BIT BUS SWITCH
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
PIN CONFIGURATION
5
6
7
8
9
10
1
2
3
4
46
45
44
43
42
41
40
39
38
37
B
4
B
0
A
0
A
1
B
1
B
2
A
2
A
3
B
3
A
19
A
18
B
18
B
17
A
17
A
16
B
16
B
15
Vcc
B
19
BEA
A
4
11
12
47
48
GND
A
15
BEB
17
18
19
20
21
22
13
14
15
16
34
33
32
31
30
29
28
27
26
25
B
9
B
5
A
5
A
6
B
6
B
7
A
7
A
8
B
8
B
14
A
13
B
13
B
12
A
12
A
11
B
11
B
10
Vcc
A
14
BEC
SO48-1
SO48-2
SO48-3
A
9
23
24
35
36
GND
A
10
BED
FUNCTION TABLE
BEA
BEA
BEB
BEB
B
0-4
B
5-9
Description
H
H
Hi-Z
Hi-Z
Disconnect
L
H
A
0-4
Hi-Z
Connect
H
L
Hi-Z
A
5-9
Connect
L
L
A
0-4
A
5-9
Connect
BEC
BEC
BED
BED
B
10-14
B
15-19
Description
H
H
Hi-Z
Hi-Z
Disconnect
L
H
A
10-14
Hi-Z
Connect
H
L
Hi-Z
A
15-19
Connect
L
L
A
10-14
A
15-19
Connect
3473 tbl 03
SSOP/
TSSOP/TVSOP
TOP VIEW
3473 drw 02
Symbol
Description
Max.
Unit
V
TERM(2)
Terminal Voltage with Respect
to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
Maximum Continuous Channel
Current
128
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating condiitions for extended
periods may affect reliability.
2. V
CC
, Control and Switch terminals.
Symbol
Parameter
Conditions
(2)
Typ. Unit
C
IN
Control Input Capacitance
4
pF
C
I/O
Switch Input/Output
Capacitance
Switch Off
pF
3473 tbl 04
NOTES:
1. Capacitance is characterized but not tested
2. T
A
= 25
C, f = 1MHz, VI
N
= 0V, V
OUT
= 0V
CAPACITANCE
(1)
3473 tbl 02
IDT74FST163384, IDT74FST1632384
20-BIT BUS SWITCH
COMMERCIAL TEMPERATURE RANGE
3
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 40
C to +85
C, V
CC
= 5.0V
10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH for Control Inputs
2.0
--
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW for Control Inputs
--
--
0.8
V
I
I H
Input HIGH Current
V
CC
= Max.
V
I
= V
CC
--
--
1
A
I
I L
Input LOW Voltage
V
I
= GND
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= V
CC
--
--
1
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
1
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
--
300
--
mA
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
R
ON
Switch On Resistance
(4)
V
CC
= Min. V
IN
= 0.0V
163xxx
--
5
7
I
ON
= 30mA
1632xxx
20
28
40
V
CC
= Min. V
IN
= 2.4V
163xxx
--
10
15
I
ON
= 15mA
1632xxx
20
35
48
I
OFF
Input/Output Power Off Leakage
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
0.1
3
A
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Measured by voltage drop between ports at indicated current through the switch.
3473 tbl 05
4
IDT74FST163384, IDT74FST1632384
20-BIT BUS SWITCH
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
i
N)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
i
= Input Frequency
N = Number of Switches Toggling at fi
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
=40
C to +85
C, V
CC
= 5.0V
10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(3)
--
0.5
1.5
mA
I
CCD
Dynamic Power Supply
Current
(4)
V
CC
= Max.
Outputs Open
V
IN
= V
CC
V
IN
= GND
--
30
40
A/
MHz/
Enable Pin Toggling
50% Duty Cycle
Switch
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
Enable Pins Toggling
V
IN
= V
CC
V
IN
= GND
--
6.0
8.0
mA
(20 Switches Toggling)
fi = 10MHz
50% Duty Cycle
V
IN
= 3.4
V
IN
= GND
--
7.0
11.0
3473 tbl 06
3473 tbl 07
NOTES:
1. See test circuit and waveforms.
2. Minimum limits guaranteed but not tested.
3. This parameter is guaranteed by design but not tested.
4. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant
for the switch alone is of the order of 2.5ns for 50pF load. Since this time is constant and much smaller than the rise/fall times of typical driving signals,
it adds very little propagation delay to the system. Propagation delay on the bus switch when used in a system is determined by the driving circuit on the
driving side of the switch and its interaction with the load on the driven side.
5. Measured at switch turn off, load = 50 pF in parallel with 10M
scope probe, V
IN
= 0.0 volts.
6. Characterized parameter. Not 100% tested.
163384
1632384
Symbol
Description
Condition
(1)
Min.
(2)
Typ.
Max.
Unit
t
PLH
t
PHL
Data Propagation Delay
Ai to Bi, Bi to Ai
(3,4)
C
L
= 50pF
R
L
= 500
--
--
0.25
1.25
ns
t
PZH
t
PZL
Switch Turn on Delay
BEx to Ai, Bi
1.5
--
6.5
7.5
ns
t
PHZ
t
PLZ
Switch Turn off Delay
BEx to Ai, Bi
(3)
1.5
--
5.5
5.5
ns
|Q
CI
|
Charge Injection
(5,6)
--
1.5
--
--
pC
IDT74FST163384, IDT74FST1632384
20-BIT BUS SWITCH
COMMERCIAL TEMPERATURE RANGE
5
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
PULSE WIDTH
SET-UP, HOLD AND RELEASE TIMES
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns
3473 lnk 08
3473 lnk 03
3473 lnk 04
3473 lnk 05
3473 lnk 06
3473 lnk 07
6
IDT74FST163384, IDT74FST1632384
20-BIT BUS SWITCH
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX
Temp. Range
16 XX
Device Type
X
Package
74
40
C to +85
C
PV
PA
PF
163384
1632384
Shrink Small Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
Thin Very Small Outline Package (SO48-3)
20-Bit Bus Switch
FST
3473 drw 08
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