COMMERCIAL TEMPERATURE RANGE

JUNE 2000

DSC-5349/2

KEY FEATURES

· Full-duplex Segmentation and Reassembly (SAR) at

155 Mbps "wire-speed" (310 Mbps aggregate speed).

· Performs ATM layer protocol functions.
· Supports AAL5, AAL3/4, AAL0 and Raw Cell formats.
· Supports Constant Bit Rate (CBR), Variable Bit Rate

(VBR), and Unassigned Bit Rate (UBR), and Available Bit
Rate (ABR) service classes.

· Segments and reassembles CS-PDUs into host memory.
· Four buffer pools for independent or chained reassembly
· PCI 2.1 compliant.
· Operates with ATM networks up to 155.52 Mbps.
· Up to 256 active transmit connections.
· Up to 256 active receive connections.
· UTOPIA Level 1 Interface to PHY.
· Utility & Management Interface to PHY.

· Stand-alone controller: embedded processor not re-

quired.

· Supports high-performance, lowest-cost ATM NIC

solution.

· Supports any buffer alignment condition.
· Supports Big and Little Endian data transfers.
· Free Bufffer Queues mapped into PCI memory space.
· Configurable transmit FIFO depth for reduced latency.
· Null cell disable option during transmit.
· Supports greater local memory size.
· Large Rx FIFO size (configurable to 1024 Kbytes).
· Meets Power Management specification.
· Automatic AAL5 padding.
· UNI 3.1, TM 4.0 compliant.
· Pin compatible with IDT 77211 SAR

Integrated Device Technology, Inc.

SYSTEM-LEVEL FUNCTIONAL BLOCK DIAGRAM

155 Mbps ATM SAR CONTROLLER
WITH ABR SUPPORT FOR PCI-BASED
NETWORKING APPLICATIONS

PRELIMINARY

INFORMATION

IDT77222

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

33 M H Z

IDT77222

155Mbps

P C I A T M
ABR SAR

P H Y

Rx U TO PIA B us

Tx U TO P IA B us

U tility B u s

155M bps

1 6 K x 3 2

S R A M

EEPROM

80.0M HZ O S C.

PCI BUS

PROM

5349 drw 01

I
I
n

t
er

f
a

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

P C I

In terface

PCI Bus

T ra nsm it

C o n tro l

T x

U to p ia

In terface

S R A M IN T E R F A C E

R eceive

C o n tro l

R x

U top ia

Interface

T x U to p ia
Bus

S R A M

Bus

R x U to p ia

Bus

U tilit y

E E P R O M O U T

5 3 4 9 d rw 0 2

E E P R O M IN

Block Diagram of the IDT77222

DESCRIPTION

The IDT77222 is a member of IDT's family of SAR products

for Asynchronous Transfer Mode (ATM) networks. The
IDT77222 performs both the ATM Adaptation Layer (AAL)
Segmentation and Reassembly (SAR) function and the ATM
layer protocol functions.

A Network Interface Card (NIC) or internetworking product

based on the IDT77222 uses host memory, rather than local
memory, to reassemble Convergence Sublayer Protocol Data
Units (CS-PDUs) from ATM cell payloads received from the
network. When transmitting, as CS-PDUs become ready,
they are queued in host memory and segmented by the

IDT77222 into ATM cell payloads. From this, the IDT77222
then creates complete 53-byte ATM cells which are sent
through the network. The IDT77222's on-chip PCI bus master
interface provides efficient, low latency DMA transfers with the
host system, while its UTOPIA interface provides direct con-
nection to PHY components used in 25.6 Mbps to 155 Mbps
ATM networks.

The IDT77222 is fabricated using state-of-the-art CMOS

technology, providing the highest levels of integration, perfor-
mance and reliability, with the low-power consumption char-
acteristics of CMOS.

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

PACKAGE PINOUT

Vcc

AD(31)

AD(30)

AD(29)

AD(28)

AD(27)

AD(26)

GND

AD(25)

AD(24)

C/BE(3)

IDSEL

AD(23)

AD(22)

GND

AD(21)

Vcc

AD(20)

AD(19)

AD(18)

AD(17)

AD(16)

GND

C/BE(2)

Vcc

FRAME

IRDY

TRDY

DEVSEL

STOP

GND

INTA

Vcc

PERR

SERR

PAR

C/BE(1)

AD(15)

GND

AD(14)

AD(13)

AD(12)

AD(11)

AD(10)

AD(9)

AD(8)

GND

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

GND
PHY_INT

PHY_RST

UTL_ALE
UTL_RD

UTL_WR

GND

UTL_AD(7)

UTL_AD(6)

UTL_AD(5)

UTL_AD(4)

Vcc

UTL_AD(3)

GND

UTL_AD(2)

UTL_AD(1)

UTL_AD(0)

Vcc

SAR_CLK

GND

SR_I/O(30)

SR_I/O(29)

GND

SR_I/O(28)

SR_I/O(27)

SR_I/O(26)

SR_I/O(25)

SR_I/O(24)

Vcc

SR_I/O(23)

GND

SR_I/O(22)

SR_I/O(21)

EEDO

EEDI

EESCLK

EECS

Vcc

E_CE

SR_I/O(31)

SR_I/O(20)

SR_I/O(19)

SR_I/O(18)

SR_I/O(17)

GND

SR_I/O(16)

SR_I/O(15)

SR_I/O(14)

SR_I/O(13)

SR_I/O(12)

SR_I/O(11)

Vcc

5
3

5
4

5
5

5
6

5
7

5
8

5
9

6
0

6
1

6
2

6
3

6
4

6
5

6
6

6
7

6
8

6
9

7
0

7
1

7
2

7
3

7
4

7
5

7
6

7
7

7
8

7
9

8
0

8
1

8
2

8
3

8
4

8
5

8
6

8
7

8
8

8
9

9
0

9
1

9
2

9
3

9
4

9
5

9
6

9
7

9
8

9
9

1
0
0

1
0
1

1
0
2

1
0
3

1
0
4

/
B

(
0

)

(
7

)

(
6

)

(
5

)

(
4

)

(
3

)

(
2

)

(
1

)

(
0

)

/
C

I
/
O

(
0

)

I
/
O

(
1

)

I
/
O

(
2

)

I
/
O

(
3

)

I
/
O

(
4

)

I
/
O

(
5

)

I
/
O

(
6

)

I
/
O

(
7

)

I
/
O

(
8

)

I
/
O

(
9

)

I
/
O

(
1

)

208 2

0
7

2
0
6

2
0
5

2
0
4

2
0
3

2
0
2

2
0
1

2
0
0

1
9
9

1
9
8

1
9
7

1
9
6

1
9
5

1
9
4

1
9
3

1
9
2

1
9
1

1
6
1

1
9
0

1
8
9

1
8
8

1
8
7

1
8
6

1
8
5

1
8
4

1
8
3

1
8
2

1
8
1

1
8
0

1
7
9

1
7
8

1
7
7

1
7
6

1
7
5

1
7
4

1
7
3

1
7
2

1
7
1

1
7
0

1
6
9

1
6
8

1
6
7

1
6
6

1
6
5

1
6
4

1
6
3

1
6
2

1
6
0

1
5
9

1
5
8

1
5
7

I
T

/
R

(
7

)

(
6

)

(
5

)

(
4

)

(
3

)

(
2

)

(
1

)

(
0

)

/
T

(
7

)

(
6

)

(
5

)

(
4

)

(
3

)

(
2

)

(
1

)

(
0

)

(
1

)

(
0

)

Index

5349 drw 03

IDT77222 SAR Controller

With ABR Support

208 Pin PQFP

Pinout

PU-208

Refer to PSC-4053 for

detailed package drawing

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

PIN DEFINITIONS

Pin #

Name

I/O

Bus Name

Description

power

AD(31)

I/O

PCI

address/data line

AD(30)

I/O

PCI

address/data line

AD(29)

I/O

PCI

address/data line

AD(28)

I/O

PCI

address/data line

AD(27)

I/O

PCI

address/data line

AD(26)

I/O

PCI

address/data line

GND

power

GND

power

AD(25)

I/O

PCI

address/data line

AD(24)

I/O

PCI

address/data line

C/BE(3)

I/O

PCI

bus command

IDSEL

PCI

bus ID select

AD(23)

I/O

PCI

address/data line

AD(22)

I/O

PCI

address/data line

GND

power

GND

power

AD(21)

I/O

PCI

address/data line

power

AD(20)

I/O

PCI

address/data line

AD(19)

I/O

PCI

address/data line

AD(18)

I/O

PCI

address/data line

AD(17)

I/O

PCI

address/data line

AD(16)

I/O

PCI

address/data line

GND

power

GND

power

C/BE(2)

I/O

PCI

bus command

power

Frame

I/O

PCI

cycle frame

IRDY

I/O

PCI

initiator ready

TRDY

I/O

PCI

target ready

DEVSEL

I/O

PCI

target indicating address decode

STOP

I/O

PCI

target requesting master to stop

GND

power

GND

power

INTA

PCI

"interrupt" "A" "request"

power

PERR

I/O

PCI

data parity error

SERR

PCI

system error

PAR

I/O

PCI

parity (for AD[0:31] and C/BE[0:3])

C/BE(1)

I/O

PCI

bus command

AD(15)

I/O

PCI

address/data line

GND

power

GND

power

AD(14)

I/O

PCI

address/data line

AD(13)

I/O

PCI

address/data line

AD(12)

I/O

PCI

address/data line

AD(11)

I/O

PCI

address/data line

5349 tbl 01

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

PIN DEFINITIONS (CON'T.)

Pin #

Name

I/O

Bus Name

Description

AD(10)

I/O

PCI

address/data line

AD(9)

I/O

PCI

address/data line

AD(8)

I/O

PCI

address/data line

GND

power

GND

power

(0)

I/O

PCI

bus command

AD(7)

I/O

PCI

address/data line

power

AD(6)

I/O

PCI

address/data line

AD(5)

I/O

PCI

address/data line

AD(4)

I/O

PCI

address/data line

GND

power

GND

power

AD(3)

I/O

PCI

address/data line

AD(2)

I/O

PCI

address/data line

AD(1)

I/O

PCI

address/data line

AD(0)

I/O

PCI

address/data line

GND

power

N/C

No connect

SR_WE

SRAM

Write enable

SR_A13

SRAM

Address line

SR_A8

SRAM

Address line

SR_A9

SRAM

Address line

SR_A11

SRAM

Address line

SR_OE

SRAM

Output Enable control

SR_A10

SRAM

Address line

SR_CS

SRAM

Chip Select

N/C

No connect

GND

power

N/C

No connect

power

SR_A12

SRAM

Address line

SR_A7

SRAM

Address line

SR_A6

SRAM

Address line

SR_A5

SRAM

Address line

SR_A4

SRAM

Address line

SR_A3

SRAM

Address line

SR_A2

SRAM

Address line

SR_A1

SRAM

Address line

SR_A0

SRAM

Address line

GND

power

GND

power

SR_I/O(0)

I/O

SRAM

Data input/output line

SR_I/O(1)

I/O

SRAM

Data input/output line

SR_I/O(2)

I/O

SRAM

Data input/output line

SR_I/O(3)

I/O

SRAM

Data input/output line

SR_I/O(4)

I/O

SRAM

Data input/output line

5349 tbl 02

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

PIN DEFINITIONS (CON'T.)

Pin #

Name

I/O

Bus Name

Description

SR_I/O(5)

I/O

SRAM

Data input/output line

GND

power

SR_I/O(6)

I/O

SRAM

Data input/output line

100

SR_I/O(7)

I/O

SRAM

Data input/output line

101

SR_I/O(8)

I/O

SRAM

Data input/output line

102

SR_I/O(9)

I/O

SRAM

Data input/output line

103

SR_I/O(10)

I/O

SRAM

Data input/output line

104

GND

power

105

power

106

SR_I/O(11)

I/O

SRAM

Data input/output line

107

SR_I/O(12)

I/O

SRAM

Data input/output line

108

SR_I/O(13)

I/O

SRAM

Data input/output line

109

SR_I/O(14)

I/O

SRAM

Data input/output line

110

SR_I/O(15)

I/O

SRAM

Data input/output line

111

SR_I/O(16)

I/O

SRAM

Data input/output line

112

GND

power

113

SR_I/O(17)

I/O

SRAM

Data input/output line

114

SR_I/O(18)

I/O

SRAM

Data input/output line

115

SR_I/O(19)

I/O

SRAM

Data input/output line

116

SR_I/O(20)

I/O

SRAM

Data input/output line

117

SR_I/O(21)

I/O

SRAM

Data input/output line

118

SR_I/O(22)

I/O

SRAM

Data input/output line

119

GND

power

120

SR_I/O(23)

I/O

SRAM

Data input/output line

121

power

122

SR_I/O(24)

I/O

SRAM

Data input/output line

123

SR_I/O(25)

I/O

SRAM

Data input/output line

124

SR_I/O(26)

I/O

SRAM

Data input/output line

125

SR_I/O(27)

I/O

SRAM

Data input/output line

126

SR_I/O(28)

I/O

SRAM

Data input/output line

127

GND

power

128

SR_I/O(29)

I/O

SRAM

Data input/output line

129

SR_I/O(30)

I/O

SRAM

Data input/output line

130

SR_1/O(31)

I/O

SRAM

Data input/output line

131

E_CE

EPROM

EPROM chip select

132

power

133

EECS

EEPROM

chip select

134

EESCLK

EEPROM

clock

135

EEDI

EEPROM

Data input

136

EEDO

EEPROM

Data output

137

GND

power

138

SAR_CLK

SAR clock input

139

power

140

UTL_AD(0)

I/O

Utility

address/data bus

141

UTL_AD(1)

I/O

Utility

address/data bus

142

UTL_AD(2)

I/O

Utility

address/data bus

143

GND

power

144

UTL_AD(3)

I/O

Utility

address/data bus

5349 tbl 03

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

PIN DEFINITIONS (CON'T.)

Pin #

Name

I/O

Bus Name

Description

145

power

146

UTL_AD(4)

I/O

Utility

address/data bus

147

UTL_AD(5)

I/O

Utility

address/data bus

148

UTL_AD(6)

I/O

Utility

address/data bus

149

UTL_AD(7)

I/O

Utility

address/data bus

150

GND

power

151

UTL_WR

Utility

write control

152

UTL_RD

Utility

read control

153

UTL_ALE

Utility

address latch enable

154

PHY_RST

PHY

rest control

155

PHY_INT

PHY

interrupt input from PHY

156

GND

power

157

power

158

UTL_CS(0)

Utility

chip select (0)

159

UTL_CS(1)

Utility

chip select (1)

160

TxData(0)

UTOPIA

transmit data bit 0

161

TxData(1)

UTOPIA

transmit data bit 1

162

TxData(2)

UTOPIA

transmit data bit 2

163

TxData(3)

UTOPIA

transmit data bit 3

164

GND

power

165

TxData(4)

UTOPIA

transmit data bit 4

166

TxData(5)

UTOPIA

transmit data bit 5

167

power

168

TxData(6)

UTOPIA

transmit data bit 6

169

TxData(7)

UTOPIA

transmit data bit 7

170

GND

power

171

TxSOC

UTOPIA

transmit start of cell

172

TxEnb

UTOPIA

transmit enable control

173

TxFull

/TxCLAV

UTOPIA

transmit buffer full

174

TxCLK

UTOPIA

transmit data sync clock

175

GND

power

176

RxData(0)

UTOPIA

receive data bit 0

177

RxData(1)

UTOPIA

receive data bit 1

178

RxData(2)

UTOPIA

receive data bit 2

179

RxData(3)

UTOPIA

receive data bit 3

180

GND

power

181

RxData(4)

UTOPIA

receive data bit 4

182

RxData(5)

UTOPIA

receive data bit 5

183

RxData(6)

UTOPIA

receive data bit 6

184

RxData(7)

UTOPIA

receive data bit 7

185

RxSOC

UTOPIA

receive start of cell

186

RxEnb

UTOPIA

receive enable control

187

RxEmpty

/RxCLAV

UTOPIA

receive buffer empty

188

GND

power

189

RxClk

UTOPIA

receive data sync clock

190

PHY_Clk

UTOPIA

Transmit sync clock input

191

TxParity

UTOPIA

transmit data parity bit

192

GND

power

5349 tbl 04

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

-0.3

6.5

Input Voltage

- 0.3

+ 0.3

OUT

Output Voltage

- 0.3

+ 0.3

stg

Storage Temperature

-55

125

deg.C

5349 tbl 06

CLOCKING

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

4.75

5.25

Input Voltage

Operating temperature

deg.C

titr

Input TTL rise time

____

titf

Input TTL rall time

____

5349 tbl 07

CAPACITANCE

Symbol

Parameter

Rate

Min.

Max.

Unit

SAR_CLK

SAR clock input freq.

155Mb/s

MHz

25Mb/s

MHz

PHY_CLK

PHY clock input freq.

155Mb/s

19.44

MHz

25Mb/s

MHz

PCI_CLK

PCI clock input freq.

33MHz

33.3

MHz

5349 tbl 08

Symbol

Parameter

Condition

Min.

Max.

Typical

Unit

Input Capacitance

except PCI Bus

____

OUT

Output Capacitance

all outputs

____

bid

Bi-Directional Capacitance

all bi-directional pins

____

inpci

PCI Bus Input Capacitance

PCI Bus inputs

____

clkpci

PCI Bus Clock Input Capacitance

____

idsel

PCI Bus ID Select Input Capacitance

____

5349 tbl 09

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

DC OPERATING CONDITIONS

Symbol

Parameter

Condition

Min.

Max.

Typical

Unit

Vil

Low-level TTL input voltage

____

-0.7V

0.8

____

Vih

High-level TTL input voltage

____

+ 0.2V

____

Vol

Low-level TTL output voltage

except PCI Bus

____

0.4

____

Vol

PCI Bus Low-level TTL output voltage

PCI Bus voltage

____

0.55

____

Voh

High-level TTL output voltage

____

2.4

____

Iol

Low-level TTL output current:
SR_A(18-0)

+ 0.4V

____

Ioh

High-level TTL output current:
SR_A(18-0)

2.4V

-4

____

Iol

Low-level TTL output current:

RxEnb

, RxClk, TxSOC,

TxData (7-0),

TxEnb

, TxParity,

TxClk,

SR_D31-0

+ 0.4V

____

Ioh

High-level TTL output current:

RxEnb

, RxClk, TxSoc,

TxData7-0,

TxEnb

, TxParity,

TxClk,

SR_WE

SR_CS

SR_I/O(31-0)

2.4V

-2

____

Iol

Low-level TTL output current:
UTL_AD(7-0),

UTL_RD

UTL_WR

UTL_ALE

UTL_CS0/1

, EESCLK, EECS,

EEDO,

PHY_RST

+ 0.4V

____

Ioh

High-level TTL output current:
UTL_AD(7-0),

UTL_RD

UTL_WR

, UTL_ALE,

UTL_CS0/1

, EESCLK, EECS,

EEDO,

PHY_RST

2.4V

-1

____

Iil

Input leakage current

< V

< Vdd

-1

____

Ityp

Dynamic Supply Current

____

300

250

5349 tbl 10

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

AC OPERATING CONDITIONS

AC TEST CONDITIONS

Input Pulse Levels

0 to 3.0V

Input Rise/Fall Times

2ns

Input Timing Ref. Level

1.5V

Output Ref. Level

1.5V

AC Test Load

See Figure Below

5349 tbl 11

1.5V

I/O

= 50

20 30 50

100

200

tCD

(Typical, ns)

Capacitance (pF)

5349 drw 05

NAND TREE

The NAND Chain provides a simple test to verify that all bond wires are installed correctly and that all pads are correctly

soldered on a PCB.

All signal pads are linked in a NAND chain, which is enabled by asserting a high, or "1", on NAND_EN (pin 201). Asserting

a "1" on the other inputs forces NAND_OUT (pin 193) to "1". By successively setting the inputs to "0", starting at CLK_OUT
(pin 198) and moving to TXPARITY (pin 191), NAND_OUT will toggle with each change.
1. Apply a "1" to NAND_EN.
2. Set all the I/O's in the chain to "0" and NAND_OUT should be a "1".The connection order of the pins in the chain are

shown in the NAND Tree Pin Order table located on the following page.

3. Set CLK_OUT to a "0" and the NAND_OUT should be a "0".
4. Leaving pin 198 at a "1" set

RST

(pin 203) to "1" and NAND_OUT should be a "1".

5. Repeat for all remaining I/O's in the NAND chain.

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

Signal Name

Pin

Num ber

Signal Name

Pin

Num ber

Signal Name

Pin

Num ber

Signal Name

Pin

Num ber

C L K _ O UT

1 9 8

A D [1 2 ]

4 7

S R _I/O [0 6 ]

9 9

UT L _ A D [5 ]

1 4 7

RST

2 0 3

A D [11 ]

4 8

S R _I/O [0 7 ]

1 0 0

UT L _ A D [6 ]

1 4 8

C L K

2 0 4

A D [1 0 ]

4 9

S R _I/O [0 8 ]

1 0 1

UT L _ A D [7 ]

1 4 9

GNT

2 0 5

A D [9 ]

5 0

S R _I/O [0 9 ]

1 0 2

UTL_WR

1 5 1

REQ

2 0 6

A D [8 ]

5 1

S R _I/O [1 0 ]

1 0 3

UTL_RD

1 5 2

A D [3 1 ]

C /

[0 ]

5 5

S R _ I/O [11]

1 0 6

UT L _ A L E

1 5 3

A D [3 0 ]

A D [7 ]

5 6

S R _I/O [1 2 ]

1 0 7

PHY_RST

1 5 4

A D [2 9 ]

A D [6 ]

5 8

S R _I/O [1 3 ]

1 0 8

PHY_INT

1 5 5

A D [2 8 ]

A D [5 ]

5 9

S R _I/O [1 4 ]

1 0 9

UTL_CS[0]

1 5 8

A D [2 7 ]

A D [4 ]

6 0

S R _I/O [1 5 ]

110

UTL_CS[1]

1 5 9

A D [2 6 ]

A D [3 ]

6 3

S R _I/O [1 6 ]

111

T xD ata[0]

1 6 0

A D [2 5 ]

1 0

A D [2 ]

6 4

S R _I/O [1 7 ]

113

T xD ata[1]

1 6 1

A D [2 4 ]

A D [1 ]

6 5

S R _I/O [1 8 ]

114

T xD ata[2]

1 6 2

C /

[3 ]

1 2

A D [0 ]

6 6

S R _I/O [1 9 ]

115

T xD ata[3]

1 6 3

IDSEL

1 3

SR_WE

6 9

S R _I/O [2 0 ]

116

T xD ata[4]

1 6 5

A D [2 3 ]

1 4

S R _ A [1 3 ]

7 0

S R _I/O [2 1 ]

117

T xD ata[5]

1 6 6

A D [2 2 ]

1 5

S R _ A [8 ]

7 1

S R _I/O [2 2 ]

118

T xD ata[6]

1 6 8

A D [2 1 ]

1 8

S R _ A [9 ]

7 2

S R _I/O [2 3 ]

1 2 0

T xD ata[7]

1 6 9

A D [2 0 ]

2 0

S R _ A [11 ]

7 3

S R _I/O [2 4 ]

1 2 2

T xS O C

1 7 1

A D [1 9 ]

2 1

S R _ O E

7 4

S R _I/O [2 5 ]

1 2 3

TxEnb

1 7 2

A D [1 8 ]

2 2

S R _ A [1 0 ]

7 5

S R _I/O [2 6 ]

1 2 4

T xC L AV

1 7 3

A D [1 7 ]

2 3

SR_CS

7 6

S R _I/O [2 7 ]

1 2 5

T xC LK

1 7 4

A D [1 6 ]

2 4

S R _ A [1 2 ]

8 1

S R _I/O [2 8 ]

1 2 6

R xD a ta [0]

1 7 6

C /

[2 ]

2 7

S R _ A [7 ]

8 2

S R _I/O [2 9 ]

1 2 8

R xD a ta [1]

1 7 7

Frame

2 9

S R _ A [6 ]

8 3

S R _I/O [3 0 ]

1 2 9

R xD a ta [2]

1 7 8

IRDY

3 0

S R _ A [5 ]

8 4

S R _I/O [3 1 ]

1 3 0

R xD a ta [3]

1 7 9

TRDY

3 1

S R _ A [4 ]

8 5

E_CE

1 3 1

R xD a ta [4]

1 8 1

DEVSEL

3 2

S R _ A [3 ]

8 6

E E C S

1 3 3

R xD a ta [5]

1 8 2

STOP

3 3

S R _ A [2 ]

8 7

E E S C LK

1 3 4

R xD a ta [6]

1 8 3

INITA

3 6

S R _ A [1 ]

8 8

E E D I

1 3 5

R xD a ta [7]

1 8 4

PERR

3 8

S R _ A [0 ]

8 9

E E D O

1 3 6

R xS O C

1 8 5

SERR

3 9

S R _I/O [0 0 ]

9 2

S A R _C LK

1 3 8

RxEnb

1 8 6

PA R

4 0

S R _I/O [0 1 ]

9 3

UT L _ A D [0 ]

1 4 0

R xC L AV

1 8 7

C /

[1 ]

4 1

S R _I/O [0 2 ]

9 4

UT L _ A D [1 ]

1 4 1

R xC L K

1 8 9

A D [1 5 ]

4 2

S R _I/O [0 3 ]

9 5

UT L _ A D [2 ]

1 4 2

P HY _C LK

1 9 0

A D [1 4 ]

4 5

S R _I/O [0 4 ]

9 6

UT L _ A D [3 ]

1 4 4

T xP a rity

1 9 1

A D [1 3 ]

4 6

S R _I/O [0 5 ]

9 7

UT L _ A D [4 ]

1 4 6

53 49 tbl 12

NAND TREE PIN OREDER

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

Symbol

Parameter

Min.

Max.

Unit

tval

CLK to Output Signal Valid Delay: AD31-0, C/

3-0, PAR,

FRAME

IRDY

DEVSEL

TRDY

STOP

PERR

SERR

tval(ptp)

CLK to Output Signal Valid Delay:

REQ

ton

Float to Signal Active Delay: AD31-0, C/

3-0, PAR,

FRAME

IRDY

DEVSEL

TRDY

STOP

PERR

SERR

____

toff

Signal Active to Float Delay: AD31-0, C/

3-0, PAR,

FRAME

IRDY

DEVSEL

TRDY

STOP

PERR

SERR

____

tsu

Input Setup Time to CL

K :

AD31-0, C/

3-0, PAR,

FRAME

IRDY

DEVSEL

TRDY

STOP

PERR

____

tsu(ptp)

Input Setup Time to CLK:

GNT

, (

REQ

)

10(12)

____

Input Hold Time from CLK: AD31-0, C/

3-0, PAR,

FRAME

IRDY

DEVSEL

TRDY

STOP

PERR

GNT

2 *

____

trst-pwr

Reset Active Time After Power Stable

____

trst-clk

Reset Active Time After CLK Stable

100

____

trst-off

Reset Active to Output Float Delay: AD31-0, C/

3-0, PAR,

FRAME

IRDY

DEVSEL

TRDY

STOP

PERR

SERR

____

thigh

Clock high time

11n

____

tlow

Clock low time

11n

____

5349 tbl 13

* - Does not meet PCI Local Bus revision 2.1 timing specification

PCI BUS (SEE FIGURE 1& 2)

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

UTOPIA BUS (SEE FIGURE 3)

S ym b ol

P aram eter

M in.

M ax.

U nit

T xC lk , R xC lk D e la y fro m P HY _ C L K

_ __ _

T xD a ta (7 -0 ), T xS O C ,

TxEnb

, T xP a rity O utp ut Va lid fro m T xC lk

1 5

TxFull

/T xC L AV S e tup Tim e to T xC lk

1 0

_ __ _

TxFull

/T xC L AV Ho ld Tim e fro m T xC lk

3 * *

_ __ _

RxEnb

O ut p ut Va lid fro m R xC lk

1 5

R xD a ta (7 -0 ), R xS O C S e tup Tim e to R xC lk

1 0

_ __ _

R xD a ta (7 -0 ), R xS O C Ho ld Tim e fro m R xC lk

2 * *

_ __ _

RxEmpty

/R xC L AV S e tup Tim e to R xC lk

1 0

_ __ _

RxEmpty

/R xC L AV Ho ld Tim e fro m T xC lk

2 * *

_ __ _

53 49 tb l 1 4

** - Do es no t me et UTO PIA 1 tim ing s p ec ific ation (A f- phy- 0 017 .00)

UTILITY BUS WRITE CYCLE (SEE FIGURE 4)

UTILITY BUS READ CYCLE (SEE FIGURE 5)

Symbol

Parameter

M in.

M ax.

Unit

tr1

UT L _ A L E P ulse W id th

2 5

_ __ _

tr2

UTL_CS0/1

O utp ut Va lid to UT L _ A L E fa lling e d g e

2 5

_ __ _

tr3

UTL_RD

O utp ut Va lid fro m UT L _ A L E fa lling e d g e

_ __ _

8 0

tr4

UTL_CS0/1

P ulse W id th

2 5 0

_ __ _

tr5

UTL_RD

P ulse W id th

1 8 5

_ __ _

tr6

UT L _ A L E fa lling e d g e to

UTL_RD

ris ing e d g e

2 5 0

_ __ _

tr7

U T L _ A D (7 -0 ) A d d re ss S e tup Tim e to UT L _ A L E fa lling e d g e

3 0

_ __ _

tr8

UT L _ A D (7 -0 ) A d d re ss Ho ld Tim e fro m UT L _ A L E fa lling e d g e

1 0

_ __ _

tr9

UT L _ A D (7 -0 ) D a ta S e tup Tim e to

UTL_CS0/1

ris ing e d g e

8 0

_ __ _

tr1 0

UT L _ A D (7 -0 ) D a ta Ho ld Tim e fro m

UTL_CS0/1

ris ing e d g e

1 0

_ __ _

tr11

UT L _ A L E fa lling e d g e to

UTL_CS0/1

ris ing e d g e

2 2 5

_ __ _

53 49 tb l 1 6

S ym b o l

P aram eter

M in.

M ax.

U nit

tw 1

UT L _ A L E P uls e W id th

2 5

_ __ _

tw 2

UTL_CS0/1

O utp ut Va lid to UT L _ A L E fa lling ed g e

2 5

_ __ _

tw 3

UTL_WR

O utp ut Va lid from UT L _ A LE fa lling e d g e

_ __ _

8 0

tw 4

UTL_CS0/1

P uls e W id th

2 7 5

_ __ _

tw 5

UTL_WR

P uls e W id th

1 7 5

_ __ _

tw 6

UT L _ A L E fa lling e d g e to

UTL_WR

ris ing e d g e

2 2 5

_ __ _

tw 7

U T L _ A D (7 -0 ) A d d re s s S e tup Tim e to UT L _ A L E fa lling e d g e

3 0

_ __ _

tw 8

UT L_ A D (7 -0 ) A d d re s s Ho ld Tim e fro m UT L _ A L E fa lling e d g e

1 0

_ __ _

tw 9

UT L _ A D (7 -0 ) D a ta S e tup Tim e to

UTL_WR

ris ing e d g e

1 8 5

_ __ _

tw 1 0

UT L _ A D (7 -0 ) D a ta Ho ld Tim e fro m

UTL_WR

ris ing e d g e

1 0

_ __ _

tw 11

UT L _ A L E fa lling e d g e to

UTL_CS0/1

ris ing e d g e

2 5 0

_ __ _

53 49 tb l 1 5

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

EPROM (SEE FIGURE 8)

EEPROM (SEE FIGURE 9)

SRAM BUS READ CYCLE (SEE FIGURE 7)

SRAM BUS WRITE CYCLE (SEE FIGURE 6)

Symbol

Parameter

M in.

M ax.

Unit

S R _ A (1 8 -0 ) S e tup Tim e t o

SR_WE

fa lling e d g e

_ __ _

SR_CS

fa lling e d g e to

SR_WE

fa lling e d g e

_ __ _

SR_CS

p uls e w id th

2 5

_ __ _

S R _ I/O (3 1 -0 ) S e tup Tim e to

SR_WE

ris ing e d g e

_ __ _

S R _ I/O (3 1 -0 ) Ho ld Tim e fro m

SR_WE

ris ing e d g e

_ __ _

SR_WE

P uls e W id th

1 0

_ __ _

53 49 tb l 1 7

Symbol

Parameter

M in.

M ax.

Unit

S R _ A ( 1 8 - 0 ) to S R _ I/O (3 1 -0 ) Va lid

_ __ _

1 5

SR_OE

p uls e w id th

2 5

_ __ _

No t e : S R _ I/O (3 1 - 0 ) S e tup a nd Ho ld tim e s a r e g u a r a nte e d b y d e sig n w he n t1 a cc e ss t im e is m e t .

5 3 49 t b l 1 8

Symbol

Parameter

Min.

Max.

Unit

SR_I/O(7-0) Hold Time from

E_CE

rising edge

____

E_CE

Pulse Width

____

SR_A(18-0) Change to SR_I/O(7-0) Valid

____

SR_A(18-0) Pulse Width

____

5349 tbl 19

Symbol

Parameter

Min.

Max.

Unit

Comments

SAR_CLK to Output Signal Valid Delay: EECS, EEDO, EECLK

100

____

software controlled

EEDI Input Setup Time to SAR_CLK

____

software controlled

EEDI Input Hold Time from SAR_CLK

____

software controlled

5349 tbl 20

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

Several software vendors have writen IDT77222 software drivers for various operating systems. Please contact your local

IDT sales representative for a vendor list, or e-mail atmhelp@idt.com.

IDT offers the Sarwin2 demo driver and application suite, which can be used to evaluate the IDT77222 when used with

a IDT NIC reference or evaluation adapter. It may also be used as a reference for sample source code when developing a
proprietary device driver. Please contact your IDT sales representative or e-mail atmhelp@idt.com to obtain a free cdrom.

NIC Reference and Evaluation Adapters

NIC Reference and Evaluation adapters are available in several form factors. Bill of Materials (BOM) and schematics are

available upon request for each of the NIC adapters. A list of current NIC adapter offerings can be found at www.idt.com.

Note: The Micro ABR SAR User Manual provides a detailed description of the 77222 operation and registers.

SAR_CLK

EECLK

EECS

EEDI

EEDO

5349 drw 14

Figure 9. EEPROM Timing

SOFTWARE AND SOFTWARE DRIVERS

IDT77222 155Mb/s ATM Segmentation & Reassembly (SAR) Controller

PRELIMINARY

with ABR for the PCI Local Bus

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

Notes:

Refer to PSC-4053 for detailed package drawing.

Replacing the 77211 with the 77222:

The 77222 PG package is the same package as the 77211 PQF, the 77222 is a direct replacement to the 77211 SAR.
To use the 77222 in a 155 Mbps application a 80 MHz oscillator is required (replace the 50 MHz oscillator used with
the 77211).

PRELIMINARY DATASHEET: DEFINITION

"PRELIMINARY" datasheets contain descriptions for products that are in early release, including features and block
diagrams.

Data Sheet Document History

6/24/98:

Created new document

9/15/99:

Updated software section

6/22/00:

Added PG-208 to package pinout and added PSC-4053 reference. Removed Industrial temp rating.
Changed pin name for pin 198. Updated SRAM, Utility Bus, UTOPIA Bus, EPROM and PCI timing
parameters and diagrams. Updated AC test Conditions section. Added information for NAND Tree.
Changed from Advanced to Preliminary data sheet.

Package

IDT

NNNNN

Device Type

Power

NNN

Speed

Process/

Temp. Range

155

Speed in Mps

77222

155Mbs ATM Segmentation &
Reassembly (SAR) Controller for the
PCI Local Bus

5349 drw 15

208-pin Plastic Quad Flatpack

Low Power CMOS

(Blank)

Commercial

Integrated Device Technology, Inc.

2975 Stender Way, Santa Clara, CA 95054-3090

Telephone: (408) 727-6116

FAX 408-330-1748

Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT77222L-155

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT77222L-155