1999 Integrated Device Technology, Inc.
6.06
MARCH 1999
DSC 3607/3
1
PRELIMINARY
IDT77V500
Features
x
Single chip controller for IDT77V400 Switching Memory
x
One IDT77V500 and one IDT77V400 form the core required
for a 1.24Gbps 8 x 8 port non-blocking switch
x
Supports up to 8192 Virtual Connections (VCs)
x
Per VC queuing for fairness, with four priorities per VC
available for each output port of the switch
x
Capable of supporting CBR, VBR, UBR, and ABR (EFCI)
service classes
x
Low power dissipation
430mW (typ.)
x
Optional header modification operation
x
Multicasting and Broadcasting capability
x
Provides congestion management support through EFCI,
CLP, and EPD functionality
x
System clock cycle times as fast as 27ns (37MHz)
x
Option available for resolving contention issues between
multiple IDT77V500 configurations
SWITCHStAR
TM
ATM CELL BASED
1.24Gbps NON-BLOCKING
INTEGRATED SWITCH CONTROLLER
Typical 8 x 8 Switch Configuration using the IDT77V500 Switch Controller
x
One IDT77V500 can manage up to eight IDT77V400's
without derating for larger switch configurations
x
Industrial temperature range (-40 C to +85 C) is available
x
Single +3.3V 300mV power supply
x
Available in a 100-pin Thin Plastic Quad Flat Pack (TQFP)
Description
The IDT77V500 ATM Cell Based Switch Controller, when paired
with the IDT77V400 Switching Memory, forms the core control logic
and switch fabric for a 1.24Gbps non-blocking ATM switch. The
IDT77V500 manages all of the switch traffic moving through the
IDT77V400, commanding the storage of incoming ATM cells and
interpreting and modifying the cell header information as necessary
for data flow through the switch. It then uses the header information,
including priority indicators, to queue and direct the individual cells for
transmission out the appropriate output port of the IDT77V400.
The IDT77V500 utilizes Per Virtual Connection (VC) Queuing to
keep track of each call, and has the capacity to keep track of as many
8-bit Processor/
Call Setup
Manager
IDT77V500
Switch
Controller
IDT77V400
Switching
Memory
IDT77155
155Mbps
PHY
Port 0
Port 0
Port 7
Port 7
Control
Control
Data
Data
External Interface
for Global Setup
and Control
3607 drw 01
(for example,
IDT77V550
IDT79RV3041,
IDT79R36100,
or IDT79RV4640)
IDT77155
155Mbps
PHY
IDT77155
155Mbps
PHY
IDT77155
155Mbps
PHY
/
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
2
Functional Block Diagram
NOTES:
1. SCLK and Reset are inputs to all blocks.
2. Outputs are always enabled (active).
Description (cont.)
as 8192 individual VC queues. There are four possible priorities
available for each of the assigned outputs of the Switching Memory,
and CBR, VBR, UBR, and ABR-EFCI service classes are supported
by the Switch Controller. Multicasting and broadcasting services are
provided, requiring only the appropriate header information to execute
these operations automatically without requiring multiple Switching
Memory entries.
The IDT77V500 also has a mode for managing and transmitting
pocketized data, enabling easy transition between packet oriented
networks such as Ethernet and FDDI and ATM cell oriented networks.
The IDT77V500 has an 8-bit Manager Bus interface, MDATA0-7, to
a Call Setup Manager processor for the configuration activity and call
setup operation. When a Call Setup Cell is received by the IDT77V400,
the cell is directed to a specified output port and the payload
processed by the Call Setup Manager. The new Virtual Connection
(VC) is then established in the Queue Manager of the IDT77V500,
with all operations executed across the 8-bit Manager Bus. Subse-
quent cells of that particular VC are then prioritized and directed by the
Switch Controller as they are received by the IDT77V400; no further
interaction with the Call Manager processor is required for ongoing
queue and cell management.
The IDT77V500 supports a major subset of the available com-
mands and configurations of the IDT77V400 Switching Memory.
Please refer to the SWITCHStAR User Manual for additional feature
details and implementation information.
The IDT77V500 is fully 3.3V LVTTL compatible, and is packaged
in an 100-pin Thin Plastic Quad Flatpack (TQFP).
IOD0-31
32
Control
Logic
OFRM0-7
CRCERR
SCLK
CMD0-5
6
3607 drw 02
Call
Setup
Manager
MDATA0-7
MSTRB
MD/
C
MR/
W
Switching Memory Interface
Output
Service
and
Arbitration
State
Machine
Queue Manager
Output Queues
and
Link Registers
RESETI
RESETO
CBRCLK2
CBRCLK3
SFRM
Reset
(1)
SCLK
(1)
(2)
(2)
(2)
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
3
Package Diagram
(1,2,3)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IOD
5
IOD
4
V
SS
V
CC
IOD
3
IOD
2
IOD
1
CRCERR
V
CC
MDATA
0
MDATA
1
MDATA
2
V
CC
V
SS
MDATA
5
MDATA
6
MDATA
3
MDATA
4
NC
NC
NC
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
RESETI
NC
NC
NC
CMD3
MSTRB
MR/
W
NC
CMD4
CMD5
V
CC
IOD
24
NC
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
IOD
13
V
CC
V
SS
IOD
11
IOD
10
IOD
9
IOD
8
IOD
7
NC
NC
IOD
12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
IDT77V500PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
3607 drw 03
V
CC
V
CC
IOD
0
IOD
6
IOD
14
IOD
15
IOD
16
IOD
17
IOD
18
IOD
19
NC
V
SS
V
CC
IOD
20
IOD
21
IOD
22
IOD
23
NC
V
SS
IOD
25
IOD
26
IOD
27
IOD
28
IOD
29
IOD
30
IOD
31
V
SS
V
SS
V
SS
V
CC
V
SS
OFRM
0
OFRM
1
OFRM
2
OFRM
3
OFRM
4
OFRM
5
OFRM
6
MDATA
7
MD/
C
V
CC
V
SS
CMD2
CMD1
CMD0
RESETO
SCLK
CBRCLK2
CBRCLK3
SFRM
OFRM7
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
4
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6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
5
Absolute Maximum Ratings
(1)
NOTES:
1.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2.
V
TERM
must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 0.3V.
Recommended DC Operating
Conditions
(2)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
Capacitance
(T
A
= +25C, f = 1.0MH
z
)
TQFP ONLY
NOTES:
1.
V
IL
> -1.5V for pulse width less than 10ns.
2.
V
TERM
must not exceed Vcc + 0.3V or Vss 0.3V.
3.
V
TERM
must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 0.3V.
Maximum Operating
Temperature and Supply Voltage
(1)
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6
3
NOTE:
1. This is the parameter T
A
.
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
6
NOTE:
1. At f = f
max
SCLK is cycling at maximum frequency and all inputs are cycling at 1/t
CYC1
, using AC input levels of V
SS
to 3.0V.
DC Electrical Ccharacteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V 0.3V)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V 0.3V)
AC Test Conditions
NOTE:
1. For MDATA, IOD, and OFRM pins only.
Figure 1. AC Output Test Load
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6
3
Figure 2. Output Test Load
(for High-Impedance parameters)
* Including scope and jig.
3607 drw 05
590
50pF
435
3.3V
DATA
OUT
590
5pF*
435
3.3V
DATA
OUT
3607 drw 04
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
7
NOTES:
1. RESETI must be held High for 8 SCLK cycles. After RESETI transitions Low 8191 cycles are required before the Status Acknowledge bits will indicate that the internal
reset process in complete.
2. Transition is measured +/-200mV from Low or High impedance voltage with the Output Test Load (Figure 2).
This parameter is guaranteed by device characterization, but is not production tested.
3. Cycle units insure that the SCLK recognizes the state of CBRCLK.
AC Electrical Characteristics Over the Operating Temperature Range
(V
CC
= 3.3V 0.3V)
5
2
S
0
0
5
V
7
7
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&
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6
3
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
8
Control Interface Timing Waveform
(1)
Control Interface Commands
(1)
NOTES:
1. This waveform describes the command interaction across the IOD Bus to the IDT77V400 Switching Memory.
2. The result of this GET STATUS command is that an ISAM is full and ready to be stored to the Fusion Memory of the IDT77V400.
NOTES:
1. CMD bus commands not defined in this table are undefined and are not implemented by the IDT77V500.
2. "x" represents the specific ISAM or OSAM being accessed (IP0-IP7 or OP0-OP7 respectively).
3. "n" represents the appropriate bit of the binary representation of the ISAM or OSAM being accessed (000 to 111).
GET
STATUS
STORE
ISAM
PUT
HEADER
GET
HEADER ISAM
GET
STATUS
SCLK
CRCERR
3607 drw 06
CMD0-5
IOD0-31
Input -
Old Header
[ CRC ERROR = LOW ]
Output -
New Header
[ AVAILABLE FOR NEXT COMMAND ]
Output -
Cell Addr
t
CYC
t
CH
t
CL
t
CDC
t
DCC
t
SIO
t
SCRC
t
HCRC
t
CDIO
t
DCIO
STATUS
STATUS
(2)
t
HIO
(2)
t
CDIO
t
DCIO
)
0
:
5
D
M
C
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t
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m
m
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C
5
4
3
2
1
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(
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(
n
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3
(
n
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n
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1
0
0
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(
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n
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3
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x
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n
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1
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0
1
l
b
t
7
0
6
3
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
9
NOTE:
1. OFRM1-7 become CBUS1-7 (Outputs) during cell bus operations to arbitrate between multiple IDT77V500's.
SFRM, CBUS, and OFRM Timing Waveforms
Manager Commands
(1)
NOTE:
1. Manager Command codes not defined in this table are not to be used.
SCLK
OFRM
3607 drw 07
t
OFP
OFRM/CBUS
t
CDOF
t
DCOF
(1)
SFRM
t
DCS
t
CDS
d
n
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6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
10
M
ana
ger Bus R
ead
Ti
m
i
ng
W
a
v
e
f
o
r
m
(1
)
Mana
ger
Bus Wr
i
t
e Ti
m
i
ng W
a
v
e
f
o
r
m
(1
)
NOTES:
1
.
Write operations, both for Commands and Data, are synchronous to the rising edge of
MSTRB
. The data placed on the MDATA pins is determined by the state of the MD/
C
pin.
2
.
Either a Read cycle was completed or a Status Acknowledge was executed immediately prior to the first
MSTRB
of this write waveform.
3
.
The combination of
MSTRB
Low and MR/
W
High (Read mode) asynchronously enables the MDATA pins as outputs.
The data placed on the MDATA pins is determined by the state of the MD/
C
pin.
4
.
After the Command is written, the Manager must take MR/
W
High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High Bit 7 of the sta
tus register under these
conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on
possible higher priority operations that the IDT77V500 must support.
5
.
A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register).
MD/
C
MSTRB
MR/
W
3607 drw 08
t
SMRW
t
HMRW
t
SMD
t
HMD
MDATA
t
MCH
t
MCL
t
MCYC
t
SM
t
HM
Write first
8 ADDR bits
Acknowledge Read
t
AMD
DATA
OUT
DATA
OUT
CMD
IN
ADDR
IN
ADDR
IN
t
OHMD
Write last
8 ADDR bits
Write Cycle-
Read Command
(2)
(3)
DATA
OUT
DATA
OUT
DATA
OUT
(4)
Read Byte 0
Acknowledge Read
Acknowledge Read
Valid Command Acknowledge
t
AMD
t
OHMD
t
SMRW
t
SM
Read Byte 1
(5)
MDATA
MSTRB
t
SM
t
HM
3607 drw 09
t
SMRW
t
HMRW
t
SMD
t
HMD
MR/
W
MD/
C
t
MCH
t
MCL
t
MCYC
DATA
IN
DATA
IN
CMD
IN
DATA
OUT
Write Data Byte 0
Write Data Byte 12
Write Cycle-
Write Command
Acknowledge Read
t
OHMD
T0
T12
t
AMD
DATA
OUT
(3)
(4)
Acknowledge Read
DATA
OUT
DATA
OUT
(5)
Acknowledge Read
Acknowledge Read
Valid Command Acknowledge
t
SM
t
SMRW
(2)
NOTES:
1
.
Write operations, both for Commands and Data, are synchronous to the rising edge of
MSTRB
. The data placed on the MDATA pins is determined by the state of the MD/
C
pin.
2
.
The combination of
MSTRB
Low and MR/
W
High (Read mode) asynchronously enables the MDATA pins as outputs. That is, data is available to be read one asynchronous t
AMD
time after the falling edge of
MSTRB
if MR/
W
is HIGH.
3
.
After the Command is written, the Manager must take MR/
W
High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High Bit 7 of the sta
tus register under these
conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on
possible higher priority operations that the IDT77V500 must support.
4
.
A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register).
5
.
Waveform illustrates first two bytes of data only. Additional bytes may be available based on command used.
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
11
The Constant Bit Rate (CBR) functionality of the IDT77V500
provides both the opportunity for scheduling priority traffic at a regular
interval and traffic shaping capability. Two external CBR clocks,
CBRCLK3 and CBRCLK2, are available and associated with Output
Priority 3 (Highest Priority) and Priority 2 respectively. Calls assigned
to a particular CBR VC in the IDT77V500 Per VC Table are linked
together in a CBR Per VC list by output, so that a cell from each VC
of a particular CBR Per VC list are serviced on each cycle through the
list. The CBR Per VC List is identified by both the output and CBR
priority on that output; for example, OPyCBRx VC list represents
Output y (Output number 0-7) and CBR priority x (CBR priority 3 or 2).
Figure 3 is an example of an OPyCBRx VC List with four VCs in the
list: 100 (the first entry in the list), 200, 300 and 400. The arrows
indicate the linking sequence in this VC List. Figure 3 will be used with
the CBR Clock Functional Waveforms to illustrate two basic functional
implementations using the CBR Clocks.
CBR Clock Functional Waveform Example 1 uses the
CBR clocks to frame execution of the OPyCBRx VC List. A cell from
a specific VC on the OPyCBRx VC List is scheduled on each rising
clock edge of SCLK after a falling edge of CBRCLKx. The cell will then
be transmitted when output y is available and other previously
scheduled Input and Output ports of the IDT77V400 have been
serviced. This delay can be as long as 65 SCLK cycles maximum for
each cell in the CBR VC List , although it will typically be significantly
less. This delay needs to be taken into account, as the next cell in the
OPyCBRx VC List will not be scheduled until the previous cell in the
list has been serviced. Thus enough CBRCLKx pulses need to be
provided to make sure all potential cells in the OPyCBRx VC List are
CBR Functional Description
Figure 3.
OPyCBRx VC List Example
scheduled. This waveform illustrates the ideal case of each cell being
immediately transmitted after scheduling, enabling the scheduling
and transmission of the next cell in the OPyCBRxVC List on the next
SCLK rising edge. CBRCLKx HIGH for eight SCLK cycles or more
tells the controller that the pointer should be moved back to the top of
the CBR VC List if all the VCs in the list have been serviced. Thus the
user can establish a frame duration and be assured that a cell from
each VC in the OPyCBRx VC List is transmitted in each frame time.
Sub lists can also be established within the CBR VC List so that a
particular VC could be weighted to ship more cells per frame than the
others.
Example 2 illustrates using very slow CBR clocks (tCHx greater
than or equal to 8 SCLKs) toshape traffic in a VBR form of implemen-
tation. A cell from a VC on the OPyCBRx VC List is again scheduled
on each rising clock edge of SCLK after a falling edge of CBRCLKx,
but since t
CH
x is HIGH for more than eight SCLKs, there is more direct
control over the exact time in which each cell of the VC List is
scheduled. The single cell will then be transmitted when the output is
available and other previously scheduled Input and Output ports of the
IDT77V400 have been serviced (there is again the potential 65 SCLK
delay based on other traffic passing through the IDT77V400). The
IDT77V500 will service all of the VCs in the OPyCBRx VC List
because the count will prevent the pointer from returning to the top of
the CBR VC List until all VCs on the list with cells have been serviced.
The user can thus more closely manage the transmission of cells with
this slower CBR clock rate because it is more directly related to
individual CBRCLKx High-to-Low transitions.
3607 drw 10
100
200
300
400
Beginning
End
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
12
NOTES:
1. This example shows the procedure recommended for use of direct CBR scheduling. "x" for this waveform represents either 2 or 3, depending on which CBRCLK is used (CBRCLK2 or CBRCLK3)
("y" represents the specific output (0-7)). The OPyCBRx VC List for this example is defined in figure 3.
2. A cell from a VC on the OPyCBRx VC List is scheduled on each rising clock edge of SCLK after a falling edge of CBRCLKx.
3. This example shows four VC's in the OPyCBRx VC List. The number of VC's in the OPxCBRx VC List may be as large as 8192.
4. The period between reinitiation of the OPyCBRx VC List defines the frame size; that is, the amount of time between starting the transmissions from the top of the OPyCBRx VC List.
CBRCLKx must be HIGH for eight clocks or more to reinitiate the transmission sequence at the start of the OPyCBRx VC List.
CBR Clock Functional Waveform Example 2 - VBR/CBR Implementation (t
CH
x > 8 SCLK)
(1)
CBR Clock Parameters
(1)
CBR Clock Functional Waveform Example 1 - CBR Frame Implementation (Fast CBRCLK with
Frame Timing)
(1)
NOTES:
1. This example shows the use of a slower CBRCLK (t
CH
x > 8 SCLK) to provide VBR/CBR traffic shaping. For this waveform "x" represents either 2 or 3, depending on which CBRCLK is used
(CBRCLK2 or CBRCLK3). ("y" represents the specific output (0-7)) The OPyCBRx VC List for this example is defined in Figure 3.
2. A cell from a VC on the OPyCBRx VC List is scheduled on each rising edge of SCLK after a falling edge of CBRCLKx.
3. t
CH
x
>
8 SCLK so that a cell is scheduled after each falling edge of CBRCLKx.
4. The pointer has moved back to the beginning of the OPyCBRx VC List.
NOTES:
1. "x" for this waveform represents either 2 or 3, depending on which CBRCLK is used (CBRCLK2 or CBRCLK3).
CBRCLKx
t
CLx
t
CHx
t
CYCx
3607 drw 11
(2)
(3)
SCLK
CBRCLKx
100
200
300
400
(4)
100
200
300
400
(2)
(3)
3607 drw 12
100
SCLK
(3)
cont'd
waveform
CBRCLKx
(2)
see cont'd
waveform
3607 drw 13
(4)
200
300
100
400
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
13
Re
s
e
t
Wave
fo
r
m
S
NOTES:
1
.
RESETI must be held HIGH
for 8 SCLK cycles. When RESETI goes
LOW again 8191 cycles are used prior to the
Status Acknowledge bits showing the internal reset process is complete.
2
.
This delay should typically be much less than two SCLK cycles. RESETO remains HIGH until START Command is received from the C
all Setup Manager.
SCLK
RESETI
3607 drw 14
1
27812
8190
8191
1
t
RSI
RESETO
(1)
(2)
2
2 clock cycles max.
6.42
IDT77V500 Preliminary
SWITCHStAR Switch Controller Industrial and Commercial Temperature Range
14
Ordering Information
A
Power
99
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
Commercial (0
C to +70
C)
Industrial (-40
C to +85
C)
PF
100-pin TQFP (PK100-1)
27
25
S
Standard Power
XXXXX
Device
Type
ATM Cell Based Switch Controller
77V500
IDT
3607 drw 15
System Clock Period in ns
Commercial & Industrial
SWITCHStAR and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
831-754-4613
Santa Clara, CA 95054
fax: 408-492-8674
SWITCHStARhelp@idt.com
www.idt.com
Preliminary Datasheet:
Definition
"PRELIMINARY" datasheets contain descriptions for products that are in early release.
Datasheet Document History
3/1/99:
Updated to new format.
Added Industrial Specifications.
Added S25 Speed Grade.
Pg. 3
Package Diagram noes added for clarification.
Pg. 4
Pin description table descriptions corrected. OFRM and Vss pin number corrections made.
Pg. 5
V
TERM
in Maximum ratings table reduced to 3.9V.
Pg. 10
Manager Bus Sequence Waveforms Figures 9 and 10 and their notes modified for clarity.
Pg. 14
Updated Ordering Information for S156 speed grade and Industrial temperature product. Added Preliminary
Datasheet definition and Datasheet Document History.
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