1
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 1999
1999 Integrated Device Technology, Inc.
DSC-5531/-
c
IDTQS34XST253
INDUSTRIAL TEMPERATURE RANGE
QUICKSWITCH
PRODUCTS
HIGH-SPEED CMOS
SYNCHROSWITCHTM 32:8 MUX/DEMUX
WITH ACTIVE TERMINATORS
DESCRIPTION:
The QS34XST253 is a high-speed CMOS 32:8 multiplexer/demultiplexer
with active terminators (bus-hold circuits) on the demux side. It is organized
as four independent dual 4:1 mux/demux blocks. Port selection and
connection, controlled by SEL signals, can be either asynchronous or
synchronous. In the synchronous mode, the A, B, C, or D port to Y port
connection is updated on the rising edge of the input clock CLK. Once the
port-to-port connection is made, data flow can be bi-directional with a typical
250ps propagation delay through the switch. Clock Enable, overriding
Asynchronous Enable, and Asynchronous Select controls provide addi-
tional design flexibility.
The bus-hold circuits latch the last data driven on the demux side,
providing infinite hold time and glitch-free signal transitions. Synchronous
controls and bus-hold ease timing constraints in many high speed data mux/
demux applications, such as bank interleaving. The QS34XST253 is
available in the space-saving, 80-pin dual-in-line MillipaQ package.
The QS34XST253 is characterized for operation at -40C to +85C.
Yn
0
Yn
1
An
0
Bn
0
Cn
0
An
1
Cn
1
Dn
0
Bn
1
Dn
1
T
T
T
T
T
T
T
T
T
=
R
CLKn
CLKENn
O En
0
SY NCn
O En
1
SE Ln
0
CO NTR OL
LO GIC
SE Ln
1
NOTE: One of four blocks shown.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
-
Enhanced N channel FET with no inherent diode to Vcc
-
Bidirectional signal flow
-
Flow-through pinout
-
Zero propagation delay, zero ground bounce
-
8 banks of 4:1 Mux/Demux
-
Port select synchronous to the clock
-
Clock enable and asynchronous enable
-
"Bus-hold" terminators on the Demux side
-
Undershoot clamp diodes on all switch and control pins
-
Asynchronous SEL option
-
Break-before-make feature
-
Available in 80-pin MillipaQ (Q3)
-
Bus-hold eliminates floating bus lines and reduces static power
consumption
APPLICATIONS
-
Video, audio, graphics switching, muxing
2
INDUSTRIAL TEMPERATURE RANGE
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
NC
A
00
A
01
B
00
B
01
GN D
NC
NC
GN D
NC
GN D
GN D
2
3
4
5
6
7
8
73
74
75
76
77
78
79
80
1
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
56
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
40
25
58
59
60
61
62
63
64
65
66
67
68
69
70
71
57
72
Vcc
CLKEN
0
CLK
0
SYNC
0
Vcc
CLKEN
1
CLK
1
SYNC
1
Vcc
CLKEN
2
CLK
2
SYNC
2
Vcc
OE
30
SEL
31
Y
30
Y
31
CLKEN
3
CLK
3
SYNC
3
C
00
C
01
D
00
D
01
A
10
A
11
B
10
B
11
C
10
C
11
D
10
D
11
A
20
A
21
B
20
B
21
C
20
C
21
D
20
D
21
A
30
A
31
B
30
B
31
C
30
C
31
D
30
D
31
SEL
30
OE
31
OE
20
SEL
21
Y
20
Y
21
SEL
20
OE
21
OE
10
SEL
11
Y
10
Y
11
SEL
10
OE
11
OE
00
SEL
01
Y
00
Y
01
SEL
00
OE
01
PIN CONFIGURATION
MILLIPAQ
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
Unit
V
TERM(2)
Supply Voltage to Ground
0.5 to +7
V
V
TERM(3)
DC Switch Voltage V
S
0.5 to +7
V
V
TERM(3)
DC Input Voltage V
IN
0.5 to +7
V
V
AC
AC Input Voltage (pulse width
20ns)
-3
V
I
OUT
DC Output Current
120
mA
P
MAX
Maximum Power Dissipation (T
A
= 85
C)
1.16
W
T
STG
Storage Temperature
65 to +150
C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz, V
IN
= 0V, V
OUT
= 0V)
Pins
Typ.
Max.
(1)
Unit
Control Inputs
4
5
pF
Quickswitch Channels
Demux
6
7
pF
(Switch OFF)
Mux
13
15
pF
NOTE:
1. This parameter is guaranteed at characterization but not production
tested.
PIN DESCRIPTION
Pin Names
I/O
Description
An
0
- Dn
0
I/O
Demux Ports
An
1
- Dn
1
I/O
Demux Ports
Yn
0
, Yn
1
I/O
Mux Ports
SELn
0,
SELn
1
I
Select Inputs
CLKn
I
Clock
CLKENn
I
Clock Enable
OEn
0,
OEn
1
I
Output Enable
SYNCn
I
Synchronous Selection Enable
3
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
2:1
M U X
SE Ln
0
CLKEN n
CLK n
SY N Cn
O E n
0
2:1
M U X
D
Q
To Bank n0 S w itches
To Ba nk n1 S w itches
2:1
M U X
SE Ln
1
2:1
M U X
D
Q
O E n
1
S
0
S
1
DE C O D E
LO G IC
AN D
SW ITC H
CO NT RO L
CONTROL LOGIC
(1)
NOTE:
1. One of four blocks.
FUNCTION TABLE
(1)
Control Inputs
MUX Ports
SYNCn
OEn
0
OEn
1
CLKn
CLKENn
SELn
0
SELn
1
Yn
0
Yn
1
L
L
L
L
L
L
An
0
An
1
L
L
L
L
H
L
Bn
0
Bn
1
L
L
L
L
L
H
Cn
0
Cn
1
L
L
L
L
H
H
Dn
0
Dn
1
L
H
H
L
X
X
Hold Previous Data
(2)
(Switch OFF)
Hold Previous Data
(2)
(Switch OFF)
L
L
L
H
X
X
Hold Previous Mux connection
(3)
(Switch ON)
Hold Previous Mux connection
(3)
(Switch ON)
L
H
H
H
X
X
Hold Previous Data
(4)
(Switch OFF)
Hold Previous Data
(4)
(Switch OFF)
H
L
L
X
X
L
L
An
0
An
1
H
L
L
X
X
H
L
Bn
0
Bn
1
H
L
L
X
X
L
H
Cn
0
Cn
1
H
L
L
X
X
H
H
Dn
0
Dn
1
H
H
H
X
X
X
X
Hold Previous Data (Switch OFF)
Hold Previous Data (Switch OFF)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
= Low-to-High Transition
2. Mux switches are turned off and the terminators (last value latches) hold the previous data state. The port connections can be changed by the SEL
input.
3. The contents of the "Mux select register" are unchanged and the previous Mux connection is unchanged. The output (Mux port) data state will
depend on the present data state of the input (Demux port).
4. The contents of the "Mux select register" are unchanged and the last value latch holds the previous data state.
4
INDUSTRIAL TEMPERATURE RANGE
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2
4
6
8
10
12
14
16
TYPICAL ON RESISTANCE vs V
IN
AT V
CC
= 5V
R
ON
(ohms)
V
IN
(Volts)
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40C to +85C, V
CC
= 5.0V 10%
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH for Control Pins
2
--
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW for Control Pins
--
--
0.8
V
I
IN
Input Leakage Current (Control Inputs)
0V
V
IN
Vcc
--
--
1
A
R
ON
Switch On Resistance
(2,3)
Vcc = Min., V
IN
= 0V
,
I
ON
= 30mA
--
7
9
Vcc = Min., V
IN
= 2.4V
,
I
ON
= 15mA
--
10
13
I
BHL
Input Hold Current
(4,5)
Vcc = 4.5V
V
IN
= 0.8V
60
--
--
A
I
BHH
(A, B, C, D)
Switch OFF
V
IN
= 2V
60
--
--
I
BH
Input Current
(7)
Vcc = Max.
V
IN
= 0V or Vcc
--
--
20
A
(A, B, C, D)
0.8 < V
IN
< 2V
--
--
500
(6)
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25C.
2. Measured by voltage drop between A/B and Y pin at indicated current through the switch.
3. R
ON
guaranteed but not production tested.
4. I
BHL
is the minimum sustaining "sink" current at the input for V
IN
= 0.8V. This parameter signifies the latching capability of the bus-hold circuit in
logic LOW state.
5. I
BHH
is the minimum sustaining "source" current at the input for V
IN
= 2V. This parameter signifies the latching capability of the bus-hold circuit in
logic HIGH state.
6. An external driver must provide at least I
BH
during transition to guarantee that the bus-hold input will change states.
7. I
BH
is the magnitude of the input current specified under two conditions:
a)
Input voltage at GND or Vcc. This indicates the input current under steady-state condition.
b)
Input voltage between 0.8V and 2V (TTL input threshold range). This indicates the maximum input current during transient condition. The
driver connected to the input must overcome this current requirement in order to switch the logic state of the bus-hold circuit.
5
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Max.
Unit
I
CCQ
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or Vcc, f = 0
12
A
I
CC
Power Supply Current per Control Input HIGH
(2)
V
CC
= Max., V
IN
= 3.4V, f = 0
1.5
mA
I
CCD
Dynamic Power Supply Current per MHz
(3)
V
CC
= Max., A/B/C/D and Y pins open
Control Input Toggling at 50% Duty Cycle
0.25
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven control input. (V
IN
= 3.4V, Control Pins only.) A/B/C/D and Y pins do not contribute to
Icc
.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The
A/B/C/D and Y inputs generate no significant AC or DC currents as they transition. This parameter is guaranteed but not production tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40C to +85C, V
CC
= 5.0V 10%
C
LOAD
= 50pF, R
LOAD
= 500
unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
PLH
t
PHL
Data Propagation Delay
(1,2)
A/B/C/D to Y, Y to A/B/C/D
--
0.25
--
ns
t
SEC
Clock Enable to Clock Setup Time
3
--
--
ns
t
HEC
Clock Enable to Clock Hold Time
0
--
--
ns
t
CSO
Clock to Switch Turn-On Delay
(3)
0.5
--
7
ns
t
ASO
Asynchronous Select to Switch Turn-On Delay
(3)
0.5
--
7
ns
t
W
Clock Pulse Width (High)
3
--
--
ns
t
SCS
SEL to Clock Setup Time
3
--
--
ns
t
HCS
SEL to Clock Hold Time
0
--
--
ns
t
PZL
t
PZH
Asynchronous Enable to Switch Turn-On Delay
(3)
1.5
--
5.2
ns
t
PLZ
t
PHZ
Asynchronous Enable to Switch Turn-Off Delay
(1,3)
1.5
--
4.8
ns
NOTES:
1. This parameter is guaranteed but not production tested.
2. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time
constant for the switch alone is of the order of 0.25ns for C
L
= 50pF. Since this time constant is much smaller than the rise and fall times of typical
driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch, when used in a system, is determined by the
driving circuit on the driving side of the switch and its interaction with the load on the driven side.
3. Minimums guaranteed but not production tested.
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INDUSTRIAL TEMPERATURE RANGE
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
TIMING WAVEFORMS - SYNCHRONOUS MODE, DEMUX FUNCTION
SY NC
CLK EN
CL K
SE L
O E
Port Y
Port A
Port D
HO LD PR EVIO US DAT A, DATA 1
HO LD PR EVIO US DAT A, DATA 2
DAT A 1
DAT A 2
IN V ALID D ATA
DAT A
1
DAT A 0
IN V ALID D ATA
t
SEC
t
H EC
t
SC S
t
H CS
t
SC S
t
H CS
t
PLH ,
t
PH L
t
C SO
t
PLH ,
t
PH L
t
C SO
DAT A 1
DAT A 2
DAT A 0
EXAMPLE: PORT Y TO PORT A/PORT D
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IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
TIMING WAVEFORMS - SYNCHRONOUS MODE, MUX FUNCTION
SY NC
CLKEN
CLK
SEL0, SE L1
Port A
Port B
Port Y
D AT A1
DAT A2
INVALID D ATA
DATA3
DAT A4
t
SE C
t
H EC
t
SC S
t
H CS
t
SC S
t
H CS
DAT A1
DAT A2
INV ALID D ATA
DAT A3
DAT A4
t
C SO
t
PLH ,
t
PH L
t
C SO
t
PLH ,
t
PH L
EXAMPLE: PORT A/PORT D TO PORT Y
8
INDUSTRIAL TEMPERATURE RANGE
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
TIMING WAVEFORMS - ASYNCHRONOUS MODE, MUX FUNCTION
SY NC
SEL
O E
Port A
Port D
Port Y
INV ALID
DATA
DATA1
DATA2
INV ALID D ATA
DATA3
INV ALID D ATA
DATA1
DATA2
DATA3
DATA3
t
PLH ,
t
PH L
t
PLH ,
t
PH L
t
AS O
t
PLZ,
t
PH Z
t
PZL,
t
PZH
EXAMPLE: PORT A/PORT D TO PORT Y
9
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
I
B H
+500
Sinking
C urrent
( + )
I
BHL
I
B H
I
BH H
+60
+20
60
20
+60 I
B HL
0.8V
2V
V
IH
60 I
B HL
V
IL
Sourcing
C urrent
( )
I
B H
500
Vcc
+20 I
BH
20 I
BH
Voltage
V
T
V-I CHARACTERISTICS OF BUS-HOLD CIRCUIT
V
T
Threshold Voltage
1.5V
V
IL
.8 V
IH
2V
ACTIVE TERMINATOR OR BUS-HOLD CIRCUIT
The Active Terminator circuit, also known as the bus-hold circuit, is configured as a "weak latch" with positive feedback. When connected to a
TTL or CMOS input port, the bus-hold circuit holds the last logic state at the input when the input is "disconnected" from the driver. When the output
of a device connected to such an input attempts a logic level transition, it will overdrive the bus-hold circuit. The primary benefit of a bus-hold circuit
is that it prevents CMOS inputs from floating, a situation which should be avoided to prevent spurious switching of inputs and unnecessary power
dissipation. Bus-hold is a better solution than the traditional approach of using resistive termination to Vcc or GND to prevent bus floating, because
the bus-hold circuit does not consume any static power.
This figure shows the input V-I characteristics of a typical bus-hold implementation. The input characteristics resemble a resistor. As the input
voltage is increased from 0 volts, the input "sink" current increases linearly. When the TTL threshold of the circuit is reached (typically 1.5 volts), the
latch changes the logic state due to positive feedback and the direction of the current is reversed. As the input voltage is further increased towards
Vcc, the input "source" current begins to decrease, reaching the lowest level at V
IN
= Vcc.
10
INDUSTRIAL TEMPERATURE RANGE
IDTQS34XST253
HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
ID T Q S
X X X X X
X X
P ackag e
D evice Type
B lan k
Ind ustrial (-40 C to +8 5C )
15 0 m il M illipa Q
Q 3
34 X S T 253
H ig h S pe e d C M O S S y nch ro S w itch 32 :8
M u x/D em ux w ith A ctive T e rm in ato rs
X
P ro cess
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