TECHNICAL DATA
401
8-Bit Bidirectional Universal
Shift Register with Parallel I/O
High-Speed Silicon-Gate CMOS
The IN74AC323 is identical in pinout to the LS/ALS323,
HC/HCT323. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
The IN74AC323 features a multiplexed parallel input/output data
port to achieve full 8-bit handling in a 20 pin package. Due to the large
output drive capability and the 3-state feature, this device is ideally
suited for interface with bus lines in a bus-oriented system.
Two Mode-Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table.
Synchronous parallel loading is accomplished by taking both Mode-
Select lines, S
1
and S
2
, high. This places the outputs in the high-
impedance state, which permits data applied to the data port to be
clocked into the register. Reading out of the register can be
accomplished when the outputs are enabled. The active-low
synchronous Reset overrides all other inputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A; 0.1
A @ 25
C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
IN74AC323
ORDERING INFORMATION
IN74AC323N Plastic
IN74AC323DW SOIC
T
A
= -40
to 85
C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
IN74AC323
402
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Sink/Source Current, per Pin
50
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
J
Junction Temperature (PDIP)
140
C
T
A
Operating Temperature, All Package Types
-40
+85
C
I
OH
Output Current - High
-24
mA
I
OL
Output Current - Low
24
mA
t
r
, t
f
Input Rise and Fall Time
*
(except Schmitt Inputs)
V
CC
=3.0 V
V
CC
=4.5 V
V
CC
=5.5 V
0
0
0
150
40
25
ns/V
*
V
IN
from 30% to 70% V
CC
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
IN74AC323
403
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limits
Symbol
Parameter
Test Conditions
V
25
C
-40
C to
85
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
3.0
4.5
5.5
2.1
3.15
3.85
2.1
3.15
3.85
V
V
IL
Maximum Low -
Level Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
3.0
4.5
5.5
0.9
1.35
1.65
0.9
1.35
1.65
V
V
OH
Minimum High-Level
Output Voltage
I
OUT
-50
A
3.0
4.5
5.5
2.9
4.4
5.4
2.9
4.4
5.4
V
*
V
IN
=V
IH
or V
IL
I
OH
=-12 mA
I
OH
=-24 mA
I
OH
=-24 mA
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
V
OL
Maximum Low-Level
Output Voltage
I
OUT
50
A
3.0
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
*
V
IN
= V
IH
or V
IL
I
OL
=12 mA
I
OL
=24 mA
I
OL
=24 mA
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
I
IN
Maximum Input
Leakage Current
V
IN
=V
CC
or GND
5.5
0.1
1.0
A
I
OZ
Maximum Three-
State Leakage
Current
V
IN
(OE)= V
IH
or V
IL
V
IN
=V
CC
or GND
V
OUT
=V
CC
or GND
5.5
0.6
6.0
A
I
OLD
+Minimum Dynamic
Output Current
V
OLD
=1.65 V Max
5.5
75
mA
I
OHD
+Minimum Dynamic
Output Current
V
OHD
=3.85 V Min
5.5
-75
mA
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
5.5
8.0
80
A
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
IN74AC323
404
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC
*
Guaranteed Limits
Symbol
Parameter
V
25
C
-40
C to
85
C
Unit
Min
Max
Min
Max
f
max
Maximum Clock Frequency (Figure 1)
3.3
5.0
90
130
80
105
MHz
t
PLH
Propagation Delay, Clock to Q
A
' or Q
H
'
(Figure 1)
3.3
5.0
8.5
5.5
20.5
14.0
7.0
4.5
22.0
15.0
ns
t
PHL
Propagation Delay, Clock to Q
A
' or Q
H
'
(Figure 1)
3.3
5.0
8.5
5.5
21.5
14.5
7.0
5.0
23.0
16.0
ns
t
PLH
Propagation Delay, Clock to Q
A
thru Q
H
(Figure 1)
3.3
5.0
9.0
6.0
20.5
14.5
7.5
5.0
22.5
16.0
ns
t
PHL
Propagation Delay, Clock to Q
A
thru Q
H
(Figure 1)
3.3
5.0
10.0
6.5
23.0
16.0
8.5
6.0
24.5
17.5
ns
t
PZH
Propagation Delay , OE1, OE2 to Q
A
thru Q
H
(Figure 3)
3.3
5.0
7.0
4.5
18.0
12.5
6.0
4.0
19.5
13.5
ns
t
PZL
Propagation Delay , OE1, OE2 to Q
A
thru Q
H
(Figure 3)
3.3
5.0
7.0
5.0
18.0
12.5
6.0
4.0
20.5
14.0
ns
t
PHZ
Propagation Delay , OE1, OE2 to Q
A
thru Q
H
(Figure 3)
3.3
5.0
6.5
3.5
18.5
14.0
5.5
3.0
19.5
15.0
ns
t
PLZ
Propagation Delay , OE1, OE2 to Q
A
thru Q
H
(Figure 3)
3.3
5.0
5.5
3.5
17.0
12.5
4.5
2.0
19.0
13.5
ns
C
IN
Maximum Input Capacitance
5.0
4.5
4.5
pF
Typical @25
C,V
CC
=5.0 V
C
PD
Power Dissipation Capacitance
170
pF
*
Voltage Range 3.3 V is 3.3 V
0.3 V
Voltage Range 5.0 V is 5.0 V
0.5 V
IN74AC323
405
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC
*
Guaranteed Limits
Symbol
Parameter
V
25
C
-40
C to
85
C
Unit
t
su
Minimum Setup Time, Mode Select S1 or S2
to Clock (Figure 4)
3.3
5.0
8.0
5.0
8.5
5.5
ns
t
su
Minimum Setup Time, Data Inputs P
A
thru P
H
to Clock (Figure 4)
3.3
5.0
5.5
3.5
6.0
4.0
ns
t
su
Minimum Setup Time, Data Inputs S
A
, S
H
to
Clock (Figure 4)
3.3
5.0
6.5
4.0
7.0
4.5
ns
t
su
Minimum Setup Time, Reset to Clock (Figure
2)
3.3
5.0
6.5
4.0
7.0
4.5
ns
t
h
Minimum Hold Time, Clock to Mode Select
S1 or S2 (Figure 4)
3.3
5.0
0.5
1.0
0.5
1.0
ns
t
h
Minimum Hold Time, Clock to Data Inputs P
A
thru P
H
(Figure 4)
3.3
5.0
0
1.0
0
1.0
ns
t
h
Minimum Hold Time, Clock to Data Inputs
S
A
, S
H
(Figure 4)
3.3
5.0
0
1.0
0.5
1.0
ns
t
h
Minimum Hold Time, Clock to Reset (Figure
2)
3.3
5.0
0
1.0
0
1.0
ns
t
w
Minimum Pulse Width, Clock (Figure 1)
3.3
5.0
4.5
3.5
5.0
3.5
ns
t
w
Minimum Pulse Width, Reset (Figure 2)
3.3
5.0
4.5
3.5
5.0
3.5
ns
*
Voltage Range 3.3 V is 3.3 V
0.3 V
Voltage Range 5.0 V is 5.0 V
0.5 V
IN74AC323
406
FUNCTION TABLE
Inputs
Response
Mode
Reset
Mode
Select
Output
Enables
Clock
Serial
Inputs
P
A
/
Q
A
P
B
/
Q
B
P
C
/
Q
C
P
D
/
Q
D
P
E
/
Q
E
P
F
/
Q
F
P
G
/
Q
G
P
H
/
Q
H
Q
A
' Q
H
'
S
2
S
1
OE1 OE2
D
A
D
H
Reset
L
X
L
L
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
L
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
Q
A
through Q
H
=Z
L
L
Shift
Right
H
L
H
H
X
D
X
Shift Right: Q
A
through Q
H
=Z;
D
A
F
A
; F
A
F
B
; etc
D
Q
G
H
L
H
X
H
D
X
Shift Right: Q
A
through Q
H
=Z;
D
A
F
A
; F
A
F
B
; etc
D
Q
G
H
L
H
L
L
D
X
Shift Right: D
A
F
A
=Q
A
;
F
A
F
B
=Q
B
; etc
D
Q
G
Shift
Left
H
H
L
H
X
X
D
Shift Left: Q
A
through Q
H
=Z;
D
H
F
H
; F
H
F
G
; etc
Q
B
D
H
H
L
X
H
X
D
Shift Left: Q
A
through Q
H
=Z;
D
H
F
H
; F
H
F
G
; etc
Q
B
D
H
H
L
L
L
X
D
Shift Left: D
H
F
H
=Q
H
;
F
H
F
G
=Q
G
; etc
Q
B
D
Parallel
Load
H
H
H
X
X
X
X
Parallel Load:P
N
F
N
P
A
P
H
Hold
H
L
L
H
X
X
X
X
Hold: Q
A
through Q
H
=Z; F
N
=F
N
P
A
P
H
H
L
L
X
H
X
X
X
Hold: Q
A
through Q
H
=Z; F
N
=F
N
P
A
P
H
H
L
L
L
L
X
X
X
Hold: Q
N
=Q
H
P
A
P
H
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the high-impedance
state; however, sequential operation or clearing of the register is not affected.
IN74AC323
407
Figure 1. Switching Waveform
Figure 2. Switching Waveform
Figure 3. Switching Waveform
Figure 4. Switching Waveform
IN74AC323
408
EXPANDED LOGIC DIAGRAM
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