47
IMP, Inc.
Process C1210
CMOS 1.2
m
Zero Threshold Devices
N-Channel Transistor
Symbol
Minimum
Typical
Maximum
Unit
Comments
Threshold Voltage
VT
N
0.55
0.75
0.95
V
100x1.2
m
Body Factor
N
0.34
V
1/2
100x1.2
m
Conduction Factor
N
64
75
86
A/V
2
100x100
m
Effective Channel Length
Leff
N
0.8
1.0
1.2
m
100x1.2
m
Width Encroachment
W
N
0.6
m
Per side
Punch Through Voltage
BVDSS
N
9
V
Poly Field Threshold Voltage
VTF
P(N)
10
V
P-Channel Transistor
Symbol
Minimum
Typical
Maximum
Unit
Comments
Threshold Voltage
VT
P
0.7
0.9
1.1
V
100x1.2
m
Body Factor
P
0.38
V
1/2
100x1.2
m
Conduction Factor
P
21
25
29
A/V
2
100x100
m
Effective Channel Length
Leff
P
0.9
1.1
1.3
m
100x1.2
m
Width Encroachment
W
P
0.8
m
Per side
Punch Through Voltage
BVDSS
P
9.0
V
Poly Field Threshold Voltage
VTF
P(P)
10.0
V
Zero Vt N-Channel Transis.
Symbol
Minimum
Typical
Maximum
Unit
Comments
Threshold Voltage
VT
ZLN
0.00
0.15
0.30
V
100x100
m
Body Factor
ZLN
0.348
V
1/2
100x100
m
Conduction Factor
ZLN
75
90
105
A/V
2
100x100
m
Saturation Current
I
DSATZN
28
34
40
mA 100x1.5
m
Zero Vt P-Channel Transis.
Symbol
Minimum
Typical
Maximum
Unit
Comments
Threshold Voltage
VT
ZLP
0.3
0.1
0.1
V
100x100
m
Body Factor
ZLP
0.36
V
1/2
100x100
m
Conduction Factor
ZLP
21
26
31
A/V
2
100x100
m
Saturation Current
I
DSATZP
11
15
19
mA 100x1.5
m
Electrical Characteristics
T=25
o
C Unless otherwise noted
ISO 9001 Registered
48
C1210-4-98
Process C1210
Diffusion & Thin Films
Symbol
Minimum
Typical
Maximum
Unit
Comments
Well (field) Sheet Resistance
N-well(f)
0.6
1.0
1.3
K
/
n-well
N+ Sheet Resistance
N+
20
35
50
/
N+ Junction Depth
x
jN+
0.35
m
P+ Sheet Resistance
P+
50
75
100
/
P+ Junction Depth
x
jP+
0.35
m
Gate Oxide Thickness
T
GOX
24 nm
Field Oxide Thickness
T
FIELD
800 nm
Gate Poly Sheet Resistance
POLY2
15
22
30
/
Bottom Poly Sheet Res.
POLY1
35
/
Metal-1 Sheet Resistance
M1
50
m
/
Metal-2 Sheet Resistance
M2
30
m
/
Passivation Thickness
T
PASS
200+900
nm
oxide+nit.
Capacitance
Symbol
Minimum
Typical
Maximum
Unit
Comments
Gate Oxide
C
OX
1.28
1.38
1.58
fF/
m
2
Metal-1 to Poly-1
C
M1P
0.057
fF/
m
2
Metal-1 to Silicon
C
M1S
fF/
m
2
Metal-2 to Metal-1
C
MM
0.035
fF/
m
2
Poly-1 to Poly-2
C
P1P2
0.69
0.86
1.03
fF/
m
2
Electrical Characteristics
49
IMP, Inc.
Process C1210
Starting Material
EPI P <100>
N+/P+ Width/Space
2.5/ 2.0
m
Starting Mat. Resistivity
7 - 8.5
-cm
N+ To P+ Space
9.0
m
Typ. Operating Voltage
5V
Contact To Poly Space
1.5
m
Well Type
N-well
Contact Overlap Of Diffusion
1.0
m
Metal Layers
2
Contact Overlap Of Poly
1.0
m
Poly Layers
2
Metal-1 Overlap Of Contact
1.0
m
Contact Size
1.5x1.5
m
Metal-1 Overlap Of Via
1.0
m
Via Size
1.5x1.5
m
Metal-2 Overlap Of Via
1.0
m
Metal-1 Width/Space
2.5 / 1.5
m
Minimum Pad Opening
65x65
m
Metal-2 Width/Space
2.5 / 1.5
m
Minimum Pad-to-Pad Spacing
5.0
m
Gate Poly Width/Space
1.5 / 2.0
m
Minimum Pad Pitch
80.0
m
Special Feature of C1210 Process: This process offers zero threshold n- and p-channel
transistors in addition to normal threshold transistors of CMOS 1.2
m technology.
Physical Characteristics
Metal 2
Metal 1
SIO
2
VIA
Metal 1
LTO
n
+
n
+
p
n
+
p
+
p
Field Oxide
N-well contact
Source
Poly gate
N-well
Drain
Contact
Drain
LDD
Poly gate
Sidewall spacer
Source
p
substrate contact
Channel stop
Sidewall spacer
Bottom poly
Contact
Poly gate
p
+
substrate
p
epi
p
+
p
+
LTO
5.5
VGS = 4.0V
VGS = 3.0V
VGS = 2.0V
VGS = 1.0V
VGS = 0V
ID vs VD, W/L = 20/1.2
.00
0
1
2
3
4
5
Drain Current
ID (mA)
0.55 mA
/div
Drain Voltage (v) VDS
n-ch Transistor IV characteristics of a 20/1.2 device
-3.0
VGS = 5.0V
VGS = 4.0V
VGS = 3.0V
VGS = 2.0V
VGS = 1.0V
VGS = 0.0V
ID vs VD, W/L = 20/1.2
.00
0
1
2
3
4
5
Drain Current
ID (mA)
0.3 mA
/div
Drain Voltage (v) VDS
p-ch Transistor IV characteristics of a 20/1.2 device
Cross-Sectional view of the LVMOS process
PDF 
ZIP