1
IMP8980D
PCM Digital Switch
Figure 1 Functional Block Diagram
General Description
This CMOS device is designed for
switching PCM-encoded voice or data,
under microprocessor control, in a modern
digital exchange, PBX or Central Office. It
provides simultaneous connections for up
to 256 64kbit/s channels. Each of the eight
serial inputs and outputs consist of 32
64kbit/s channels multiplexed to form a
2048kbit/s ST-BUS stream. In addition,
the IMP8980D provides microprocessor
read and write access to individual
ST-BUS (Serial Telecom Bus) channels.
Features
ST-BUS compatible
8-line x 32-channel inputs
8-line x 32-channel outputs
256 ports non-blocking switch
Single power supply (+5V)
30mW power consumption
Microprocessor-control interface
Pin-compatible with Mitel MT8980
Functional Description
The ST-BUS architecture can be used
both in software-controlled digital voice
and data switching.
The ST-Bus serial streams operate
continuously at 2048kbit/s and are
arranged in 125
s wide frames which
contain 32 8-bit channels.
The IMP8980D can switch data from
channels on ST-BUS inputs to channels on
ST-BUS outputs and simultaneously
allows its controlling microprocessor to
read channels on ST-BUS inputs or write
to channels on ST-BUS outputs (Message
Mode). To the microprocessor, the
IMP8980D looks like a memory periph-
eral. The microprocessor can write to the
IMP8980D to establish switched connec-
tions between input ST-BUS channels and
output ST-BUS channels or to transmit
messages on output ST-BUS channels. By
reading from the IMP8980D, the micro-
processor can receive messages from
ST-BUS input channels or check which
Serial
to
Parallel
Converter
Frame
Counter
Control Register
Control Interface
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
DS
CS
R/W
A5/
A0
DTA
D7/
D0
CSTo
C4i
F0i
V
DD
V
SS
Data
Memory
ISO 9001 Registered
IMP, Inc.
IMP8980D DS-5-00
2
handles the microprocessor control signals
CS, DTA, R/W and DS. There are two
parts to any address in the Data Memory
or Connection 2-7 Memory. The higher
order bits come from the Control Register,
which may be written to or read from via
the Control Interface. The lower order bits
come from the address lines directly.
The Control Register also allows the
chip to broadcast messages on all ST-BUS
outputs (i.e., to put every channel into
Message Mode), or to split the memory so
that reads are from the Data Memory and
writes are to the Connection Memory Low.
The Connection Memory High determines
whether individual output channels are in
Message Mode, and allows individual
output channels to go into a high-
impedance state, which enables arrays of
IMP8980D s to be constructed. It also
controls the CSTo pin.
All ST-BUS timing is derived from the
C4i and F0i signals.
Software Control
The address lines on the Control
Interface give access to the Control
Register directly or, depending on the
contents of the Control Register, to the
High or Low sections of the Connection
Memory or to the Data Memory.If address
line A5 is low, then the Control Register is
addressed regardless of the other address
lines (see Figure 3). If A5 is high, then the
address lines A4-A0 select the memory
location corresponding to channel 0-31 for
the memory and stream selected in the
Control Register.
The data in the Control Register
consists of mode control bits, memory
select bits, and stream address bits (see
Figure 4). The memory select bits allow the
Connection Memory High or Low or the
Data Memory to be chosen, and the
stream address bits define one of the
ST-BUS input or output streams.
Bit 7 of the Control Register allows split
memory operation - reads are from the
Data Memory and writes are to the
Connection Memory Low.
The other mode control bit, bit 6, puts
every output channel on every output
switched connections have already been
established.
By integrating both switching and
interprocessor communications, the
IMP8980D allows systems to use distrib-
uted processing and to switch voice or data
in an ST-BUS architecture.
Hardware Description
Serial data at 2048 kbit/s is received at
the eight ST-BUS inputs (STi0 to STi7),
and serial data is transmitted at the eight
ST-BUS outputs (STo0 to STo7). Each
serial input accepts 32 channels of digital
data, each channel containing an 8-bit
word which may represent a PCM-encoded
analog/voice sample as provided by a
codec.
This serial input word is converted into
parallel data and stored in the 256 X 8
Data Memory. Locations in the Data
Memory are associated with particular
channels on particular ST-BUS input
streams. These locations can be read by the
microprocessor which controls the chip.
Locations in the Connection Memory,
which is split into high and low parts, are
associated with particular ST-BUS output
streams. When a channel is due to be
transmitted on an ST-BUS output, the
data for the channel can either be switched
from an ST-BUS input or it can originate
from the microprocessor. If the data is
switched from an input, then the contents
of the Connection Memory Low location
associated with the output channel is used
to address the Data Memory. This Data
Memory address corresponds to the
channel on the input ST-BUS stream on
which the data for switching arrived. If the
data for the output channel originates
from the microprocessor (Message Mode),
then the contents of the Connection
Memory Low location associated with the
output channel are output directly, and
this data is output repetitively on the
channel once every frame until the
microprocessor intervenes.
The Connection Memory data is
received, via the Control Interface, at D7
to D0. The Control Interface also receives
address information at A5 to A0 and
3
stream into active Message Mode; i.e., the
contents of the Connection Memory Low
are output on the ST-BUS output streams
once every frame unless the ODE pin is
low. In this mode the chip behaves as if
bits 2 and 0 of every Connection Memory
High location were 1, regardless of the
actual values.
If bit 6 of the Control Register is 0, then
bits 2 and 0 of each Connection Memory
Figure 3- Address Memory Map
A5
A4
A3
A2
A1
A0
HEX ADDRESS
LOCATION
0
X
X
X
X
X
00-1F
Control Register*
1
0
0
0
0
0
20
Channel 0
1
0
0
0
0
1
21
Channel 1
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
1
1
1
1
1
1
3F
Channel 31
* Writing to the Control Register is the only fast transaction.
Memory and stream are specified by the contents of the Control Register.
High location function normally (see
Figure 5). If bit 2 is 1, the associated ST-
BUS output channel is in Message Mode;
i.e., the byte in the corresponding Connec-
tion Memory Low location is transmitted
on the stream at that channel. Otherwise,
one of the bytes received on the serial
inputs is transmitted and the contents of
the Connection Memory Low define the
ST-BUS input stream and channel where
the byte is to be found (see Figure 6).
Figure 4 - Control Register Bits
7
6
5
4
3
2
1
0
}
}
}
Mode
Control
Bits
(Unused)
Memory
Select
Bits
Stream
Address
Bits
BIT
NAME
DESCRIPTION
7
Split
When 1, all subsequent reads are from the Data Memory
Memory
and writes are to the Connection Memory Low, except when
the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In
either case, the Stream Address Bits select the subsection of
the memory which is made available.
6
Message
When 1, the contents of the Connection Memory Low are output
Mode
on the Serial Output streams except when the ODE pin is low.
When 0, the Connection Memory bits for each channel determine
what is output.
5
(unused)
4-3
Memory
0-0 - Not to be used
Select Bits
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
2-0
Stream
The number expressed in binary notation on these bits refers to
Address
the input or output ST-BUS stream which corresponds to the
Bits
subsection of memory made accessible for subsequent operations.
IMP, Inc.
IMP8980D DS-5-00
4
Figure5 - Connection Memory High Bits
7
6
5
4
3
2
1
0
}
}
No Corresponding Memory
- These bits give 0s if read.
Per Channel
Control Bits
BIT
NAME
DESCRIPTION
2
Message
When 1, the contents of the corresponding location in Connection
Channel
Memory Low are output on the location's channel and stream.
When 0, the contents of the corresponding location in Connection
Memory Low act as an address for the Data Memory and so
determine the source of the connection to the location's channel
and stream.
1
CSTo
This bit is output on the CSTo pin one channel early. The CSTo bit
for stream 0 is output first.
0
Output
If the ODE pin is high and bit 6 of the Control Register is 0, then
Enable
this bit enables the output driver for the location's channel and
stream. This allows individual channels on individual streams to
be made high-impedance, allowing switching matrices to be
constructed. A "1" enables the driver and a "0" disables it.
If the ODE pin is low, then all serial
outputs are high-impedance. If it is high
and bit 6 in the Control Register is 1, then
all outputs are active. If the ODE pin is
high and bit 6 in the Control Register is 0,
then the bit 0 in the Connection Memory
High location enables the output drivers
for the corresponding individual ST-BUS
output stream and channel. Bit 0=1
enables the driver and bit 0=0 disables it
(see Figure 5).
Bit 1 of each Connection Memory High
location (see Figure 5) is output on the
CSTo pin once every frame. To allow for
delay in any external control circuitry the
bit is output one channel before the
corresponding channel on the ST-BUS
streams, and the bit for stream 0 is output
first in the channel; e.g., bit 1's for
channel 9 of streams 0-7 are output
synchronously with ST-BUS channel 8
bits 7-0.
Applications
Digital Switching Systems
Figures 7 and 8 show how IMP8980Ds
and MT8964s form a simple digital
switching system. Figure 7 shows the
interface between the IMP8980D's and the
filter/codecs. Figure 8 shows the position of
these components in an example architec-
ture.
The Mitel MT8964 filter/codec in
Figure 7 receives and transmits digitized
voice signals on the ST-BUS input DR,
and ST-BUS output DX, respectively.
These signals are routed to the ST-BUS
inputs and outputs on the top IMP8980D,
which is used as a digital speech switch.
The MT8964 is controlled by the
ST-BUS input DC originating from the
bottom IMP8980D , which generates the
appropriate signals from an output channel
in Message Mode. This architecture
optimizes the messaging capability of the
line circuit by building signalling logic, e.g.,
for on-off hook detection, which commu-
nicates on an ST-BUS output. This
signalling ST-BUS output is monitored by
a microprocessor (not shown) through an
ST-BUS input on the bottom IMP8980D.
Figure 8 shows how a simple digital
switching system may be designed using the
ST-BUS architecture. This is a private
telephone network with 256 extensions
which uses a single IMP8980D as a speech
5
Figure 6 - Connection Memory Low Bits
switch and a second IMP8980D for
communication with the line interface
circuits.
A larger digital switching system may be
designed by cascading a number of
IMP8980Ds. Figure 9 shows four
IMP8980Ds arranged in a non-blocking
configuration which can switch any
channel on any of the ST-BUS inputs to
any channel on the ST-BUS outputs.
Application Circuit with 6802
Processor
Figure 10 shows an example of a
complete circuit which may be used to
evaluate the chip.
For convenience, a 4MHz crystal
oscillator has been used rather than a
4.096MHz clock, as both are within the
limits of the chip's specifications. The RC
delay used with the 393 counters ensures a
sufficient hold time for the FP signal, but
the values used may have to be changed if
faster 393 counters become available.The
chip is shown as memory mapped into the
MEK6802D3 system. Chip addresses
00-3F correspond to processor addresses
2000-203F. Delay through the address
decoder requires the VMA signal to be
used twice to remove glitches. The
MEK6802D3 board uses a 10K
pullup
on the MR pin, which would have to be
incorporated into the circuit if the board
was replaced by a processor.
7
6
5
4
3
2
1
0
}
}
Channel
Address
Bits
Stream
Address
Bits
BIT
NAME
DESCRIPTION
7-5*
Stream *
The number expressed in binary notation on these 3 bits is
Address
the number of the ST-BUS stream for the source of the connection.
Bits
Bit 7 is the most significant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5
is 0, then the source of the connection is a channel on STi4.
4-0*
Channel
The number expressed in binary notation on these 5 bits is
Address
the number of the channel which is the source of the connection
Bits*
(The ST-BUS stream where the channel lies is defined by bits 7,
6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is
0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the
connection is channel 19.
* If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1,
then the entire 8 bits are output on the channel and stream associated with this location.
Otherwise, the bits are used as indicated to define the source of the connection which is
output on the channel and stream associated with this location.
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