REVIEW
DOCUMENT
- SEAGATE -
D A T A B O O K
Version 1.00
June 2003
INIC-2430
FireWire 800 to
ATA Bridge IC
INIC-2430 Features
Copyright
Copyright 2003 Initio Corporation. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any
form or by any, electronic, mechanical, photocopying, recording without the express written consent and authorization of Initio Corporation, 650 North
Mary Ave., Sunnyvale, CA 94085
Trademarks
Initio, Inic-, are registered trademarks of Initio Corporation.
Change
Initio Corporation reserves the right to make changes in the product design without reservation and without notification to its users. The Material in this
publication is for information only and is subject to change without notice.
IEEE Std 1394-1995 and 1394b Compliant
Support industry standard FireWire 800 PHY
Support Asynchronous Transfers at 100, 200, 400 and 800
Mbits/s
Perform 1394b
Cycle Master
Implements SBP3/SBP2 stack to optimize the performance
SBP-3 faststart support
Shadow RAM for fast code fetch
Programmable wait state for CPU to access registers, external SRAM, and Flash
ATA/ATAPI-7 d1532r2, vol. 1 & 2 compliant
Support ATA DMA modes 0-2, and UDMA 133/100/66/33
(Note that mode 6, 133 MBytes/s, is only supported when running 1394b mode)
Support ATA PIO mode 0-4
Integrated internal ARM7TDMI 32-bit CPU with embedded SRAM
Implement the firmware download mechanism
Power Management
Low power CMOS operating at 3.3 and 2.5 Volts
144-pin LQFP or 144-pin TFBGA packages available
Dual ATA Channels
100 MBytes/s raw data rate read and write
6 GPIO pins available with TFBGA package version
4K payload size
Supports up to 32 MB of external SRAM and 32 MB of Flash memory
16 KB of internal SRAM
INIC-2430 Data Sheet
Confidential
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Table of Contents
SECTION 1 - Overview ..............................................................................................................................................1
1.1
Introduction ..................................................................................................................................................1
1.1.1 Feature Summary ..............................................................................................................................1
1.1.2 Firmware/Software Support ..............................................................................................................1
1.1.3 Devices Support ................................................................................................................................2
1.1.4 Reference Documents .......................................................................................................................2
SECTION 2 - Pin Definitions .....................................................................................................................................3
2.1
LINK-PHY Interface Pins ...........................................................................................................................5
2.2
ATA Interface Pins ......................................................................................................................................6
2.3
MVRAM / GPIO Interface Pins ..................................................................................................................7
2.4
Local Microprocessor Interface Pins ...........................................................................................................8
2.5
System Interface Pins ...................................................................................................................................9
2.6
Power and Ground Pins ...............................................................................................................................9
SECTION 3 - Address Mapping Summary ............................................................................................................11
3.1
Address Mapping .......................................................................................................................................11
3.1.1 Firmware Shadow Procedure ..........................................................................................................12
3.2
Registers .....................................................................................................................................................13
3.2.1 Link Block .......................................................................................................................................13
3.2.2 ATA Block ......................................................................................................................................14
3.2.3 Data Port to WR/RD S/G FIFOs .....................................................................................................14
3.2.4 Bridge General Registers ................................................................................................................14
3.3
Buffers .......................................................................................................................................................17
3.3.1 CMD/DATA Block .........................................................................................................................17
3.3.1.1 Asynchronous Receive Packet Formats ........................................................................18
3.3.1.2 Asynchronous Transmit Packet Formats ......................................................................21
3.3.1.3 PHY Receive Packet Format .........................................................................................24
3.3.1.4 Synthesized Bus Reset Packet Format ..........................................................................25
3.3.2 S/G DMA Block ..............................................................................................................................26
3.3.2.1 SgList Header Format ...................................................................................................26
3.4
Memories ...................................................................................................................................................28
3.4.1 External Flash Memory ...................................................................................................................28
3.4.2 Internal Memory Block ...................................................................................................................28
3.4.3 External Memory Block ..................................................................................................................28
INIC-2430 Data Sheet
Confidential
ii
Confidential
INIC-2430 Data Sheet
Table of Contents
SECTION 4 - Register Descriptions ....................................................................................................................... 29
4.1
Register Descriptions ................................................................................................................................ 29
4.1.1 Link Block Registers ...................................................................................................................... 29
4.1.2 ATA Block Registers ..................................................................................................................... 38
4.1.3 Data Port to WR/RD S/G FIFOs .................................................................................................... 40
4.1.4 Bridge General Registers ................................................................................................................ 41
SECTION 5 - Electrical Specifications ................................................................................................................... 63
5.1
Absolute Maximum Ratings ...................................................................................................................... 63
5.2
Recommended Operating Conditions ....................................................................................................... 63
5.3
General DC Characteristics ....................................................................................................................... 64
5.4
DC Electrical Characteristics for Normal Operation ................................................................................ 64
SECTION 6 - Timing Specifications ....................................................................................................................... 65
6.1
1394 Link to PHY Interface ...................................................................................................................... 65
6.2
Flash / Memory Interface .......................................................................................................................... 66
6.2.1 Flash Memory Read Cycle ............................................................................................................. 66
6.2.2 Flash Memory Write Cycle ............................................................................................................ 67
6.2.3 External SRAM Read Cycle ........................................................................................................... 68
6.2.4 External SRAM Write Cycle .......................................................................................................... 69
SECTION 7 - Packaging Specifications ................................................................................................................. 71
7.1
INIC-2430 LQFP Packaging Specifications ............................................................................................. 71
7.2
INIC-2430 TFBGA Packaging Specifications .......................................................................................... 73
INIC-2430 Data Sheet
Confidential
1
SECTION 1
Overview
1.1 Introduction
The INIC-2430 provides an advanced solution to connect ATAPI or ATA (IDE/EIDE) devices to
an IEEE-1394b interface with an integrated 32-bit CPU and embedded SRAM. To provide high
performance and a cost effective solution, the INIC-2430 integrates a 1394b link core, ATA con-
trol block and microprocessor into a single ASIC. The INIC-2430 delivers a data transfer rate of
up to 800 Mbits/sec on FireWire 800 (1394) interface (100 MBytes/sec), while its ATA interface
supports ultra DMA modes (33/66/100/133 MBytes/sec).
1.1.1 Feature Summary
IEEE Std 1394-1995 and 1394b Compliant
Support industry standard FireWire 800 PHY
Support Asynchronous Transfers at 100, 200, 400 and 800
Mbits/s
Perform 1394b
Cycle Master
Implements SBP3/SBP2 stack to optimize the performance
SBP3/SBP2 faststart support
Shadow RAM for fast code fetch
Programmable wait state for CPU to access registers, external SRAM, and Flash
ATA/ATAPI-7 d1532r2, vol. 1 & 2 compliant
Support ATA DMA modes 0-2, and UDMA 133/100/66/33
(Note that mode 6, 133 MBytes/s, is only supported when running 1394b mode)
Support ATA PIO mode 0-4
Integrated internal ARM7TDMI 32-bit CPU with embedded SRAM
Implement the firmware download mechanism
Power Management
Low power CMOS operating at 3.3 and 2.5 Volts
144-pin LQFP or 144-pin TFBGA packages available
Dual ATA Channels
100 MBytes/s raw data rate read and write
6 GPIO pins available with TFBGA package version
4K payload size
Supports up to 32 MB of external SRAM and 32 MB of Flash memory
16 KB of internal SRAM
1.1.2 Firmware/Software Support
Protocols supported include SBP-2, SBP-3, RBC and ATA/ATAPI -7
Software utilities for downloading the upgraded firmware code
INIC-2430 Data Sheet
PDF 
ZIP