INIC-525 Preliminary Data Sheet

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Table of Contents

SECTION 1 - Overview ..............................................................................................................................................1

1.1

Introduction ................................................................................................................................................1
1.1.1

Feature Summary .........................................................................................................................1

1.1.2

Functional Description .................................................................................................................2

1.1.3

Reference Documents ..................................................................................................................2

SECTION 2 - Pin Definitions .....................................................................................................................................3

2.1

SCSI Interface Pins ....................................................................................................................................4

2.2

Miscellaneous Interface Pins ......................................................................................................................7

2.3

Power and Ground Pins ..............................................................................................................................8

SECTION 3 - Functional Description .......................................................................................................................9

3.1

INIC-525 Pin Functional Descriptions .......................................................................................................9

3.2

INIC-525 Functional Diagram .................................................................................................................10

SECTION 4 - Electrical Specifications ...................................................................................................................11

4.1

Absolute Maximum Ratings .....................................................................................................................11

4.2

Recommended Operating Conditions ......................................................................................................11

4.2.1

SCSI Single Ended (SE) Recommended Operating Conditions ................................................11

4.2.2

SCSI Low Voltage Differential (LVD) Recommended Operating Conditions .........................12

4.2.3

SCSI DIFFSENS Receiver Recommended Operating Conditions ............................................12

SECTION 5 - Timing Specifications .......................................................................................................................13

5.1

General Timing ........................................................................................................................................13

5.1.1

AC Input/Output Timing Parameters .........................................................................................13

5.1.2

Clock Timing Parameters ...........................................................................................................14

5.2

SCSI Signal Interface Parameters ............................................................................................................15
5.2.1

SCSI Interface Timing Parameters ............................................................................................15

SECTION 6 - Packaging Specifications ..................................................................................................................17

6.1

INIC-525 PQFP Packaging Specifications ..............................................................................................17

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INIC-525 Preliminary Data Sheet

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SECTION 1

Overview

1.1 Introduction

The INIC-525 chip is a SCSI bus expander/converter. As a converter, it allows Single-Ended (SE)
SCSI devices to be attached to a Low Voltage Differential (LVD) or a High Voltage Differential
(HVD) SCSI bus. It can also be used as a bus expander to extend SE, LVD, or HVD cables. It
optimizes SCSI bus timing for improved SCSI performance without any impact to the SCSI proto-
col.

1.1.1 Feature Summary

w Operates both as a SCSI bus converter or expander

· As a converter or expander, allows SE, LVD, HVD

SE, LVD, HVD connections

w SCSI bus electrical isolation for clustering environments

w Target/Initiator independent

w No SCSI ID is used

w No software overhead

w Supports Double Transition Clocking

w Supports Quick Arbitrate and Selection

w Up to 3 devices may be cascaded

w Supports asynchronous/synchronous transfer speeds up to Ultra-3 SCSI (Fast-80)

for LVD

LVD (expander mode) or Ultra SCSI (Fast-20) for SE devices (converter mode).

w Dynamically tunes itself to process, voltage & temperature

w Wired-OR glitches are blocked from A side to B side or vice versa

w BSY LED bus activity indicator

w SCSI-1, SCSI-2, SCSI-3 & EPI Compliant

w Package type

· 160pin PQFP
· Fully pin compatible with LSI SYM53C140

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INIC-525 Preliminary Data Sheet

Overview

Section 1

Figure 1-1 INIC-525 Block Diagram

1.1.2 Functional Description

Delay/Process Control Module
The process control module tunes itself dynamically to the device process, voltage and tempera-
ture. This tuning is used to adjust timing circuits to re-time the SCSI signals to achieve optimal
setup/hold times. It is also used to ensure a minimum pulse width in some cases as will be noted in
a later section.

Re-timing Module
This module is tightly coupled to the process control module. In its basic sense, the design simply
selects which logical path the signal is to take. At the appropriate time, select whether to pass the
signal through; de-assert it; or keep it asserted. Each signal path has its only retiming selection
paths.

1.1.3 Reference Documents

SCSI Parallel Interface-3 (SPI-3) Specification, American National Standards Institute (ANSI)
Document Number ANSI T10/1302D revision 8.

SCSI Enhanced Parallel Interface (EPI).

SCSI Bus

side A

SCSI Bus

side B

Re-timing circuit

LVD/SE

I/O

module

LVD/SE

I/O

module

Delay/Process

Control

State Machine

Control

Signals

INIC-525 Preliminary Data Sheet

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SECTION 2

Pin Definitions

Figure 2-1 shows the pinout of the INIC-525.

Figure 2-1 INIC-525 PQFP Pin Assignments

VSS_

SCS

BSD6

BSD5

BSD4

VSS_

SCSI

BSD3

SCSI

BSD2

BSD1

VSS_

SCSI

BSD0

BSDP

BSD1

VSS_

SCSI

BSD1

SCSI

BSD1

VSS_

SCSI

VSS_

SCSI

ASD1

SCSI

ASD1

ASD9

VSS_

SCSI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

BSD11+

BSD11-

BSD10+

BSD10-

BSD9+

BSD9-

VSS_SCSI

BSD8+

BSD8-

VDD_SCSI

BSIO+

BSIO-

BSREQ+

BSREQ-

VSS_SCSI

BSCD+

BSCD-

BSSEL+

BSSEL-

BSMSG+

BSMSG-

VSS_SCSI

VSS_CORE

BSRST+

BSRST-

VDD_CORE

VDD_SCSI

BSACK+

BSACK-

BSBSY+

BSBSY-

VSS_SCSI

BSATN+

BSATN-

BSDP0+

BSDP0-

VDD_SCSI

RBIAS

BSD7+

BSD7-

INIC-525

160-PIN PQFP

TOP VIEW

120

119
118
117
116
115
114
113
112

111

110

109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

VSS_SCSI
ASD4-
ASD4+
ASD5-
ASD5+
ASD6-
ASD6+
VDD_SCSI
ASD7-
ASD7+
VSS_SCSI
ASDP0-
ASDP0+
ASATN-
ASATN+
ASBSY-
ASBSY+
VSS_CORE
VSS_SCSI
ASACK-
ASACK+
VDD_SCSI
VDD_CORE
ASRST-
ASRST+
VSS_SCSI
ASMSG-
ASMSG+
ASSEL-
ASSEL+
ASCD-
ASCD+
VSS_SCSI
ASREQ-
ASREQ+
ASIO-
ASIO+
ASD8-
ASD8+
VDD_SCSI

SS_

SCSI

I
F

I
/
O

HVD_

NAB

I
V

SY_

OCK

SET/

HVD_

SS_

I
/
O

I
F

SS_

SCSI

SS_

SCSI

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INIC-525 Preliminary Data Sheet

Pin Definitions

Section 2

2.1 SCSI Interface Pins

Table 2-1 SCSI Interface Pins

SYMBOL

PIN #

TYPE

DESCRIPTION

A_SD[15:0]+/-

134, 135, 137-

142, 73, 74, 76-

79, 82, 83, 111,

112, 114-119,
122-127, 129,

130

I/O

DIFFERENTIAL +/- PORT A SCSI DATA: 16-bit SCSI Data
bus.

A_SDP[1:0] +/-

131, 132, 108,

109

I/O

DIFFERENTIAL +/- PORT A SCSI DATA PARITY:
A_SDP[0] corresponds to A_SD[7:0]; while A_SDP[1] to
A_SD[15:8].

A_SCD+/-

89, 90

I/O

DIFFERENTIAL +/- PORT A SCSI COMMAND/DATA SIG-
NAL: When asserted, it indicates a command phase, otherwise
it indicates a data phase.

A_SIO+/-

84, 85

I/O

DIFFERENTIAL +/- PORT A SCSI INPUT/OUTPUT SIG-
NAL: When asserted, it indicates an output phase, otherwise it
indicates an input phase, referenced to the initiator.

A_SMSG+/-

93, 94

I/O

DIFFERENTIAL +/- PORT A SCSI MESSAGE SIGNAL:
When asserted, it indicates a message phase.

A_SREQ+/-

86, 87

I/O

DIFFERENTIAL +/- PORT A SCSI REQUEST SIGNAL:
When asserted, it indicates a request for information transfer
on the data bus.

A_SACK+/-

100, 101

I/O

DIFFERENTIAL +/- PORT A SCSI ACKNOWLEDGE SIG-
NAL: When asserted, it indicates an acknowledgement of an
information transfer on the data bus.

A_SBSY+/-

104, 105

I/O

DIFFERENTIAL +/- PORT A SCSI BUSY SIGNAL: When
asserted, it indicates that the bus is in use.

A_SATN+/-

106, 107

I/O

DIFFERENTIAL +/- PORT A SCSI ATTENTION SIGNAL:
When asserted by an initiator, it indicates an ATTENTION
condition.

A_SSEL+/-

91, 92

I/O

DIFFERENTIAL +/- PORT A SCSI SELECT SIGNAL: When
asserted, it indicates an initiator trying to select a target or a
target trying to re-select an initiator.

Section 2

Pin Definitions

INIC-525 Preliminary Data Sheet

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A_SRST+/-

96, 97

I/O

DIFFERENTIAL +/- PORT A SCSI BUS RESET: When
asserted, it indicates a SCSI RESET condition.

A_DIFF_SENSE

143

PORT A DIFFERENTIAL SENSING: This pin senses if the
SCSI bus connection on port A is SE or LVD and should be
connected to the SCSI bus DIFFSENS signal.

A_HVD_MODE

145

PORT A HIGH VOLTAGE DIFFERENTIAL CONTROL:
When this pin is set and A_DIFF_SENSE detects the proper
voltage level, all of the minus signal lines on port A become
S/E mode and all of the plus signal lines become control sig-
nals to external HVD transceivers.

B_DIFF_SENSE

159

PORT B DIFFERENTIAL SENSING: This pin senses if the
SCSI bus connection on port B is SE or LVD and should be
connected to the SCSI bus DIFFSENS signal.

B_HVD_MODE

157

PORT B HIGH VOLTAGE DIFFERENTIAL CONTROL:
When this pin is set and B_DIFF_SENSE detects the proper
voltage level, all of the minus signal lines on port B become
S/E mode and all of the plus signal lines become control sig-
nals to external HVD transceivers.

B_SD[15:0]+/-

61, 62, 64, 65,

67-70, 1-6, 8, 9,

39, 40, 42-47,
49, 50, 52-55,

57, 58

I/O

DIFFERENTIAL +/- PORT B SCSI DATA: 16-bit SCSI Data
bus.

B_SDP[1:0] +/-

59, 60, 35, 36

I/O

DIFFERENTIAL +/- PORT B SCSI DATA PARITY:
B_SDP[0] corresponds to B_SD[7:0]; while B_SDP[1] to
B_SD[15:8].

B_SCD+/-

16, 17

I/O

DIFFERENTIAL +/- PORT B SCSI COMMAND/DATA SIG-
NAL: When asserted, it indicates a command phase, otherwise
it indicates a data phase.

B_SIO+/-

11, 12

I/O

DIFFERENTIAL +/- PORT B SCSI INPUT/OUTPUT SIG-
NAL: When asserted, it indicates an output phase, otherwise it
indicates an input phase, referenced to the initiator.

B_SMSG+/-

20, 21

I/O

DIFFERENTIAL +/- PORT B SCSI MESSAGE SIGNAL:
When asserted, it indicates a message phase.

B_SREQ+/-

13, 14

I/O

DIFFERENTIAL +/- PORT B SCSI REQUEST SIGNAL:
When asserted, it indicates a request for information transfer
on the data bus.

Table 2-1 SCSI Interface Pins (Continued)

SYMBOL

PIN #

TYPE

DESCRIPTION

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INIC-525 Preliminary Data Sheet

Pin Definitions

Section 2

B_SACK+/-

28, 29

I/O

DIFFERENTIAL +/- PORT B SCSI ACKNOWLEDGE SIG-
NAL: When asserted, it indicates an acknowledgement of an
information transfer on the data bus.

B_SBSY+/-

30, 31

I/O

DIFFERENTIAL +/- PORT B SCSI BUSY SIGNAL: When
asserted, it indicates that the bus is in use.

B_SATN+/-

33, 34

I/O

DIFFERENTIAL +/- PORT B SCSI ATTENTION SIGNAL:
When asserted by an initiator, it indicates an ATTENTION
condition.

B_SSEL+/-

18, 19

I/O

DIFFERENTIAL +/- PORT B SCSI SELECT SIGNAL: When
asserted, it indicates an initiator trying to select a target or a
target trying to re-select an initiator.

B_SRST+/-

24, 25

I/O

DIFFERENTIAL +/- PORT B SCSI BUS RESET: When
asserted, it indicates a SCSI RESET condition.

Table 2-1 SCSI Interface Pins (Continued)

SYMBOL

PIN #

TYPE

DESCRIPTION

Section 2

Pin Definitions

INIC-525 Preliminary Data Sheet

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2.2 Miscellaneous Interface Pins

Table 2-2 Miscellaneous Interface Pins

SYMBOL

PIN #

TYPE

DESCRIPTION

RESET#

146

pullup

CHIP RESET: Active low. This asynchronous input resets the device.
A duration of 100ns is needed to achieve a reset condition. An inter-
nal analog power-on reset operation is also built-in. This function can
be used to replace the RESET# pin. It senses the Vdd supply and gen-
erates an internal reset signal to reset the device. It takes about ~30us
to negate the internal reset signal.

CLK

147

CLOCK: A 40MHz input clock is needed for chip operation.

WS_ENABLE

150

WARM START ENABLE: When low, the chip will wait for the next
bus free; then it will reset internally, disable the device, and places it in
an electrical isolation mode (this means devices are ready for warm
swap).

When high, wait for bus free; then enables the chip for normal SCSI
operation

XFER_ACTIVE

149

TRANSFER ACTIVE: When WS_ENABLE is low, the chip will wait
for next bus free; then it resets internally, disables the device, and
XFER_ACTIVE will go low for the LED indicator (indicating ready
for warm swap).

When high it indicates the chip is in normal SCSI operation mode.

BUSY_LED

148

BUSY ACTIVE LED: This output pin goes high when there is activity,
otherwise, the pin is low. Busy is defined by the SCSI bus being in a
valid SCSI state other than BUS_FREE.

RBIAS

RECEIVER BIAS CONTROL, R=9.76K ohm 1%

SIE_ENABLE

151

SCSI Signal Integrity Enhancement. If this pin is tied to high, then the
SCSI Signal Integrity Enhancement will be enabled. This pin provides
an alternative way of improving the signal quality in the event the 3V
Vdd for SCSI I/O drivers causes SCSI signal integrity problems. If this
pin is not connected, then SCSI Signal Integrity Enhancement will be
disabled.

5V_VDD

152

PWR

This pin needs to be tied to 5V Vdd if the SIE_Enable pin is enabled.
Otherwise this pin is unconnected.

153-156

n/a

No Connection

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INIC-525 Preliminary Data Sheet

Pin Definitions

Section 2

2.3 Power and Ground Pins

NOTES: 1. All VDD pins must be supplied 3.3 Volts.

2. If the power to the VDD

or VDD

CORE

pins are separated, either power up the pins simultaneously or

power up VDD

CORE

before VDD

. The VDD

pins need to powered down before the VDD

CORE

pins.

Table 2-3 Power and Ground Pins

SYMBOL

PIN #

TYPE

DESCRIPTION

VDD

SCSI

10, 27, 37, 51,
66, 75, 81, 99,

113, 121, 133

PWR

POWER for SCSI bus I/O pins

VSS

SCSI

7, 15, 22, 32, 41,

48, 56, 63, 71, 72,

80, 88, 95, 102,

110, 120, 128, 136,

160

GND

GROUND for SCSI bus I/O pins

VDD

CORE

26, 98

PWR

POWER for SCSI bus internal core logic

VSS

CORE

23, 103

GND

GROUND for SCSI bus internal core logic

VDD

158

PWR

POWER for SCSI bus I/O logic

VSS

144

GND

GROUND for SCSI bus I/O logic

INIC-525 Preliminary Data Sheet

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SECTION 3

Functional Description

3.1 INIC-525 Pin Functional Descriptions

All SCSI pin names described below use the naming conventions shown on this page. Pin names
with the post-fix "+/-" (eg B_SD+/-) refers to both LVD or SE operations capable. The "-" pin will
be used for SE mode of operation in this case. SCSI pins without the post-fix "+/-" ,or with the "#"
post-fix, are used for SE mode only. The INIC-525 supports either LVD or SE modes for both
sides. In the following section, a generic pin name, without the "#" or "+/-" post-fix, will be used
to signify the pins (eg, REQ refers to either REQ#, REQ+/- or REQ-).

SCSI Data & Parity (A_SD/A_SD+/-, B_SD+/-, A_SDP/A_SDP+/-, B_SDP+/-)
These data and parity pins are filtered as they come into the INIC-525. Internally, they are latched
for the purpose of re-timing referenced to the REQ/ACK signals depending on which data phases
it is.

REQ/ACK (A/B_SREQ#, A/B_SACK#, A/B_SREQ+/-, A/B_SACK+/-)
The REQ/ACK pins are filtered as they come in prior to going through a circuit to maintain a min-
imum pulse width. The leading edge is also delayed to optimize the setup times for REQ/ACK and
SCSI Data/Parity. Thereafter, the input's duration determines the output's duration. When one
port's signal is sensed to be driving, the other port's input will be disabled.

BSY (A/B_SBSY#, A/B_SBSY+/-)
The BSY pins are filtered as they come in. Depending on the SCSI state, the device automatically
selects 2 path options. One is to simply pass the BSY signal from one port to the other. In the
other option, the device will carefully time the circuit to pass over BSY from one port to the other
until the other port may also start driving. When the other port is sensed to be driving, the original
port's output will also be driven by the INIC-525INIC-525 to achieve a real wired-OR condition
just like a single SCSI bus. Thereafter, the original port's input will be turned off. The 2nd option
is automatically determined via the SCSI state machine and SCSI signals.

SEL (A/B_SSEL#, A/B_SSEL+/-)
The SEL pins are filtered as they come in. When one port's signal is sensed to be driving, the other
port's input will be disabled. In the event of both sides driving, port A's SEL will be propagated to
port B.

MSG/CD/IO/ATN (A/B_SMSG#, A/B_SCD#, A/B_SIO#, A/B_SATN#, A/B_SMSG+/-,
A/B_SCD+/-, A/B_SIO+/-, A/B_SATN+/-)
The MSG/CD/IO pins are filtered as they come in. When one port's signal is sensed to be driving,
the other port's input will be disabled.

RST (A/B_SRST#, A/B_SRST+/-)
The RST pins are filtered as they come in. This filter is a larger 25ns filter design. In the event of a
LVD or SE mode selection change, the RST will be asserted. When the ISOLATE pin is asserted
(high), the device will not assert RST even if the LVD/SE mode changes.

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INIC-525 Preliminary Data Sheet

Functional Description

Section 3

3.2 INIC-525 Functional Diagram

Figure 3-1 below shows the INIC-525 pin functional descriptions.

Figure 3-1 INIC-525 Functional Diagram

A_SD[15:0]+

A_SD[15:0]-

A_SDP[1:0]+

A_SDP[1:0]-

A_SCD+

A_SCD-

A_SIO+

A_SIO-

A_SMSG+

A_SMSG-

A_SREQ+

A_SREQ-

A_SACK+

A_SACK-

A_SBSY+

A_SBSY-

A_SATN+

A_SATN-

A_SSEL+

A_SSEL-

A_SRST+

A_SRST-

RESET#

CLK

WS_ENABLE

A_DIFF_SENSE

A_HVD_MODE

B_SD[15:0]+

B_SD[15:0]-

B_SDP[1:0]+

B_SDP[1:0]-

B_SCD+

B_SCD-

B_SIO+

B_SIO-

B_SMSG+

B_SMSG-

B_SREQ+

B_SREQ-

B_SACK+

B_SACK-

B_SBSY+

B_SBSY-

B_SATN+

B_SATN-

B_SSEL+

B_SSEL-

B_SRST+

B_SRST-

B_DIFF_SENSE

INIC-525 SCSI

Expander/Converter

BSY_LED

XFER_ACTIVE

B_HVD_MODE

INIC-525 Preliminary Data Sheet

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SECTION 4

Electrical Specifications

4.1 Absolute Maximum Ratings

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and the functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

4.2 Recommended Operating Conditions

4.2.1 SCSI Single Ended (SE) Recommended Operating Conditions

Ta = -0

C to +70

= 3.3V ± 5%

= 0V

Input leakiage include hi-Z output leakage for all bi-directional buffers with tri-state outputs :
(A/B_SD[15:0], A/B_SDP[1:0], A/B_SREQ#, A/B_SACK#, A/B_SSEL#, A/B_SBSY#,
A/B_SRST#, A/B_SATN#, A/B_SMSG#, A/B_SCD#, A/B_SIO#).

Table 4-1 Absolute Maximum Ratings

Environment
(maximum
ratings

Storage Temperature

-55

C to +125

Operating Temperature

-0

C to +70

ESD Immunity

2.0 KV human model

Voltage Levels
(maximum
ratings)

Power Supply Voltages

3.6 Volts

(VDD = 3.3V)

Terminal Voltage on any pin with
respect to ground

-0.5 to +5.5 Volts (SCSI SE pins)
-0.5 to +4.1 Volts (SCSI LVD/MSE pins)

Table 4-2 SCSI Single Ended (SE) Recommended Operating Conditions

Symbol Parameter

Minimum

Maximum

Units

Test

Condition

Notes

Supply Voltage

3.13

3.47

Input Leakage Voltage

-20

Input High Voltage

1.9

Input Low Voltage

1.0

IHYS

Input Hysteresis

0.3

Output High Voltage

2.0

= 7 mA

Output Low Voltage

0.5

= 48 mA

Input Pin Capacitance

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INIC-525 Preliminary Data Sheet

Electrical Specifications

Section 4

4.2.2 SCSI Low Voltage Differential (LVD) Recommended Operating Conditions

Ta = -0

C to +70

= 3.3V ± 5%

= 0V

Input leakiage include hi-Z output leakage for all bi-directional buffers with tri-state outputs
(A/B_SD[15:0], A/B_SDP[1:0], A/B_SREQ#, A/B_SACK#, A/B_SSEL#, A/B_SBSY#,
A/B_SRST#, A/B_SATN#, A/B_SMSG#, A/B_SCD#, A/B_SIO#).

4.2.3 SCSI DIFFSENS Receiver Recommended Operating Conditions

Ta = -0

C to +70

= 3.3V ± 5%

= 0V

Table 4-3 SCSI Low Voltage Differential (LVD) Recommended Operating Conditions

Symbol

Parameter

Minimum

Maximum

Units

Test Condition

Notes

Supply Voltage

3.13

3.47

Input Leakage Current

-20

Differential Output
(asserted)

0.32

0.8

V1=1.056V, V2=0.634V
V1=1.866V, V2=1.444V

Differential Output
(negated)

0.32

0.8

V1=1.056V, V2=0.634V
V1=1.866V, V2=1.444V

Common Mode Output

0.845

1.655

= 2 mA

Input Pin Capacitance

Table 4-4 SCSI DIFFSENS Receiver Recommended Operating Conditions

Symbol

Parameter

Minimum

Maximum

Units

Test Condition

Notes

Single-ended Sense Voltage

-0.35

0.5

LVD

Low Voltage Differential
Sense Voltage

0.7

1.9

HVD

High Voltage Differential
Sense Voltage

2.4

VDD+0.3

Input Leakage Current

-20

INIC-525 Preliminary Data Sheet

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SECTION 5

Timing Specifications

5.1 General Timing

Timing values in the `Preliminary' Data Sheet are derived from timing simulation. After AC Characteriza-
tion of the device, the Data Sheet's timing values reflect characterization data (unless noted otherwise), at
which time `Preliminary' is removed from the Data Sheet title and footers.

5.1.1 AC Input/Output Timing Parameters

Figure 5-1 AC Input/Output Timing

Symbol

Parameter

Min

Values

Typ

Max

Units

Notes

Signal Fall Time

Cap loading @ 15pF

Signal Rise Time

1.4V

90%

10%

90%

10%

1.4V

AC INPUT CONDITIONS

AC OUTPUT TIMING CONDITIONS

2.3V

0.7V

2.3V

0.7V

Test Point

From Output
Under Test

OUTPUT TEST LOAD DIAGRAM

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Section 5

Timing Specifications

INIC-525 Preliminary Data Sheet

Confidential

5.2 SCSI Signal Interface Parameters

5.2.1 SCSI Interface Timing Parameters

Table 5-1 SCSI Interface Timing Parameters (Single Transition)

Symbol Parameter

Minimum

Maximum

Units

Notes

Input Data Setup (Fast-40)

Input Data Setup (Fast-20)

Input Data Setup (Fast-10)

Input Data Setup (Fast-5)

4.75

6.5

Input Data Hold (Fast-40)

Input Data Hold (Fast-20)

Input Data Hold (Fast-10)

Input Data Hold (Fast-5)

4.75

11.5

Input REQ/ACK assertion pulse width
(Fast-40 - LVD

LVD only)

Input REQ/ACK assertion pulse width
(Fast-20)

6.5

Input REQ/ACK de-assertion pulse width
(Fast-40 - LVD

LVD only)

Input REQ/ACK de-assertion pulse width
(Fast-20)

Data Transport Delay (LVD

LVD)

Data Transport Delay (LVD

SE)

Data Transport Delay (SE

SE)

Output Data Setup (Fast 40 - LVD

LVD only)

Output Data Setup (Fast 20)

9.5

Output Data Hold (Fast 40 - LVD

LVD only)

Output Data Hold (Fast 20)

9.5

REQ/ACK Transport Delay (LVD

LVD)

REQ/ACK Transport Delay (LVD

SE)

REQ/ACK Transport Delay (SE

SE)

Output REQ/ACK pulse width (LVD

LVD)

Output REQ/ACK pulse width (any port SE)

Confidential

INIC-525 Preliminary Data Sheet

Timing Specifications

Section 5

Table 5-2 SCSI Interface Timing Parameters (Double Transition)

Symbol Parameter

Minimum

Maximum

Units

Notes

Input Data Setup (Fast-80)

Input Data Setup (Fast-40)

Input Data Setup (Fast-20)

Input Data Setup (Fast-10)

1.45

2.9

5.8

11.6

Input Data Hold (Fast-80)

Input Data Hold (Fast-40)

Input Data Hold (Fast-20)

Input Data Hold (Fast-10)

1.45

2.9

5.8

11.6

Input REQ/ACK assertion pulse width
(Fast-80 - LVD

LVD only)

Input REQ/ACK assertion pulse width
(Fast-40 - LVD

LVD only)

Input REQ/ACK assertion pulse width
(Fast-20)

Input REQ/ACK de-assertion pulse width
(Fast-80 - LVD

LVD only)

Input REQ/ACK de-assertion pulse width
(Fast-40 - LVD

LVD only)

Input REQ/ACK de-assertion pulse width
(Fast-20)

Data Transport Delay (LVD

LVD)

Data Transport Delay (LVD

SE)

Data Transport Delay (SE

SE)

Output Data Setup (Fast 80 - LVD

LVD only)

Output Data Setup (Fast 40 - LVD

LVD only)

Output Data Setup (Fast 20)

Output Data Hold (Fast 80 - LVD

LVD only)

Output Data Hold (Fast 40 - LVD

LVD only)

Output Data Hold (Fast 20)

REQ/ACK Transport Delay (LVD

LVD)

REQ/ACK Transport Delay (LVD

SE)

REQ/ACK Transport Delay (SE

SE)

Output REQ/ACK pulse width (Fast 80 - LVD

LVD)

Output REQ/ACK pulse width (Fast 40 - LVD

LVD)

Output REQ/ACK pulse width (any port SE)

11.5

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tion if such be made.

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mance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customerís
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