ChipFind - документация

Электронный компонент: IN16C01

Скачать:  PDF   ZIP
IN16C01
Korzhenevskogo 12, Minsk, 220108, Republic of
Belarus
Fax: +375 (17) 278 28 22,
Phone: +375 (17) 278 07 11, 212 24 70, 212 24 61,
212 69 16
E-mail: office@bms.by
URL: www.bms.by
16-
BIT
RISC
M
ICROCONTROLLER
1. Introduction
The IN16C01 is a CMOS single-chip 16-bit microcontroller.
The IN16C01 is a general purpose microcomputer and can be used in control systems, data
acquisition systems and DSP systems. Low-power and fully static operation allow to use the
microcontroller in self-contained systems with limited power consumption.
On the base of its capabilities the IN16C01 could be compared with the next general-purpose
microcontrollers: Intel's 80С196 and 80C186, Motorola's 68300 and 68НС16, Siemens' SAB
80C16x. The IN16C01 has an array multiplier and dedicated hardware for DSP operations support,
which allows to compare the microcontroller with the next DSP: Texas Instruments' TMS320C25,
Motorola's DSP561хх, Analog Devices' ADSP21xx.
The IN16C01 implements the modular architecture when there is a common internal bus to which
all other units are connected. The architecture allows to `tailor' the microcontroller to an appropriate
customer's application. The basic set of the microcontroller units includes:
ћ Microprocessor
ћ RAM
ћ ROM
ћ Timers
ћ UART
ћ Synchronous Serial Interface (SSI)
ћ Bi-directional Parallel Ports
The microcontroller is assumed to be extended with ADC, EEPROM, PWM unit, I
2
C
interface and other units in future.
2. Architectural Overview
A simplified functional block diagram of the IN16C01 microcontroller is shown in fig.2.1.
Fig. 2.1. Simplified functional block diagram of the IN16C01
IN16C01
Korzhenevskogo 12, Minsk, 220108, Republic of
Belarus
Fax: +375 (17) 278 28 22,
Phone: +375 (17) 278 07 11, 212 24 70, 212 24 61,
212 69 16
E-mail: office@bms.by
URL: www.bms.by
As one can see in the figure the microcontroller consists of the following units:
ћ CPU
core
ћ RAM
ћ PROM
ћ Timer system (counter/timer, watchdog timer)
ћ UART
ћ Synchronous serial interface (SSI)
ћ Parallel ports D, C
The IN16C01 is a synchronous VLSI with fully static operation, i.e. the microcontroller's clock may be shut
off indefinitely without the device losing its state. Once the clock is restored the microcontroller will begin
executing as if there had been no interruption.
The current IN16C01 realisation is assumed to have the maximum clock frequency of 10 MHz.
2.1 CPU
core

The brains of the IN16C01 is the CPU core.
Main CPU core features are:
ћ Stack oriented RISC architecture
ћ 24-bit
address
ћ 16/32-data
ћ Modified Harvard architecture with independent
simultaneous access to the program and data
spaces
ћ Two data stacks of 8 sixteen-bit words each
ћ Sixteen 24 bit words for return stack
ћ Eight 24 bit words for address stack
ћ All instructions are executed in one or two clock
cycles
ћ Interrupt response of two clock cycles
ћ 16x16 multiply in one clock cycle
ћ Multiply-accumulate (with 38 bit accumulator) in
two clock cycles
ћ Divide operation support
The stack oriented architecture means that the
processed data are stored in a stack (the data stack).
Vast majority of the microcontroller's instructions use
one or two top stack words as their operands. The
particular feature of the IN16C01 is that it has four
stacks: two stacks for data, a return stack and an
address stack. All the stacks can operate
simultaneously. The data stacks contain processed
data. The return stack contains 'return from
subroutine' addresses or variables addresses. The
address stack
contains variables addresses.
Fig. 2.2. Block diagram of the CPU core

The block diagram of the CPU core is shown in fig. 2.2. As one can see from the figure,
the CPU contains the following units:
DS
IN16C01
Korzhenevskogo 12, Minsk, 220108, Republic of
Belarus
Fax: +375 (17) 278 28 22,
Phone: +375 (17) 278 07 11, 212 24 70, 212 24 61,
212 69 16
E-mail: office@bms.by
URL: www.bms.by
The data stack. The stack consists of internal stack memory (two fields of eight 16-bit
words) and the 'top' and 'next' registers: T and N.
Т
The 32-bit 'top' register of the data stack. The register is accessible as a 16-bit register (t
or %t) or a 32-bit register (Т). The register is always used as one of the ALU operands.
N
The 32-bit 'next' register of the data stack. The register is always used as the second ALU
operand and is employed for arithmetic operations.
The data, written into the data stack memory, are always taken from the N register. The
data, read from the data stack memory, are written into the N register. The N register can
be moved into the T register via the ALU. During the data stack push operation, the T
register can be written directly into the N register.
Move operations between the T and N registers and between the N register and the data
stack are independent from each other and can be executed simultaneously.
RS
The return stack. The stack consists of internal return stack memory of sixteen 24-bit
words and the RT register. The return stack is accessible via the RT register only.
RT
The 24-bit 'top' register of the return stack. During RT register read, the return stack can
be 'popped'. During RT register write, the return stack can be 'pushed'. The RT register is
used in subroutine calls and return from subroutine instructions, and to local variables
storing as well.
AS
The address stack. The stack consists of internal address stack memory of eight 24-bit
words and the AT register. The address stack is accessible via the AT register only.
AT
The 24-bit 'top' register of the address stack. The register stores variables' addresses.
During AT register read, the address stack can be 'popped'. During RT register write, the
address stack can be 'pushed'.
аsp, dsp, rsp
The address, data and return stacks' pointers. These registers are not accessible to
software.
L
The 16-bit instruction register.
РС
The 24-bit program counter.
CT
IN16C01
Korzhenevskogo 12, Minsk, 220108, Republic of
Belarus
Fax: +375 (17) 278 28 22,
Phone: +375 (17) 278 07 11, 212 24 70, 212 24 61,
212 69 16
E-mail: office@bms.by
URL: www.bms.by
The 16-bit general purpose register. The register can be used as a counter. The register
contents can be analysed by conditional branch instructions and can be decremented
concurrently with an ALU operation. The register is used as a counter in flow mode
instructions.
USER
The 24-bit address register. The register's contents are used as a base address during
external registers access.
SP
The 24-bit general purpose register. The register can contain an address and can be used
to address the data memory as well.
RP
The 24-bit general purpose register. The register can contain an address and can be used
to address the data memory as well.
WORK
The 32-bit general purpose register. The register can be used in integer multiply and
multiply-accumulate operations.
ALU
The 16-bit arithmetic-logic unit with a multiplier. The ALU's two operands are the T and N
registers.
PSW
16-bit processor status word..
2.2 Memory
The microcontroller address space is divided into data and program memory. The
IN16C01 accesses the internal data and program memories concurrently using separate
buses. An external memory access is accomplished via common bus with separate
address and data. The SDI input signal defines the type of the space selected (data or
program). The internal data memory can not be modified.
The CPU core addresses 16-bit words in memory. One clock cycle is needed to read or
write a memory word.
The microcontroller supports a possibility to write high/low bytes in a 16-bit word. There
are special prefixes in the IN16C01 instruction set: BYTE_L and BYTE_H. These prefixes
control WRL and WRH signals.
IN16C01
Korzhenevskogo 12, Minsk, 220108, Republic of
Belarus
Fax: +375 (17) 278 28 22,
Phone: +375 (17) 278 07 11, 212 24 70, 212 24 61,
212 69 16
E-mail: office@bms.by
URL: www.bms.by
Fig 2.3. Memory Map of the IN16C01
3
The Microcontroller Pins
The IN16C01 is available in PQFP 100 package (see fig. 3.1.).
Table 5.1. The IN16C01 pin assignment
Pin
number
Mnemonic In/Out
Function
1
TXD_R
in/out
transmitter's data SSI_R
2 VDD
supply
3 VSS
ground
4
CLKX_R
in/out
transmitter's clock SSI_R
5
FSX_L
in/out
transmitter's clock SSI_L
6
TXD_L
in/out
transmitter's data SSI_L
7
CLKX_L
in/out
transmitter's clock SSI_L
8
CLKR_L
in
receiver's clock SSI_L
9
FSR_L
in
receiver's clock SSI_L
10
RXD_L
in
receiver's data SSI_L
11
PD15
in/out
15-th bit of the D port
12
PD14
in/out
14-th bit of the D port
13
PD13
in/out
13-th bit of the D port
14
PD12
in/out
12-th bit of the D port
15
PD11
in/out
11-th bit of the D port
16
PD10
in/out
10-th bit of the D port
17
PD9
in/out
9-th bit of the D port
18
PD8
in/out
8-th bit of the D port