TECHNICAL DATA
2K 2.5V CMOS Serial EEPROMs
IN24LC02B
DESCRIPTION
IN24LC02B is a 2K-bit Electrically Erasable PROM. The device is organized as a single
block of 256 x 8 bit memory with a two wire serial interface.
Low voltage design permits operation down to 2.5volts with standby and active currents
of only 5
A and 1mA respectively.
The IN24LC02B also has a page-write capability for up to 8 bytes of data.
The IN24LC02B is available in the standard 8-pin DIP.
PACKAGE
T
A
= -40 ... +85
C
PINNING
Name Function
Vss Ground
SDA
Serial Address/Data I/O
SCL Serial
Clock
WP
Write Protect Input
VCC
+2.5V to 5.5V Power Supply
AO, A1, A2
No Internal Connection
FEATURES
Single supply with operation down to 2.5V
Low power CMOS technology
- 1 mA active current typical
- 10
A standby current typical at 5.5V
- 5
A standby current typical at 3.0V
Organized as a single block of 256 bytes (256x8)
Two wire serial interface bus, I
2
C compatible
Schmitt trigger, filtered inputs for noise suppression
Output slope control to eliminate ground bounce
100 kHz (2.5V) and 400 kHz (5V) compatibility
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
2 ms typical write cycle time for page-write
Hardware write protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection > 3,000V
1,000,000 ERASE/WRITE cycles guaranteed*
Data retention > 200 years
Pin Connection
1 8
2 7
3 6
4 5
A0
Vcc
A1
WP
A2
SCL
Vss
SDA
1
IN24LC02B
Figure 1. Representative Block Diagram
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
Parameter Value
V
CC
7.0 V
All inputs and outputs w.r.t.Vss
-0.6V to Vcc + 1.0V
Storage temperature
-65
o
C to +150
o
C
Ambient temp. with power applied
-40
o
C to +85
o
C
Soldering temperature of leads (10 seconds)
+300
o
C
ESD protection on all pins
> 4 kV
DC CHARACTERISTICS
Vcc = +2.5V to +5.5V: Tamb = -40
o
C to +85
o
C
Parameter Symbol
Min
Max
Units
Mode
WP, SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage
V
lH
V
IL
V
HYS
V
OL
0.7V
CC
-
0.05V
CC
-
-
0.3V
CC
-
0.40
V
V
V
V
Note 1
I
OL
= 3.0mA, V
CC
= 2.5V
Input leakage current
I
LI
-10 10
A
V
lN
=0.1V to V
CC
Output leakage current
I
LO
-10 10
A
V
OUT
=0.1V to V
CC
Pin capacitance (all inputs/outputs)
C
IN
C
OUT
- 10
pF
V
CC
= 5.0V (Note 1)
Tamb =25
o
C,Fclk =1MHz
Operating current
I
CC
WRITE
I
CC
READ
-
-
3
1
mA
mA
V
CC
= 5.5V SCL =400 kHz
Standby current
I
CCS
-
-
30
100
A
A
SDA=SCL=V
CC
=3.0V,
SDA=SCL=V
CC
=5.5V
2
IN24LC02B
Figure 2. Bus timing Start/Stop
AC CHARACTERISTICS
STANDARD
MODE
Vcc = 4.5 - 5.5V
FAST MODE
Parameter
Symbol
Min
Max Min Max
Units
Remarks
Clock frequency
F
CLK
-
100 - 400
kHz
Clock high time
T
HIGH
4000
-
600
- ns
Clock low time
T
LOW
4700
- 1300 - ns
SDA and SCL rise time
T
R
-
1000 - 300
ns
Note
2
SDA and SCL fall time
T
F
-
300 - 300
ns
Note
2
START condition hold time
T
HD:STA
4000
-
600
-
ns
After this period the
first clock pulse is
generated
START condition setup time
T
SU:STA
4700
-
600
-
ns
Only relevant for
repeated START
condition
Data input hold time
T
HD:DAT
0 -
0
- ns
Data input setup time
T
SU:DAT
250 -
100
- ns
STOP condition setup time
T
SU:STO
4000
-
600
-
ns
Output valid from clock
T
AA
-
3500 - 900
ns
Note
1
Bus free time
T
BUF
4700
- 1300 - ns
Time the bus must be
free before a new
transmission can start
Output fall time from V
IH
min
to V
IL
max
T
OF
-
250
20+0.1C
B
250 ns
Note2,
C
B
100pF
Input filter spike suppres-sion
(SDA & SCL pins)
T
SP
-
50 - 50
ns
Note 3
Write cycle time
T
WR
-
10 - 10
ms
Byte or Page mode
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined
region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or
STOP conditions.
Note 2: Not 100% tested. C
B
= total capacitance of one bus line in pF.
Note 3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide
improved noise and spike suppression. This eliminates the need for a Ti specification for standard
operation.
3
IN24LC02B
Figure 3. Bus timing Data
FUNCTIONAL DESCRIPTION
The IN24LC02B supports a bidirectional two wire bus and data transmission protocol. A device
that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The
bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus
access, and generates the START and STOP conditions, while the IN24LC02B works as slave.
Both, master and slave can operate as transmitter or receiver but the master device determines
which mode is activated.
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been defined (see Figure 4).
Bus not Busy (A)
Both data and clock lines remain HIGH.
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START
condition. All commands must be preceded by a START condition.
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP
condition. All operations must be ended with a STOP condition.
Data Valid (D)
The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW period of the clock signal. There is one clock
pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of the data bytes transferred between the START and STOP conditions is determined by the
master device and is theoretically unlimited, although only the last sixteen will be stored when
doing a write operation. When an overwrite does occur it will replace data in a first in first out
fashion.
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
4
IN24LC02B
Note: The IN24LC02B does not generate any acknowledge bits if an internal programming cycle is in
progress
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse
in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the data line HIGH to enable the master to
generate the STOP condition.
Figure 4. Data Transfer Sequence on the serial bus
BUS CHARACTERISTICS
Slave Address
The IN24LC02B are software-compatible with devices such as 24C01A, 24C02A, 24LC01,
and 24LC02B. A single 24LC02B can be used in place of two 24LC01's,
for example, without any modifications to software.
The "chip select" portion of the control byte becomes a don't care.
After generating a START condition, the bus master transmits the slave address consisting
of a 4-bit device code (1010) for the IN24LC02B, followed by three don't care bits.
The eighth bit of slave address determines if the master device wants to read or write to
the IN24LC02B (see Figure 5).
The IN24LC0 monitors the bus for its corresponding slave address all the time.
It generates an acknowledge bit if the slave address was true and it is not in a programming
mode.
Operation
Control Code
Chip Select
R/W
Read 1010 XXX
1
Write 1010 XXX
0
5
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