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Электронный компонент: IN74AC193N

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TECHNICAL DATA
288
Presettable 4-Bit Binary UP/DOWN Counter
High-Speed Silicon-Gate CMOS
The IN74AC193 is identical in pinout to the LS/ALS193,
HC/HCT193. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
The counter has two separate clock inputs, a Count Up Clock and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When
the Parallel Load input is taken low the data is loaded independently of
either clock input. This feature allows the counters to be used as
devide-by-n by modifying the count lenght with the preset inputs. In
addition the counter can also be cleared. This is accomplished by
inputting a high on the Master Reset input. All 4 internal stages are set
to low independently of either clock input.Both a Terminal Count
Down (TC
D
) and Terminal Count Up (TC
U
) Outputs are provided to
enable cascading of both up and down counting functions. The TC
D
output produces a negative going pulse when the counter underflows
and TC
U
outputs a pulse when the counter overflows. The counter can
be cascaded by connecting the TC
U
and TC
D
outputs of one device to
the Count Up Clock and Count Down Clock inputs, respectively, of the
next device.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A; 0.1
A @ 25
C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
IN74AC193
ORDERING INFORMATION
IN74AC193N Plastic
IN74AC193D SOIC
T
A
= -40
to 85
C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
IN74AC193
289
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Sink/Source Current, per Pin
50
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
J
Junction Temperature (PDIP)
140
C
T
A
Operating Temperature, All Package Types
-40
+85
C
I
OH
Output Current - High
-24
mA
I
OL
Output Current - Low
24
mA
t
r
, t
f
Input Rise and Fall Time
*
(except Schmitt Inputs)
V
CC
=3.0 V
V
CC
=4.5 V
V
CC
=5.5 V
0
0
0
150
40
25
ns/V
*
V
IN
from 30% to 70% V
CC
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
IN74AC193
290
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limits
Symbol
Parameter
Test Conditions
V
25
C
-40
C to
85
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
3.0
4.5
5.5
2.1
3.15
3.85
2.1
3.15
3.85
V
V
IL
Maximum Low -Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
3.0
4.5
5.5
0.9
1.35
1.65
0.9
1.35
1.65
V
V
OH
Minimum High-Level
Output Voltage
I
OUT
-50
A
3.0
4.5
5.5
2.9
4.4
5.4
2.9
4.4
5.4
V
*
V
IN
=V
IH
or V
IL
I
OH
=-12 mA
I
OH
=-24 mA
I
OH
=-24 mA
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
V
OL
Maximum Low-Level
Output Voltage
I
OUT
50
A
3.0
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
*
V
IN
=V
IH
or V
IL
I
OL
=12 mA
I
OL
=24 mA
I
OL
=24 mA
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
I
IN
Maximum Input Leakage
Current
V
IN
=V
CC
or GND
5.5
0.1
1.0
A
I
OLD
+Minimum Dynamic
Output Current
V
OLD
=1.65 V Max
5.5
75
mA
I
OHD
+Minimum Dynamic
Output Current
V
OHD
=3.85 V Min
5.5
-75
mA
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
5.5
8.0
80
A
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
FUNCTION TABLE
Inputs
Mode
MR
PL
CP
U
CP
D
H
X
X
X
Reset(Asyn.)
L
L
X
X
Preset(Asyn.)
L
H
H
No Count
L
H
H
Count Up
L
H
H
Count Down
L
H
H
No Count
X = don't care
The IN74AC193 is an UP/DOWN MODULO-
16 Binary Counter.
Logic equations
For Terminal Count:
TC
U
= Q
0
Q
1
Q
2
Q
3
CP
U
TC
D
= Q
0
Q
1
Q
2
Q
3
CP
D
IN74AC193
291
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC
*
Guaranteed Limits
Symbol
Parameter
V
25
C
-40
C to 85
C
Unit
Min
Max
Min
Max
f
max
Maximum Clock Frequency (Figure 1)
3.3
5.0
88
120
40
55
MHz
t
PLH
Propagation Delay, CP
U
or CP
D
to TC
U
or
TC
D
(Figure 2)
3.3
5.0
20
13
22
14.5
ns
t
PHL
Propagation Delay, CP
U
or CP
D
to TC
U
or
TC
D
(Figure 2)
3.3
5.0
19
11.5
21
13.0
ns
t
PLH
Propagation Delay, CP
U
or CP
D
to Q
n
(Figure
1)
3.3
5.0
15
10
17.0
11.5
ns
t
PHL
Propagation Delay, CP
U
or CP
D
to Q
n
(Figure
1)
3.3
5.0
15
9.5
17.0
11
ns
t
PLH
Propagation Delay, P
n
to Q
n
(Figure 3)
3.3
5.0
15
10
17.0
11.5
ns
t
PHL
Propagation Delay, P
n
to Q
n
(Figure 3)
3.3
5.0
15
9.5
17.0
11
ns
t
PLH
Propagation Delay, PL to Q
n
(Figure 4)
3.3
5.0
15
10
17
11.5
ns
t
PHL
Propagation Delay, PL to Q
n
(Figure 4)
3.3
5.0
20
12.5
22
14
ns
t
PHL
Propagation Delay, MR to Q
n
(Figure 5)
3.3
5.0
20
12.5
22
14
ns
t
PLH
Propagation Delay, MR to TC
U
(Figure 6)
3.3
5.0
18
12
20
13.5
ns
t
PHL
Propagation Delay, MR to TC
D
(Figure 6)
3.3
5.0
19
11.5
21
13.0
ns
t
PLH
Propagation Delay, PL to TC
U
or TC
D
(Figure
6)
3.3
5.0
20
13
22
14.5
ns
t
PHL
Propagation Delay, PL to TC
U
or TC
D
(Figure
6)
3.3
5.0
15
8.5
17
10
ns
t
PLH
Propagation Delay, P
n
to TC
U
or TC
D
(Figure
6)
3.3
5.0
20
13
22
14.5
ns
t
PHL
Propagation Delay, P
n
to TC
U
or TC
D
(Figure
6)
3.3
5.0
20
12.5
22
14
ns
C
IN
Maximum Input Capacitance
5.0
4.5
4.5
pF
Typical @25
C,V
CC
=5.0 V
C
PD
Power Dissipation Capacitance
45
pF
*
Voltage Range 3.3 V is 3.3 V
0.3 V
Voltage Range 5.0 V is 5.0 V
0.5 V
IN74AC193
292
TIMING REQUIREMENTS
(C
L
=50pF, Input t
r
=t
f
=3.0 ns)
V
CC
*
Guaranteed Limits
Symbol
Parameter
V
25
C
-40
C to
85
C
Unit
t
su
Minimum Setup Time, P
n
to PL (Figure 7)
3.3
5.0
9
6
10
7
ns
t
h
Minimum Hold Time, PL to P
n
(Figure 7)
3.3
5.0
-1.0
-1.0
0
0
ns
t
w
Minimum Pulse Width, PL (Figure 4)
3.3
5.0
17
12
21
13
ns
t
w
Minimum Pulse Width, CP
U
or CP
D
(Figure 1)
3.3
5.0
11
8
12
9
ns
t
w
Minimum Pulse Width, MR (Figure 5)
3.3
5.0
14
10
16
12
ns
t
rec
Minimum Recovery Time, PL to CP
U
or CP
D
(Figure 5)
3.3
5.0
9
12
10
13
ns
t
rec
Minimum Recovery Time, MR to CP
U
or CP
D
(Figure 5)
3.3
5.0
17
12
21
14
ns
*
Voltage Range 3.3 V is 3.3 V
0.3 V
Voltage Range 5.0 V is 5.0 V
0.5 V
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms