IN74HC163A
1
P
RESETTABLE
C
OUNTERS
High-Performance Silicon-Gate CMOS
The IN74HC163A is identical in pinout to the LS/ALS163. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC163A is programmable 4-bit synchronous counter
that feature parallel Load, synchronous Reset, a Carry Output for
cascading and count-enable controls.
The IN74HC163A is binary counter with synchronous Reset.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC163AN Plastic
IN74HC163AD SOIC
T
A
= -55
to 125 C for all
packages
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
FUNCTION TABLE
Inputs Outputs
Rese
t
Load Enable
P
Enable
T
Clock Q0 Q1 Q2 Q3 Function
L X X
X
L L L L Reset
to
"0"
H
L
X
X
P0 P1 P2 P3 Preset
Data
H
H
X
L
No change
No count
H
H
L
X
No change
No count
H H H H
Count
up
Count
X
X
X
X
No change
No count
X=don't care
P0,P1,P2,P3 = logic level of Data inputs
Ripple Carry Out = Enable T
Q0 Q1 Q2 Q3
PIN ASSIGNMENT
IN74HC163A
2
MAXIMUM RATINGS
*
Symbol Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
25
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10
Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65 to 125C
SOIC Package: : - 7 mW/
C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to
GND)
0 V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure
1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, V
IN
and
V
OUT
should be constrained to the range GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
V
CC
). Unused outputs must be left open.
IN74HC163A
3
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
V
CC
Guaranteed
Limit
Symbol Parameter
Test
Conditions
V 25
C
to
-55
C
85
C
125
C
Unit
V
IH
Minimum
High-
Level Input
Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20 A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low -
Level Input
Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20 A
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum
High-
Level Output
Voltage
V
IN
=V
IH
or V
IL
I
OUT
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
=V
IH
or V
IL
I
OUT
6.0 mA
I
OUT
7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum
Low-
Level Output
Voltage
V
IN
=V
IH
or V
IL
I
OUT
20 A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
=V
IH
or V
IL
I
OUT
6.0 mA
I
OUT
7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum
Input
Leakage Current
V
IN
=V
CC
or GND
6.0
0.1
1.0
1.0
A
I
CC
Maximum
Quiescent Supply
Current
(per Package)
V
IN
=V
CC
or GND
I
OUT
=0
A
6.0 4.0 40 160
A
IN74HC163A
4
AC ELECTRICAL CHARACTERISTICS(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25
C
to
-55
C
85C 125
C
Unit
f
max
Maximum Clock Frequency (Figures1,6)
2.0
4.5
6.0
6
30
35
5
24
28
4
20
24
MHz
t
PLH
Maximum Propagation Delay Clock to Q
2.0
4.5
6.0
120
20
16
160
23
20
200
28
22
ns
t
PHL
(Figures
1,6)
2.0
4.5
6.0
145
22
18
185
25
20
320
30
23
ns
t
PLH
Maximum Propagation Delay Enable T to
Ripple Carry Out
2.0
4.5
6.0
110
16
14
150
18
15
190
20
17
ns
t
PHL
(Figures
2,6)
2.0
4.5
6.0
135
18
15
175
20
16
210
22
20
ns
t
PLH
Maximum Propagation Delay Clock to
Ripple
2.0
4.5
6.0
120
22
18
160
27
22
200
30
25
ns
t
PHL
Carry Out (Figures 1,6)
2.0
4.5
6.0
145
22
20
185
28
24
220
35
28
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any
Output, (Figures 1 and 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per
Gate)
Typical @25
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic
power consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
30 pF
IN74HC163A
5
TIMING REQUIREMENTS (C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25
C
to
-55
C
85C 125
C
Unit
t
su
Minimum Setup Time, Preset Data Inputs
to Clock (Figure 4)
2.0
4.5
6.0
40
15
12
60
20
18
80
30
20
ns
t
su
Minimum Setup Time, Load to Clock
(Figure 4)
2.0
4.5
6.0
60
15
12
75
20
18
90
30
20
ns
t
su
Minimum Setup Time, Reset to Clock
(Figure 3)
2.0
4.5
6.0
60
20
17
75
25
23
90
35
25
ns
t
su
Minimum Setup Time, Enable T or
Enable P to Clock (Figure 5)
2.0
4.5
6.0
80
20
17
95
25
23
110
35
25
ns
t
h
Minimum Hold Time, Clock to Load or
Preset Data Inputs (Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
h
Minimum Hold Time, Clock to Reset
(Figure 3)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
h
Minimum Hold Time, Clock to Enable T
or Enable P (Figure 5)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
rec
Minimum Recovery Time, Load Inactive
to Clock (Figure 4)
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
t
w
Minimum Pulse Width, Clock (Figure 1)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
w
Minimum Pulse Width, Reset (Figure 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
r,
t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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