TECHNICAL DATA
228
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The IN74HC165 is identical in pinout to the LS/ALS165. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/ Parallel Load input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the
rising edge of either Clock or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
IN74HC165
ORDERING INFORMATION
IN74HC165N Plastic
IN74HC165D SOIC
T
A
= -55
to 125
C for all packages
LOGIC DIAGRAM
PIN 16=V
CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Internal Stages
Output
Operation
Serial Shift/
Parallel Load
Clock
Clock
Inhibit
S
A
A-H
Q
A
Q
B
-Q
G
Q
H
L
H
X
X
a...h
a
b-g
h
Asynchronous Parallel Load
H
L
L
X
L
Q
An
-Q
Fn
Q
Gn
Serial Shift via Clock
H
L
H
X
H
Q
An
-Q
Fn
Q
Gn
H
L
L
X
L
Q
An
-Q
Fn
Q
Gn
Serial Shift via Clock
H
L
H
X
H
Q
An
-Q
Fn
Q
Gn
Inhibit
H
X
H
X
X
no change
Inhibited Clock
H
H
X
X
X
H
L
L
X
X
no change
No Clock
X = Don't Care
Q
An
-Q
Fn
= Data shifted from the preceding stage
PIN ASSIGNMENT
IN74HC165
229
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
25
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
IN74HC165
230
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
C
to
-55
C
85
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low -
Level Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20
A
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
=V
IH
or V
IL
I
OUT
4.0 mA
I
OUT
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low-Level
Output Voltage
V
IN
= V
IL
or V
IH
I
OUT
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IL
or V
IH
I
OUT
4.0 mA
I
OUT
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input
Leakage Current
V
IN
=V
CC
or GND
6.0
0.1
1.0
1.0
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
I
OUT
=0
A
6.0
8.0
80
160
A
IN74HC165
231
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
C
to
-55
C
85
C
125
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock (or Clock
Inhibit) to Q
H
or Q
H
(Figures 1 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PLH
, t
PHL
Maximum Propagation Delay ,
SerialShift./.Parallel Load to Q
H
or Q
H
(Figures 2 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Input H to Q
H
or
Q
H
(Figures 3 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
Typical @25
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
85
pF
IN74HC165
232
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
C to
-55
C
85
C
125
C
Unit
t
SU
Minimum Setup Time, Parallel
Data Inputs to Serial
Shift/Parallel Load (Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
SU
Minimum Setup Time, Input
S
A
to Clock (or Clock Inhibit)
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
SU
Minimum Setup Time, Serial
Shift/Parallel Load to Clock
(or Clock Inhibit) (Figure 6)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
SU
Minimum Setup Time, Clock
to Clock Inhibit (Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time, Serial
Shift/Parallel Load to Parallel
Data Inputs (Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
h
Minimum Hold Time, Clock
(or Clock Inhibit) to Input S
A
(Figure 5)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
h
Minimum Hold Time, Clock
(or Clock Inhibit) to Serial
Shift/Parallel Load (Figure 6)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
rec
Minimum Recovery Time,
Clock to Clock Inhibit
(Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
w
Minimum Pulse Width, Clock
(or Clock Inhibit) (Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
w
Minimum Pulse Width, Serial
Shift/Parallel Load (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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