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Электронный компонент: IN74HC240A

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IN74HC240A
1
O
CTAL
3-S
TATE
I
NVERTING
B
UFFER
/L
INE
D
RIVER
/L
INE
R
ECEIVER
High-Performance Silicon-Gate CMOS
The IN74HC240A is identical in pinout to the LS/ALS240. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
This octal inverting buffer/line driver/line receiver is designed
to be used with 3-state memory address drivers, clock drivers,
and other bus-oriented systems. The device has inverting
outputs and two active-low output enables.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC240AN Plastic
IN74HC240ADW SOIC
T
A
= -55
to 125 C for all
packages
FUNCTION TABLE
Inputs Outputs
Enable A,
Enable B
A,B YA,YB
L L H
L H L
H X Z
X = don't care
Z = high impedance
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
PIN ASSIGNMENT
IN74HC240A
2
MAXIMUM RATINGS
*
Symbol Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
35
mA
I
CC
DC Supply Current, V
CC
and GND Pins
75
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10
Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65 to 125C
SOIC Package: : - 7 mW/
C from 65 to 125C

RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to
GND)
0 V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure
1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns


This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, V
IN
and
V
OUT
should be constrained to the range GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
V
CC
). Unused outputs must be left open.
IN74HC240A
3
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
V
CC
Guaranteed
Limit
Symbol Parameter
Test
Conditions
V
25
C to
-55
C
85
C
125
C
Unit
V
IH
Minimum
High-
Level Input
Voltage
V
OUT
=0.1 V
I
OUT
20 A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low -
Level Input
Voltage
V
OUT
= V
CC
-0.1 V
I
OUT
20 A
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum
High-
Level Output
Voltage
V
IN
= V
IL
I
OUT
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
=V
IL
I
OUT
6.0 mA
I
OUT
7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum
Low-
Level Output
Voltage
V
IN
=V
IH
I
OUT
20 A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
I
OUT
6.0 mA
I
OUT
7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum
Input
Leakage Current
V
IN
=V
CC
or GND
6.0
0.1
1.0 1.0
A
I
OZ
Maximum
three
State Leakage
Current
Output in High-
Impedance State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND
6.0
0.5
5.0 10.
0
A
I
CC
Maximum
Quiescent Supply
Current
(per Package)
V
IN
=V
CC
or GND
I
OUT
=0
A
6.0 4.0 40
160
A
IN74HC240A
4
AC ELECTRICAL CHARACTERISTICS(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25
C
to
-55
C
85C 125
C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, A to YA or
B to YB (Figures 1 and 3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output
Enable to YA or YB (Figures 2 and 4)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
t
PZH
,
t
PZL
Maximum Propagation Delay, Output
Enable to YA or YB (Figures 2 and 4)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any
Output
(Figures 1 and 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
C
OUT
Maximum
Three-State
Output
Capacitance
(Output in High-Impedance State)
- 15 15 15 pF
Power Dissipation Capacitance (Per
Transceiver Channel)
Typical @25
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic
power consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
32 pF

Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
IN74HC240A
5
Figure 3. Test Circuit
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/8 of the Device)