TECHNICAL DATA
1
INTEGRAL
Quad 2-Input NAND Gate
The IN74LV00 is low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT00A.
The IN74LV00 provides the 2-Input NAND function.
Optimized for Low Voltage applications: 1.2 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Low Input Current
IN74LV00
ORDERING INFORMATION
IN74LV00N Plastic
IN74LV00D SOIC
IZ74LV00 Chip
T
A
= -40
? 125
C for all packages
LOGIC DIAGRAM
02
1A
1B
1Y
01
03
05
2A
2B
2Y
04
06
10
3A
3B
3Y
09
08
13
4A
4B
4Y
12
11
PIN 14 =V
CC
PIN 7 = GND
FUNCTION TABLE
Input
Output
A
B
B
*
A
Y
=
L
L
H
L
H
H
H
L
H
H
H
L
H - high level
L - low level
PIN ASSIGNMENT
IN74LV00
2
INTEGRAL
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC supply voltage (Referenced to GND)
-0.5
+5.0
V
I
IK
*
1
DC input diode current
20
mA
I
OK
*
2
DC output diode current
50
mA
I
O
*
3
DC output source or sink current
-bus driver outputs
25
mA
I
CC
DC V
CC
current for types with
- bus driver outputs
50
mA
I
GND
DC GND current for types with
- bus driver outputs
50
mA
P
D
Power dissipation per package, plastic DIP+
SOIC package+
750
500
mW
Tstg
Storage temperature
-65
+150
C
T
L
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/
C from 70
to 125
C
SOIC Package: : - 8 mW/
C from 70
to 125
C
*
1
: V
I
<
-0.5 or V
I
>
V
CC
+0.5V
*
2
: Vo
<
-0.5 or Vo
>
V
CC
+0.5V
*
3
: -0.5V
<
Vo
<
V
CC
+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
1.2
3.6
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-40
+125
C
t
r
, t
f
Input Rise and Fall Time
V
CC
=1.2 V
V
CC
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
0
0
0
0
1000
700
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND
(V
IN
or
V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
IN74LV00
3
INTEGRAL
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
,
Guaranteed Limit
V
25
C
-40
C
85
C
-40
C
125
C
Symbol
Parameter
Test Conditions
min
max
min
max
min
max
Unit
V
IH
High-Level Input
Voltage
1.2
2.0
3.0
3.6
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
V
V
IL
Low -Level Input
Voltage
1.2
2.0
3.0
3.6
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
V
V
I
= V
IL
or V
IH
I
O
= -50
1.2
2.0
3.0
3.6
1.1
1.92
2.92
3.52
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
V
V
OH
High-Level Output
Voltage
V
I
= V
IL
or V
IH
I
O
= -6.0 m
3.0
2.48
-
2.34
-
2.20
-
V
V
I
= V
IL
or V
IH
I
O
= 50
1.2
2.0
3.0
3.6
-
-
-
-
0.09
0.09
0.09
0.09
-
-
-
-
0.1
0.1
0.1
0.1
-
-
-
-
0.1
0.1
0.1
0.1
V
V
OL
Low-Level Output
Voltage
V
I
= V
IL
or V
IH
I
O
= 6.0 m
3.0
-
0.33
-
0.4
-
0.5
V
I
IL
Low-Level Input
Leakage Current
V
I
= 0 V
3.6
-
-0.1
-
-1.0
-
-1.0
A
I
I
High-Level Input
Leakage Current
V
I
= V
CC
3.6
-
0.1
-
1.0
-
1.0
A
I
Quiescent Supply
Current
(per Package)
V
I
= 0 or V
CC
I
O
= 0
3.6
-
2.0
-
20
-
40
A
IN74LV00
4
INTEGRAL
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
LH
= t
HL
= 6.0 ns, V
IL
=0V, V
IH
=V
CC
)
V
CC
Guaranteed Limit
V
25
C
-40
C ? 85
C
-40
C ? 125
C
Symbol
Parameter
min
max
min
max
min
max
Unit
t
THL,
(t
TLH
)
Output Transition
Time, Any Output
(Figure 1)
1.2
2.0
*
-
-
60
16
10
-
-
-
75
20
13
-
-
-
90
24
15
ns
t
PHL,
(t
PLH
)
Propagation Delay,
Input A to Output Y
(Figure 1)
1.2
2.0
*
-
-
-
135
23
14
-
-
-
405
28
18
-
-
-
405
34
21
C
I
Input Capacitance
3.0
-
7.0
-
-
-
-
pF
=25
, V
I
=0V?V
CC
pF
C
PD
Power Dissipation Capacitance (Per Inverter)
44
* - V
CC
= (3.30.3) V
Used to determine the no-load dynamic power consumption:
P
D
= C
PD
V
CC
2
f
I
+ ?(C
L
V
CC
2
fo), f
I
-input frequency, fo- output frequency (MHz)
?(C
L
V
CC
2
fo) - sum of the outputs
Figure 1. Switching Waveforms
Figure 2. Test Circuit
0.1
0.1
0.1
0.1
0.9
0.9
0.9
0.9
V
1
t
P LH
t
HL
t
THL
t
PHL
t
LH
t
TLH
V
1
V = 0.5 V
1
CC
Input , B
Output Y
GND
GND
V
CC
V
CC
V
1
V
1
PULSE
GENERATOR
DEVICE
UNDER
TEST
V
CC
V
I
V
O
C
L
R
L
R
T
Termination resistance R
T
-
should be equal to Z
OUT
pulse
generators
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