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TECHNICAL DATA
1
INTEGRAL
Octal D Flip-Flop with Common Clock and Reset
The IN74LV273 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT273.
The IN74LV273 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common clock (CP) and master
reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The
state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Qn) of the flip-
flop. All outputs will be forced LOW independently of clock or data
inputs by a LOW voltage level on the MR input. The device is useful for
applications where the true output only is required and the clock and
master reset are common to all storage elements.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
Supply voltage range: 1.2 to 5.5 V
Low input current: 1.0
; 0.1
at = 25
High Noise Immunity Characteristic of CMOS Devices
IN74LV273
N SUFFIX
PLASTIC DIP
DW SUFFIX
SO
1
20
1
20
ORDERING INFORMATION
IN74LV273N
Plastic DIP
IN74LV273DW
SOIC
IZ74LV273
chip
T
A
= -40
to 125
C for all packages
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output
Reset
Clock
D
Q
L
X
X
L
H
H
H
H
L
L
H
L
X
no change
H
X
no change
H= high level
L = low level
X = don't care
Z = high impedance
PIN ASSIGNMENT
1
2
3
5
4
6
7
8
9
10
V CC
20
18
17
16
15
14
19
11
12
13
GND
RESET
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CLOCK
IN74LV273
2
INTEGRAL
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC supply voltage
-0.5 to +7.0
V
I
IK
*
1
Input diode current
20
mA
I
OK
*
2
Output diode current
50
mA
I
O
*
3
Output source or sink current
25
mA
I
CC
V
CC
current
50
mA
I
GND
GND current
50
mA
P
D
Power dissipation per package:
Plastic DIP *
4
SO *
4
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO
Package) from Case for 4 Seconds
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V.
*
2
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V.
*
3
-0.5 V < V
O
< V
CC
+ 0.5 V.
*
4
Derating - Plastic DIP: - 12 mW/
C from 70
to 125
C
SO Package: - 8 mW/
C from 70
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage
1.2
5.5
V
V
I
DC Input Voltage
0
V
CC
V
V
O
DC Output Voltage
0
V
CC
V
T
A
Operating Temperature, All Package Types
-40
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
0 V
V
CC
2.0 V
2.0 V
V
CC
2.7 V
2.7 V
V
CC
3.6 V
3.6 V
V
CC
5.5 V
0
0
0
0
500
200
100
50
ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND
(V
IN
or
V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
IN74LV273
3
INTEGRAL
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Test
V
CC
Guaranteed Limit
Symbol Parameter
conditions
V
25
C
-40
C
85
C
125
C
min
max
min
max
min
max
min
max
Unit
V
IH
HIGH level
input
voltage
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
V
V
IL
LOW level
output
voltage
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
V
V
OH
HIGH level
output
voltage
V
I
= V
IH
or V
IL
I
O
= -100
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.05
1.85
2.55
2.85
3.45
4.35
5.35
-
-
-
-
-
-
-
1.05
1.85
2.55
2.85
3.45
4.35
5.35
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
V
V
I
= V
IH
or V
IL
I
O
= -6 m
3.0
2.48
-
2.48
-
2.40
-
2.20
-
V
V
I
= V
IH
or V
IL
I
O
= -12 m
4.5
3.70
-
3.70
-
3.60
-
3.50
-
V
V
OL
LOW level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
V
V
I
= V
IH
or V
IL
I
O
= 6 m
3.0
-
0.33
-
0.33
-
0.40
-
0.50
V
V
I
= V
IH
or V
IL
I
O
= 12 m
4.5
-
0.40
-
0.40
-
0.55
-
0.65
V
I
I
Input
current
V
I
= V
CC
or 0 V
5.5
-
0.1
-
0.1
-
1.0
-
1.0
I
CC
Supply
current
V
I
=V
CC
or 0 V
I
O
= 0
5.5
-
8.0
-
8.0
-
80
-
160
I
CC1
Additional
supply
current per
input
V
I
= V
CC
- 0.6V
2.7
3.6
-
0.2
-
0.2
-
0.5
0.85
mA
IN74LV273
4
INTEGRAL
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
r
=t
f
=2.5 ns)
Test
V
CC
Guaranteed Limit
Symbol
Parameter
conditions
V
-40
C to
25
C
85
C
125
C
Unit
min
max
min
max
min
max
t
PHL,
t
PLH
Propagation delay , Clock
to Q
V
I
= 0 V or V
1
Figures 1,4
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
150
30
22
17
14
-
-
-
-
-
150
32
24
19
16
-
-
-
-
-
150
41
30
24
20
ns
t
PHL
Propagation delay , Reset
to Q
V
I
= 0 V or V
1
Figures 2,4
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
160
40
30
23
19
-
-
-
-
-
160
44
33
26
22
-
-
-
-
-
160
56
41
33
28
ns
C
I
Input capacitance
5.0
-
6.0*
-
-
-
-
pF
C
PD
Power dissipation
capacitance (per flip-flop)
V
I
= 0 V or V
CC
5.5
-
40*
-
-
-
-
pF
* T = 25
o
C
TIMING REQUIREMENTS
(C
L
=50 pF, t
r
=t
f
=2.5 ns)
Test
V
CC
Guaranteed Limit
Symbol
Parameter
conditions
V
-40
C to
25
C
85
C
125
C
Unit
min
max
min
max
min
max
t
w
Pulse Width, Clock (low or
high), Reset (low)
V
I
= 0 V or V
1
Figures 1,2,4
1.2
2.0
2.7
3.0
4.5
60
28
21
16
12
-
-
-
-
-
70
34
25
20
16
-
-
-
-
-
80
41
30
24
20
-
-
-
-
-
ns
t
su
Setup Time, Data to Clock V
I
= 0 V or V
1
Figures 3,4
1.2
2.0
2.7
3.0
4.5
40
18
13
11
9
-
-
-
-
-
50
22
16
13
11
-
-
-
-
-
60
26
19
15
13
-
-
-
-
-
ns
t
rem
Removal Time, Reset to
Clock
V
I
= 0 V or V
1
Figures 2,4
1.2
2.0
2.7
3.0
4.5
5
5
5
5
5
-
-
-
-
-
5
5
5
5
5
-
-
-
-
-
5
5
5
5
5
-
-
-
-
-
ns
t
h
Hold Time, Clock to Data
V
I
= 0 V or V
1
Figures 3,4
1.2
2.0
2.7
3.0
4.5
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
ns
IN74LV273
5
INTEGRAL
f
c
Clock Frequency
V
I
= 0 V or V
1
Figures 1,4
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
2
17
23
30
32
-
-
-
-
-
1
14
19
24
27
-
-
-
-
-
1
12
16
20
24
MHz


V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms