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TECHNICAL DATA
1
INTEGRAL
Octal D-type flip-flop;
positive edge-trigger (3-State)
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip-flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for oriented
applications. A clock (CP) and an output enable (OE) input are common
to all flip-flops. The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements on the LOW-
to-HIGH CP transition. When OE is LOW, the contents of the eight flip-
flops are available at the outputs. When OE is HIGH, the outputs go to
the high impedance OFF-state. Operation of the OE input does not affect
the state of the flip-flops.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
Supply voltage range: 1.0 to 5.5 V
Low input current: 1.0
; 0.1
at = 25
High Noise Immunity Characteristic of CMOS Devices
IN74LV574
N SUFFIX
PLASTIC DIP
DW SUFFIX
SO
1
20
1
20
ORDERING INFORMATION
IN74LV574N
Plastic DIP
IN74LV574DW
SOIC
IZ74LV574
chip
T
A
= -40
to 125
C for all packages
FUNCTION TABLE
Inputs
Output
Output
Enable
Clock
D
Q
L
H
H
L
L
L
L
L,H,
X
no
change
H
X
X
Z
H= high level
L = low level
X = don't care
Z = high impedance
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
PIN ASSIGNMENT
IN74LV574
2
INTEGRAL
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC supply voltage
-0.5 to +7.0
V
I
IK
*
1
Input diode current
20
mA
I
OK
*
2
Output diode current
50
mA
I
O
*
3
Output source or sink current
35
mA
I
CC
V
CC
current
70
mA
I
GND
GND current
70
mA
P
D
Power dissipation per package:
Plastic DIP *
4
SO *
4
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO
Package) from Case for 4 Seconds
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V.
*
2
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V.
*
3
-0.5 V < V
O
< V
CC
+ 0.5 V.
*
4
Derating - Plastic DIP: - 12 mW/
C from 70
to 125
C
SO Package: : - 8 mW/
C from 70
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage
1.0
5.5
V
V
I
DC Input Voltage
0
V
CC
V
V
O
DC Output Voltage
0
V
CC
V
T
A
Operating Temperature, All Package Types
-40
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
0 V
V
CC
2.0 V
2.0 V
V
CC
2.7 V
2.7 V
V
CC
3.6 V
3.6 V
V
CC
5.5 V
0
0
0
0
500
200
100
50
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND
(V
IN
or
V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
IN74LV574
3
INTEGRAL
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Test
V
CC
Guaranteed Limit
Symbol Parameter
conditions
V
25
C
-40
C
85
C
125
C
min
max
min
max
min
max
min
max
Unit
V
IH
HIGH level
input
voltage
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
V
V
IL
LOW level
output
voltage
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
V
V
OH
HIGH level
output
voltage
V
I
= V
IH
or V
IL
I
O
= -100
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.05
1.85
2.55
2.85
3.45
4.35
5.35
-
-
-
-
-
-
-
1.05
1.85
2.55
2.85
3.45
4.35
5.35
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
V
V
I
= V
IH
or V
IL
I
O
= -8 m
3.0
2.48
-
2.48
-
2.40
-
2.20
-
V
V
I
= V
IH
or V
IL
I
O
= -16 m
4.5
3.70
-
3.70
-
3.60
-
3.50
-
V
V
OL
LOW level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
V
V
I
= V
IH
or V
IL
I
O
= 8 m
3.0
-
0.33
-
0.33
-
0.40
-
0.50
V
V
I
= V
IH
or V
IL
I
O
= 16 m
4.5
-
0.40
-
0.40
-
0.55
-
0.65
V
I
I
Input
current
V
I
= V
CC
or 0 V
5.5
-
0.1
-
0.1
-
1.0
-
1.0
I
CC
Supply
current
V
I
=V
CC
or 0 V
I
O
= 0
5.5
-
8.0
-
8.0
-
20
-
160
I
CC1
Additional
supply
current per
input
V
I
= V
CC
- 0.6V
2.7
3.6
-
0.2
-
0.2
-
0.5
0.85
mA
IN74LV574
4
INTEGRAL
I
OZ
Three state
leakage
current
3-state output
V
I
(11) = V
IH
V
O
=V
CC
or 0 V
5.5
-
0.5
-
0.5
-
5
-
10
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
r
=t
f
=2.5 ns)
Test
V
CC
Guaranteed Limit
Symbol
Parameter
conditions
V
-40
C to
25
C
85
C
125
C
Unit
min
max
min
max
min
max
t
PHL,
t
PLH
Propagation delay , Clock
to Q
V
I
= 0 V or V
1
Figures 1,3
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
160
26
20
16
14
-
-
-
-
-
170
34
25
20
17
-
-
-
-
-
200
43
31
25
21
ns
t
PHZ,
t
PLZ
Propagation delay, OE to
Q
V
I
= 0 V or V
1
Figures 2,4
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
160
31
23
20
17
-
-
-
-
-
170
39
29
24
20
-
-
-
-
-
200
48
36
29
24
ns
t
PZH,
t
PZL
Propagation delay, OE to
Q
V
I
= 0 V or V
1
Figures 2,4
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
140
26
20
16
14
-
-
-
-
-
160
34
25
20
17
-
-
-
-
-
180
43
31
25
21
ns
C
I
Input capacitance
5.5
-
7.0*
-
-
-
-
pF
C
PD
Power dissipation
capacitance (per flip-flop)
V
I
= 0 V or V
CC
5.5
-
50*
-
-
-
-
pF
* T = 25
o
C
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 1. Test Circuit
Figure 2. Test Circuit
TIMING REQUIREMENTS
(C
L
=50 pF, t
r
=t
f
=2.5 ns)
DEVICE
UNDER
TEST
OUTPUT
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
1 k
C
L
*
TEST POINT
Connect to V
CC
when
testing t
PLZ
and t
PZL
Connect to GND
when
testing t
PHZ
and t
PZH
IN74LV574
5
INTEGRAL
Test
V
CC
Guaranteed Limit
Symbol
Parameter
conditions
V
-40
C to
25
C
85
C
125
C
Unit
min
max
min
max
min
max
t
w
Pulse Width, Clock (high) V
I
= 0 V or V
1
Figures 1,3
1.2
2.0
2.7
3.0
4.5
120
29
21
17
15
-
-
-
-
-
34
25
20
-
-
-
41
30
24
-
-
-
ns
t
su
Setup Time, Data to Clock V
I
= 0 V or V
1
Figures 1,5
1.2
2.0
2.7
3.0
4.5
40
19
14
11
9
-
-
-
-
-
22
16
13
-
-
-
26
19
15
-
-
-
ns
t
h
Hold Time, Clock to Data
V
I
= 0 V or V
1
Figures 1,5
1.2
2.0
2.7
3.0
5
5
5
5
-
-
-
-
5
5
5
5
-
-
-
-
5
5
5
5
-
-
-
-
ns
f
c
Clock Frequency
V
I
= 0 V or V
1
Figures 1,3
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
2
17
21
27
31
-
-
-
15
19
24
-
-
-
12
16
20
MHz
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
Figure 3. Switching Waveforms