TECHNICAL DATA
1
Octal 3-State Inverting
Bus Transceiver
The 74LV640 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT640.
The 74LV640 provides six inverting buffers with Schmitt-trigger
action.
Wide Operating Voltage: 1.2 to 3.6 V
Optimized for Low Voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
=2.7 V and V
CC
=3.6 V
Low input current
IN74LV640
ORDERING INFORMATION
IN74LV640N Plastic
IN74LV640D SOIC
IZ74LV640 Chip
T
A
= -40
to 125
C for all packages
PIN ASSIGNMENT
640
DIR
01
A
8
02
A
1
03
A
2
04
A
3
05
A
4
06
A
5
07
A
6
08
A
7
09
GND
10
20
19
18
17
16
15
14
13
12
11
B
8
B
1
B
2
B
3
B
4
B
5
B
6
B
7
OE
V
CC
LOGIC DIAGRAM
18
B
8
03
17
B
1
A
1
04
16
B
2
A
2
05
15
B
3
A
3
06
14
B
4
A
4
07
13
B
5
A
5
08
12
B
6
A
6
09
11
B
7
A
7
01
DIR
02
A
8
19
OE
PIN 20=V
CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Inputs/Outputs
OE
DIR
L
L
A=B
input
L
H
input
B=A
H
X
Z
Z
IN74LV640
2
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC supply voltage (Referenced to GND)
-0.5
+5.0
V
I
IK
*
1
DC input diode current
20
mA
I
OK
*
2
DC output diode current
50
mA
Io*
3
DC output source or sink current
-bus driver outputs
35
mA
I
GND
DC GND current for types with
- bus driver outputs
70
mA
I
CC
DC V
CC
current for types with
- bus driver outputs
70
mA
P
D
Power dissipation per paskade, plastic DIP+
SOIC package+
750
500
mW
Tstg
Storage temperature
-65
+150
C
T
L
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/
C from 65
to 125
C
SOIC Package: : - 8 mW/
C from 65
to 125
C
*
1
: V
I
<
-0.5V or V
I
>
V
CC
+0.5V
*
2
: Vo
<
-0.5V or Vo
>
V
CC
+0.5V
*
3
: -0.5V
<
Vo
<
V
CC
+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
1.2
3.6
V
V
IN,
V
OUT
DC Input Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-40
+125
C
t
LH
, t
HL
Input Rise and Fall Time
V
CC
=1.2 V
V
CC
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
0
1000
700
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
IN74LV640
3
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
25
C
-40
C
85
C
-40
C
125
C
Symbol
Parameter
Test
Conditions
V
CC
V
min
max
min
max
min
max
Unit
V
IH
High-Level
Input Voltage
V
O
= V
CC
-
0.1 V
1.2
2.0
3.0
3.6
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
V
V
IL
Low -Level
Input Voltage
1.2
2.0
3.0
3.6
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
V
V
I
= V
IH
-or
V
IL
I
O
= -50
A
1.2
2.0
3.0
3.6
1.1
1.92
2.92
3.52
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
V
OH
High-Level
Output Voltage
V
I
= V
IH
-or
V
IL
I
O
= -8.0
mA
3.0
2.48
-
2.34
-
2.20
-
V
V
I
= V
IH
-or
V
IL
I
O
= 50
A
1.2
2.0
3.0
3.6
-
-
-
-
0.09
0.09
0.09
0.09
-
-
-
-
0.1
0.1
0.1
0.09
-
-
-
-
0.1
0.1
0.1
0.09
V
OL
Low-Level
Output Voltage
V
I
= V
IH
-or
V
IL
I
O
= 8.0 mA
3.0
-
0.33
-
0.40
-
0.50
V
I
IL
Low-Level Input
Leakage Current
V
I
=0 V
*
-
-0.1
-
-1.0
-
-1.0
A
I
IH
High-Level
Input Leakage
Current
V
I
= V
*
-
0.1
-
1.0
-
1.0
A
I
OZ
Maximum Three-
State Leakage
Current
V
I
= V
IL
or
V
IH
V
O
=V
CC
or
GND
1.2
*
-
0.5
-
5.0
-
10
A
I
CC
Quiescent
Supply Current
(per Package)
V
I
=0 V or
V
I
O
= 0
A
*
-
8.0
-
80.0
-
180.0
A
.
IN74LV640
4
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
LH
=t
HL
= 6.0 ns, R
L
=1 k? )
Guaranteed Limit
25
C
-40
C
85
C
-40
C
125
C
Symbol
Parameter
Test
Conditions
V
CC
V
min
max
min
max
min
max
Unit
t
PLH
, t
PHL
Propagation
Delay, A to B , B
to A
V
IL
=0 V
V
IH
=V
CC
t
LH
= t
HL
=6.0 ns
L
= 50 pF
1.2
2.0
*
-
-
-
100
23
14
-
-
-
125
28
18
-
-
-
140
34
21
ns
t
PLZ
, t
PHZ
Propagation
Delay , Direction
or Output
Enable to A or B
V
IL
=0 V
V
IH
=V
CC
t
LH
= t
HL
=6.0 ns
L
= 50 pF
1.2
2.0
*
-
-
-
120
30
20
-
-
-
140
37
24
-
-
-
160
43
28
ns
t
PZL
, t
PZH
Propagation
Delay , Direction
or Output
Enable to A or B
V
IL
=0 V
V
IH
=V
CC
t
LH
= t
HL
=6.0 ns
L
= 50 pF
1.2
2.0
*
-
-
-
120
28
17
-
-
-
140
35
21
-
-
-
160
43
26
ns
t
TLH
, t
THL
Output
Transition Time,
Any Output
V
IL
=0 V
V
IH
=V
CC
t
LH
= t
HL
=6.0 ns
L
= 50 pF
1.2
2.0
*
-
-
-
60
16
10
-
-
-
75
20
13
-
-
-
90
24
15
ns
C
I
Input
Capacitance (Pin
1 or Pin 19)
3.0
-
7.0
-
-
-
-
pF
C
I/O
Input
Capacitance (Pin
2-9 or Pin 11-18)
3.0
-
20.0
-
-
-
-
pF
C
PD
V
I
=0 V or
V
-
50
-
-
-
-
pF
* - V
CC
=3.3
0.3V
Figure 1. Switching Waveforms
Figure 2. Test Circuit
0.1
0.1
0.1
0.1
0.9
0.9
0.9
0.9
V
1
V
1
V
1
V
1
t
PHL
t
THL
t
TLH
t
HL
t
PLH
t
LH
B (A)
GND
V
CC
V
CC
PULSE
GENERATOR
DEVICE
UNDER
TEST
V
C C
V
I
V
O
C
L
R
L
R
T
Termination resistance R
T
- should be
equal to Z
OUT
of pulse generators
IN74LV640
5
CHIP PAD DIAGRAM IZ74LV640
Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer)
Thickness of chip 0.46
0,02 mm
PAD LOCATION
Pad No
Symbol
X
Y
01
DIR
0.140
0.573
02
A1
0.140
0.315
03
A2
0.370
0.140
04
A3
0.790
0.140
05
A4
1.000
0.140
06
A5
1.200
0.140
07
A6
1.417
0.140
08
A7
1.833
0.140
09
A8
2.060
0.354
10
GND
2.060
0.760
11
B8
2.060
1.340
12
B7
2.060
1.520
13
B6
1.833
1.750
14
B5
1.415
1.750
15
B4
1.000
1.750
16
B3
0.790
1.750
17
B2
0.580
1.750
18
B1
0.370
1.750
19
OE
0.140
1.544
20
V
CC
0.140
1.375
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
1
.
9
9
+
0
.
0
3
Chip marking
LV640
(X=2.010;Y=1.810)
2.30 0.03
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