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Электронный компонент: IN74LV74N

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TECHNICAL DATA
1
INTEGRAL
Dual D-type flip-flop with set and reset;
positive-edge trigger
The IN74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The IN74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
D
) and (R
D
) inputs;
also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable one set-up time prior to the LOW-to-
HIGH clock transition, for predictable operation. Schmitt-trigger action in
the clock input makes the circuit highly tolerant to slower clock rise and
fall times.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
Supply voltage range: 1.2 to 3.6 V
Low input current: 1.0
; 0.1
at = 25
High Noise Immunity Characteristic of CMOS Devices
IN74LV74
1
14
1
14
N SUFFIX
PLASTIC
D SUFFIX
SOIC
ORDERING INFORMATION
IN74LV74N
Plastic DIP
IN74LV74D
SOIC
IZ74LV74
chip
T
A
= -40
to 125
C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Outputs
Set
Reset
Clock
Data
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*
H*
H
H
H
H
L
H
H
L
L
H
H
H
L
X
No Change
H
H
H
X
No Change
H
H
X
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
H= high level L = low level
X = don't care Z = high impedance
1
2
3
5
4
6
7
V CC
14
13
12
11
10
8
9
GND
RESET 1
DATA 1
SET 1
Q1
Q1
RESET 2
DATA2
CLOCK 2
SET 2
Q2
Q2
CLOCK 1
IN74LV74
2
INTEGRAL
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC supply voltage
-0.5 to +5.0
V
I
IK
*
1
Input diode current
20
mA
I
OK
*
2
Output diode current
50
mA
I
O
*
3
Output source or sink current
35
mA
I
CC
V
CC
current
70
mA
I
GND
GND current
70
mA
P
D
Power dissipation per package:
Plastic DIP *
4
SO *
4
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO
Package) from Case for 4 Seconds
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V.
*
2
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V.
*
3
-0.5 V < V
O
< V
CC
+ 0.5 V.
*
4
Derating - Plastic DIP: - 12 mW/
C from 70
to 125
C
SO Package: - 8 mW/
C from 65
to 125
C

RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage
1.2
3.6
V
V
I
DC Input Voltage
0
V
CC
V
V
O
DC Output Voltage
0
V
CC
V
T
A
Operating Temperature, All Package Types
-40
+125
C
t
r
, t
f
Input Rise and Fall Time except for Schmitt-
trigger inputs (Figure 1)
V
CC
=1.2 V
V
CC
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
0
0
0
0
1000
700
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND
(V
IN
or
V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
IN74LV74
3
INTEGRAL
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Test
V
CC
Guaranteed Limit
Symbol
Parameter
conditions
V
25
C
-40
C to 85
C
125
C
Unit
min
max
min
max
min
max
V
IH
HIGH level input
voltage
1.2
2.0
3.0
3.6
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
V
V
IL
LOW level output
voltage
1.2
2.0
3.0
3.6
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
V
V
OH
HIGH level output
voltage
V
I
= V
IH
or V
IL
I
O
= -50
1.2
2.0
3.0
3.6
1.1
1.92
2.92
3.52
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
V
V
I
= V
IH
or V
IL
I
O
= -6m
3.0
2.48
-
2.34
-
2.20
-
V
V
OL
LOW level output
voltage
V
I
= V
IH
or V
IL
I
O
= 50
1.2
2.0
3.0
3.6
-
-
-
-
0.09
0.09
0.09
0.09
-
-
-
-
0.1
0.1
0.1
0.1
-
-
-
-
0.1
0.1
0.1
0.1
V
V
I
= V
IH
or V
IL
I
O
= 6 m
3.0
-
0.33
-
0.4
-
0.5
V
I
I
Input current
V
I
= V
CC
or 0 V
*
-
0.1
-
1.0
-
1.0
I
CC
Supply current
V
I
=V
CC
or 0 V
I
O
= 0
*
-
4.0
-
40
-
80
* V
CC
= 3.3
0.3 V
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
r
=t
f
=6.0 ns)
Test
V
CC
Guaranteed Limit
Symbol
Parameter
conditions
V
25
C
-40
C to
85
C
125
C
Unit
min max
min
max
min
max
t
PHL,
t
PLH
Propagation delay , Clock
to Q or Q
V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
*
-
-
-
140
45
28
-
-
-
160
56
35
-
-
-
180
67
42
ns
t
PHL,
t
PLH
Propagation delay , Set to
Q or Q
V
I
= 0 V or V
CC
Figures 2,3
1.2
2.0
*
-
-
-
150
44
27
-
-
-
170
54
34
-
-
-
190
65
41
ns
t
PHL,
t
PLH
Propagation delay , Reset
to Q or Q
V
I
= 0 V or V
CC
Figures 2,3
1.2
2.0
*
-
-
-
160
47
29
-
-
-
180
58
37
-
-
-
200
70
44
ns
t
THL,
t
TLH
Output Transition Time,
Any Output
V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
*
-
-
-
90
20
15
-
-
-
110
25
19
-
-
-
130
30
23
ns
C
I
Input capacitance
3.0
-
7.0
-
-
-
-
pF
IN74LV74
4
INTEGRAL
C
PD
Power dissipation
capacitance (per flip-flop)
V
I
= 0 V or V
CC
-
48
-
-
-
-
pF
IN74LV74
5
INTEGRAL
TIMING REQUIREMENTS
(C
L
=50 pF, t
r
=t
f
=6.0 ns)
Test
V
CC
Guaranteed Limit
Symbol
Parameter
conditions
V
25
C
-40
C to 85
C
125
C
Unit
min
max
min
max
min
max
t
w
Puls e Width, Clock, Set or
Reset
V
I
= 0 V or V
CC
Figures 1,2,3
1.2
2.0
*
75
25
16
-
-
-
96
32
20
-
-
-
114
38
24
-
-
-
ns
t
su
Setup Time, Data to Clock V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
*
25
16
10
-
-
-
32
20
13
-
-
-
40
24
15
-
-
-
ns
t
rem
Removal Time, Set or
Reset to Clock
V
I
= 0 V or V
CC
Figures 2,3
1.2
2.0
*
18
9
6
-
-
-
24
12
8
-
-
-
30
15
9
-
-
-
ns
t
h
Hold Time, Clock to Data
V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
*
3
3
3
-
-
-
5
3
3
-
-
-
5
3
3
-
-
-
ns
f
c
Clock Frequency
V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
3.0
8
18
30
-
-
-
6
15
24
-
-
-
4
12
20
-
-
-
MHz
* V
CC
= 3.3
0.3 V

V
M
= 0.5
V
CC
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
Figure 1. Switching Waveforms