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Электронный компонент: IN82C55AN

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IN82C55AN
1
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
The Integral IN82C55AN is a high-performance, CHMOS version of the industry standard
IN82C55AN general purpose programmable I/O device which is designed for use with all
Intel and most other microprocessors. It provides 24 I/O pins which may be individually
programmed in 2 groups of 12 and used in 3 major modes of operation.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs
or outputs. In MODE 1, each group may be programmed to have 8 lines of input or output.
3 of the remaining 4 pins are used for handshaking and interrupt control signals. MODE 2
is a strobed bi-directional bus configuration.
FEATURES
Compatible with all Intel and Most Other Microprocessors
High Speed, Zero Wait State Operation with 8MHz 8086/88 and 80186/188
24 Programmable I/O Pins
Low Power CHMOS
Completely TTL Compatible
Control Word Read-Back Capability
Direct Bit Set/Reset Capability
2.5mA DC Drive Capability on all I/O Port Outputs
Available in 40-Pin DIP
Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
GROUP
A
CONTROL
DATA
BUS
BUFFER
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
GROUP
B
PORT
B
(8)
GROUP
B
PORT C
LOWER
(4)
GROUP
A
PORT C
UPPER
(4)
GROUP
A
PORT
A
(8)
PA
7
-PA
0
PC
7
-PC
4
PC
3
-PC
0
PB
7
-PB
0
D
7
-D
0
RD
RD
WR
CS
A
1
A
0
Reset
8 BIT
INTERNAL
DATA BUS
Figure 1
1.
2.
3.
4.
5.
6.
7.
8.
9.
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA
4
PA
5
PA
6
PA
7
WR
Reset
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
V
CC
PB
7
PB
6
PB
5
PB
4
PB
3
PA
3
PA
2
PA
1
PA
0
RD
CS
V
SS
A
1
A
0
PC
7
PC
6
PC
5
PC
4
PC
0
PC
1
PC
2
PC
3
PB
0
PB
1
PB
2
Figure 2
IN82C55AN
2
Symbol Pin
number
Type
Name and Function
PA
3-0
1-4
I/O
PORT A, PINS 0-3: Lower nibble of an 8-bit data output latch
buffer and an 8-bit data input latch.
RD
5
I
READ CONTROL: This input is low during CPU read
operations.
CS
6
I
CHIP SELECT: A low on this input enables the 82C55A to
respond to
RD
and
WR
signals RD and WR are ignored
otherwise.
GND 7
System
Ground.
A
1-0
8-9
I
ADDRESS: These input signals in conjunction
RD
and
WR
control the selection of one of the three ports or the control
word registers.
A
1
A
0
RD
WR
CS
Input Operation (Read)
0 0 0 1 0
Port A - Data Bus
0 1 0 1 0
Port B - Data Bus
1 0 0 1 0
Port C - Data Bus
1 1 0 1 0
Control Word - Data Bus
Output Operation (Write)
0 0 1 0 0
Data Bus - Port A
0 1 1 0 0
Data Bus - Port B
1 0 1 0 0
Data Bus - Port C
1 1 1 0 0
Data Bus - Control
Disable
Function
x x x x 1
Data Bus-3-State
x
x
1
1
0
Data Bus-3-State
PC
7-4
10-13
I/O
PORT C, PINS 4-7: Upper nibble of an 8-bit data output
latch/buffer and an 8-bit data input buffer (no latch for input).
This port can be divided into two 4-bit ports under the mode
control. Each 4-bit port contains a 4-bit latch and it can be used
for the control signal outputs and status signal inputs in
conjunction with ports A and B.
PC
0-3
14-17
I/O
PORT C, PINS 0-3: Lower nibble of Port C.
PB
0-7
18-25
I/O
PORT B, PINS 0-7: An 8-bit data output latch/buffer and an 8-
bit data input buffer
VCC
26
SYSTEM POWER: +5V Power Supply
D
7-0
27-34
I/O
DATA BUS: Bi-directional, tri-state data bus lines, connected to
system data bus
RESET
35
I
RESET: A high on this input clears the control register and all
ports are set to the input mode
WR
36
I
WRITE CONTROL: This input is low during CPU write
operations
PA
7-4
37-40
I/O
PORT A PINS 4-7: Upper nibble of an 8-bit data output
latch/buffer and an 8-bit data input latch
IN82C55AN
3
IN82C55AN FUNCTIONAL DESCRIPTION
General
The IN82C55AN is a programmable peripheral interface device designed for use in Intel microcomputer
systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the
microcomputer system bus. The functional configuration of the IN82C55AN is programmed by the system
software so that normally no external logic is necessary to interface peripheral devices or structures.
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to interface the IN82C55AN to the system data bus. Data is
transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control
words and status information are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfers of both Data and Control or
Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to
both of the Control Groups.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU
"outputs" a control word to the IN82C55AN. The control word contains information such as "mode", "bit set",
"bit reset", etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group
A and Group B) accepts "commands" from the Read/Write Control Logic, receives "control words" from the
internal data bus and issues the proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as shown in the address decode table in the pin
descriptions. Figure 6 shows the control word format for both Read and Write operations. When the control
word is read, bit D7 will always be a logic "1", as this implies control word mode information.
Ports A, B, and C
The IN82C55AN contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional
characteristics by the system software but each has its own special features or "personality" to further
enhance the power and flexibility of the IN82C55AN.
Port A. One 8-bit data output latch/buffer and one 8-bit input latch/buffer. Both "pull-up" and "pull-down" bus
hold devices are present on Port A.
Port B. One 8-bit data input/output latch/buffer. Only "pull-up" bus hold devices are present on Port B.
Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used
for the control signal outputs and status signal inputs in conjunction with ports A and B. Only "pull-up" bus
hold devices are present on Port C.
See Figure 4 for the bus-hold circuit configuration for Port A, B, and C.
IN82C55AN
4
GROUP
A
CONTROL
DATA
BUS
BUFFER
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
GROUP
B
PORT
B
(8)
GROUP
B
PORT C
LOWER
(4)
GROUP
A
PORT C
UPPER
(4)
GROUP
A
PORT
A
(8)
PA
7
-PA
0
PC
7
-PC
4
PC
3
-PC
0
PB
7
-PB
0
D
7
-D
0
RD
RD
WR
CS
A
1
A
0
Reset
8 BIT
INTERNAL
DATA BUS
Figure 3. IN82C55AN Block Diagram Showing Data Bus Buffer and Read Write Control Logic
Functions
RESET
INTERNAL
DATA IN
INTERNAL
DATA OUT
INTERNAL
DATA OUT
EXTERNAL
PORT A
PIN
RESET
INTERNAL
DATA OUT
VCC
P*
WR
EXTERNAL
PORT B,C
PIN
*NOTE:
Port pins loaded with more than 20pF capacitance may not have their logic level guaranteed following a hardware reset.
*
WR
Figure 4. Port A, B, C, Bus-hold Configuration
IN82C55AN
5
IN82C55AN OPERATIONAL DESCRIPTION
Mode Selection
There are three basic modes of operation that can be selected by the system software:
Mode 0 - Basic input/output
Mode 1 - Strobed Input/output
Mode 2 - Bi-directional Bus
When the reset input goes "high" all ports will be set to the input mode with all 24 port lines held at a logic
"one" level by the internal bus hold devices (see Figure 4 Note). After the reset is removed the IN82C55AN
can remain in the input mode with no additional initialization required. This eliminates the need for pullup or
pulldown devices in "all CMOS" designs. During the execution of the system program, any of the other
modes may be selected by using a single output instruction. This allows a single IN82C55AN to service a
variety of peripheral devices with a simple software maintenance routine.
The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as
required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be
reset whenever the mode is changed. Modes may be combined so that their functional definition can be
"tailored" to almost any I/O structure. For instance; Group B can be programmed in Mode 0 to monitor simple
switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a
keyboard or tape reader on an interrupt-driven basis.
ADRESS BUS
8
RD, WR
D7-D0
A0, A1
B
C
A
CONTROL BUS
DATA BUS
8
4
4
8
MODE 0
PB
7
-PB
0
PC
3
-PC
0
PC
7
-PC
4
PA
7
-PA
0
8
8
MODE 1
PB
7
-PB
0
CONTROL
OR I/O
CONTROL
OR I/O
PA
7
-PA
0
B
C
A
8
8
MODE 2
PB
7
-PB
0
I/O
CONTROL
PA
7
-PA
0
B
C
A
Figure 5. Basic Mode Definitions and Bus Interface