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Электронный компонент: IZ0065

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TECHNICAL DATA
1
IN T E G R A L
40 Channel Segment / Common Driver For Dot Matrix LCD
The IZ0065 is a LCD driver LSI which is fabricated by low power CMOS technology. Basically this LSI consists
of 20
2 bit bi-directional shift register, 20
2 bit data latch and 20
2 bit driver. This LSI can be used a common
or segment driver.
FEATURES
Display driving bias: static -1/5
Power supply voltage: +5V
10%, +3V
10%
Supply voltage for display: 0 ~ -5V(V
EE
)
Interface
FUNCTIONS
Dot matrix LCD driver with 40-channel output.
Selectable function to use common/segment drivers
simultaneously.
Input / Output signal
- output: 20
2 channel waveform for LCD driving
- input: - Serial display data and control pulse from
the controller LSI.
Bias voltage (V
1
-V
6
)
driver(cascade connection)
controller
Other IZ0065
IZ0066
KS0066
HD44780
SED1278
CMOS Process
Bare chip available
ABSOLUTE MAXIMUM RATING (Ta = 25
o
C)
Characteristic
Symbol
Value
Unit
Operating Voltage
V
DD
-0.3 ~ 7.0
V
Driver Supply Voltage
V
LCD
V
DD
- 13.5 ~ V
DD
+ 0.3
V
Input Voltage 1
V
IN1
- 0.3 ~ V
DD
+ 0.3
V
Input Voltage 2 (V
1
-V
6
)
V
IN2
V
DD
+ 0.3 ~ V
EE
- 0.3
V
Operating Temperature
T
OPR
-30 ~ +85
o
C
Storage Temperature
T
STG
-55 ~ +125
o
C
Voltage greater than above may damage to then circuit.
V
EE
: connect protection resistor (220
5%)
IZ0065
IZ0065
2
IN T E G R A L
ELECTRICAL CHARACTERISTICS
DC characteristics
(V
DD
=2.7~5.5V, V
DD
- V
EE
=3~13V, V
SS
=0V, Ta=-30 ~ +85
O
C )
Characteristic
Symbol
Test Condition
Min
Max
Unit
Applicable pin
Operating Current *
I
DD
f
CL2
=400KHz
-
1
mA
-
Supply Current *
I
EE
f
CL1
=1KHz
-
10
A
Input High Voltage
V
IH
-
0.7V
DD
V
DD
V
CL1, CL2, DL1,
DL2,
Input Low Voltage
V
IL
0
0.3V
DD
DR1, DR2,
Input Leakage Current
I
LKG
V
IN
=0-V
DD
-5
5
A
SHL1, SHL2, M,
FCS
Output High Voltage
V
OH
I
OH
= -0.4mA
V
DD
-
0.4
-
DL1, DL2, DR1,
DR2
Output Low Voltage
V
OL
I
OL
= +0.4mA
-
0.4
V
Voltage Descending
V
D1
I
ON
=0.1mA for one of
SC1-SC40
-
1.1
V(V
1
-V
6
),
SC(SC
1
-SC
40
)
V
D2
I
ON
=0.5mA for each
SC1-SC40
-
1.5
Leakage Current
I
V
V
IH=
V
DD
~ V
EE
(Output SC1-
SC40:floating)
-10
10
A
V
1
-V
6
* V
DD
-V
EE
=4V
AC characteristics
(V
DD
=2.7~5.5V, V
DD
- V
EE
=3~13V, V
SS
=0V, Ta=-30 ~ +85
O
C )
Characteristic
Symbol
Test Condition
Min
Max
Unit
Applicable pin
Data Shift Frequency
f
CL
-
-
400
KHz
CL2
Clock High Level Width
t
WCKH
-
800
-
CL1, CL2
Clock Low Level Width
t
WCKL
-
800
-
CL2
Clock Set-up Time
t
LS
from CL2 to CL1
500
-
t
LS
from CL1 to CL2
500
-
ns
CL1, CL2
Clock Rise/Fall Time
t
R
/t
F
-
-
200
Data Set-up Time
t
SU
-
300
-
DL1, DL2, DR1,
DR2,
Data Hold Time
t
DH
-
300
-
FLM
Data Delay Time
t
D
CL=15pF
-
500
DL1, DL2, DR1,
DR2
Input/Output current excluded; When input is at the intermediate level with CMOS, excessive current flows through
the input circuit to the power supply,To avoid this, input level must be fixed at H or L.
IZ0065
3
IN T E G R A L
BLOCK DIAGRAM
LCD DRIVER
DATA LATCH
(20 bit)
LCD DRIVER
DATA LATCH
(20 bit)
BIDIRECTIONAL
SHIFT REGISTER
(20bit)
BIDIRECTIONAL
SHIFT REGISTER
(20bit)
SW
CONTR
LOGIC
V
6
V
5
V
DD
Vss
V
EE
CL
2
CL
1
M
V
4
V
3
V
2
V
1
S
C
4
0
S
C
3
9
S
C
2
2
S
C
2
1
S
C
1
S
C
2
S
C
2
0
S
C
1
9
V
2
V
1
PART 2
PART 1
S
H
L
2
D
R
2
D
L
2
D
R
1
S
H
L
1
D
L
1
F
C
S
IZ0065
4
IN T E G R A L
PIN DESCRIPTION
PIN
INP/
OUTP
NAME
DESCRIPTION
INTER-
FACE
V
DD
(24)
Operating Voltage
For logical circuit (+5 V
10
%
, +3 V
10
%
)
Power
GND (34) Power
0 V (GND)
Supply
V
EE
(31)
Negative Supply
Voltage
For LCD driver circuit (-5 V)
V
1
V
2
(44,45)
Input
Bias Voltage
Bias voltage level for LCD drive (select level)
Power
SC
1



SC
20
Output
LCD driver
LCD driver output
LCD
V
3
V
4
(46,47)
Input PART 1 Bias Voltage
Bias voltage level for LCD drive (nonselect level)
Power
SHL1
Input
Data interface Selection of the shift direction of Part 1 shift register
V
DD
(41)
SHL1
DL1
DR1
or
V
DD
out
in
V
SS
V
SS
in
out
DL1,DR1
(35,36)
Input/
Output
Data input/output of Part 1 shift register
Controller
or
IZ0065
SC
21



SC
40
Output
LCD driver
LCD driver output
V
5
V
6
(48,49)
Input PART 2 Bias Voltage
Bias voltage level for LCD drive (nonselect level)
Power
SHL2
Input
Data interface Selection of the shift direction of Part 2 shift register
V
DD
(42)
SHL2
DL2
DR2
or
V
DD
out
in
V
SS
V
SS
in
out
DL2,DR2
(37,38)
Input/
Output
Data input/output of Part 2 shift register
Controller
or
IZ0065
M
Input
Alternated
(40)
signal for LCD
PART
FCS
CL1
CL2
M
polarity
Controller
driver output
1
V
SS
latch clock
shift clock
M
CL1,CL2
Input
Data shift / latch clock
V
DD
(
)
(
)
(32,33)
2
V
SS
shift clock
latch clock
_
FCS
(43)
Input
Mode selection
V
DD
(
)
(
)
M
Shift/latch clock of display data and polarity of M signal
are changed by FCS signal.
By setting FCS to V
DD
level , user can select the function
that use Part 1 as segment driver and Part 2 as common
driver simultaneously.
NC(39)
No connection pin
N.C
IZ0065
5
IN T E G R A L
APPLICATION CIRCUIT
BT
1
5
7
8
V
(1 /5 b ia s)
LC D
LC
D


Pa
n
e
l
C
O
M1
~
C
OM1
6
SE
G
1
~
S
E
G
4
0
D
OS
C1
OS
C2
V
SS
M
CL
K
1
CL
K
2
V
DD
V
1
V
2
V
3
V
4
V
5
DB

~
DB
07
SC

~
SC
14
0
SC

~
SC
14
0
SC

~
SC
14
0
DL
2
DR
1
DR
2
CL
1
CL
2
M
DL
2
DR
1
DR
2
CL
1
CL
2
M
DL
2
DR
1
DR
2
CL
1
CL
2
M
V
EE
V
1
V
2
V
3
V
4
V
5
V
6
V
EE
V
1
V
2
V
3
V
4
V
5
V
6
V
EE
V
1
V
2
V
3
V
4
V
5
V
6
V
DD
V
SS
SH
L
2
SH
L
1
FC
S
DL
1
V
DD
V
SS
SH
L
2
SH
L
1
FC
S
DL
1
V
DD
V
SS
SH
L
2
SH
L
1
FC
S
DL
1
BT
1
5
1
0
B
T
15
10
B
T
15
1
0
V
DD
V
5
V
4
V
3
V
2
V
1
GN
D

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