TECHNICAL DATA
1
INTEGRAL
Triple 3-Input NOR Gate
The IN74HCT27A is high-speed Si-gate CMOS device and is pin
compatible with low power Schottky TTL (LSTTL). The device provide
the Triple 3-input NOR function.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN ASSIGNMENT
IN74HCT27A
ORDERING INFORMATION
IN74HCT27AN
Plastic
IN74HCT27AD
SOIC
IZ74HCT27A
Chip
T
A
= -55
to 125
C for all packages
PIN 14 =V
CC
PIN 7 = GND
FUNCTION TABLE
Inputs
Output
A
B
C
C
B
A
Y
+
+
=
L
L
L
H
X
X
H
L
X
H
X
L
H
X
X
L
X = don't care
1
2
3
5
4
6
7
V CC
14
13
12
11
10
8
9
GND
A1
B1
B2
B3
A2
A3
Y2
Y3
Y1
C1
C2
C3
A1
A2
A3
C1
C2
C3
Y1
Y2
Y3
B1
B2
B3
IN74HCT27A
2
INTEGRAL
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
25
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP**
SOIC Package**
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
4.5
5.5
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND
(V
IN
or
V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
IN74HCT27A
3
INTEGRAL
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
C
to
-55
C
85
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
0.1V or
V
OUT
V
CC
-0.1V
I
OUT
20 ?A
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low -Level
Input Voltage
V
OUT
0.1V or
V
OUT
V
CC
-0.1V
I
OUT
20 ?A
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IN
=V
IH
or V
IL
I
OUT
- 20 ?A
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
OH
Minimum High-Level
Output Voltage
V
IN
= V
IH
or V
IL
I
OUT
- 4.0 mA
4.5
3.98
3.84
3.70
V
V
IN
= V
IH
or V
IL
I
OUT
20 ?A
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
= V
IH
or V
IL
I
OUT
4.0 mA
4.5
0.26
0.33
0.4
I
IL
Maximum Low-Level
Input Leakage Current
V
IN
= 0 V
5.5
-0.1
-1.0
-1.0
A
I
IH
Maximum High-Level
Input Leakage Current
V
IN
= V
CC
5.5
0.1
1.0
1.0
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or 0 V
I
OUT
=0 ?A
5.5
2.0
20
40
A
-55
C
25
C ?
-125
C
I
CCT
Maximum
Additional Quiescent
Supply Current on
input pin
V
IN
=2.4V any one input,
V
IN
=0 V or V
CC
, others inputs
I
OUT
=0 ?A
4.5
2.9
2.4
m
IN74HCT27A
4
INTEGRAL
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
C to
-55
C
85
C
125
C
Unit
t
PHL
, t
PLH
Maximum Propagation Delay (Figure 1)
4.5
24
31
37
ns
t
THL
, t
TLH
Maximum Output Transition Time
(Figure 1)
4.5
15
19
22
ns
C
IN
Maximum Input Capacitance
5.0
10
10
10
pF
Power Dissipation Capacitance (Per Gate)
T
A
=25
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
54
pF
Figure 1. Switching Waveforms
Figure 2. Test Circuit
V = 3 V
1
V = 1.3 V
2
Input
Output
0.1
0.1
0.1
0.1
0.9
0.9
0.9
0.9
t
PHL
t
f
t
T HL
t
PLH
t
r
t
TLH
V
2
V
2
V
2
V
2
0 V
GND
V
CC
V
1
PULSE
GENERATOR
DEVICE
UNDER
TEST
V
CC
V
I
V
O
C
50 pF
L
R
T
Termination resistance R
T
- should
be equal to Z
OUT
of pulse
generators
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