Document Outline
- 21143 PCI/CardBus 10/100 Ethernet LAN Controller Datasheet
21143 PCI/CardBus 10/100 Ethernet LAN
Controller
Networking Silicon
Preliminary
Datasheet
Product Features
s
Fully compliant with Revision 2.1 of the
PCI Local Bus Specification and with
Revision 1.0 of the PCI Bus Power
Management Interface Specification.
s
Fully compliant with Revision 1.0 of the
Advanced Configuration and Power
Interface (ACPI) Specification and with
Revision 1.0 of the Network Device Class
Power Management Specification, under
the OnNow Architecture for Microsoft's
PC 97 Hardware Design Guide and PC 98
System Design Guide.
s
Supports IEEE 802.3 with full
Auto-Negotiation algorithm of full-duplex
and half-duplex operation for 10 Mb/s and
100 Mb/s (NWAY).
s
Supports IEEE 802.3 and ANSI 8802-3
Ethernet standards.
s
Supports direct memory access (DMA) and
has direct interface to both the CardBus*
and PCI local bus.
s
Provides glueless 32-bit PCI bus master
interface.
s
Contains large independent receive and
transmit FIFOs.
s
Contains internal PCS and scrambler/
descrambler for MII/SYM interface for
100BASE-TX.
s
Contains onchip integrated AUI port and a
10BASE-T transceiver.
s
Supports autodetection between
10BASE-T, AUI, and MII/SYM ports.
s
Provides an upgradable boot ROM
interface up to 256KB.
s
Supports remote wake-up-LAN and Magic
Packet* with the SecureONTM password
option.
s
Supports PCI/CardBus clock speed
frequency from dc to 33 MHz; network
operation with PCI clock from 20 MHz to
33 MHz.
s
Implements low-power management with
two power-saving modes (sleep and
snooze).
s
Implements low-power, 3.3-V CMOS
technology.
Order Number: 278073-001
November 1998
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
21143
Preliminary
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 21143 PCI/CardBus 10/100 Ethernet LAN Controller may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Preliminary
Datasheet
iii
21143
Contents
1.0
21143 OVERVIEW .......................................................................................................................... 1
1.1
General Description ............................................................................................................ 2
1.2
Microarchitecture ................................................................................................................ 3
2.0
PINOUT ........................................................................................................................................... 5
2.1
Signal Reference Tables .................................................................................................... 7
2.2
Signal Reference Tables .................................................................................................... 9
2.3
Pin Tables.........................................................................................................................15
2.4
Signal Grouping by Function ............................................................................................ 17
3.0
ELECTRICAL AND ENVIRONMENTAL SPECIFICATIONS........................................................ 19
3.1
Voltage Limit Ratings........................................................................................................ 19
3.2
Temperature Limit Ratings ...............................................................................................19
3.3
Power Specifications ........................................................................................................ 20
3.4
PCI Bus and CardBus Electrical Parameters ................................................................... 20
3.4.1
PCI and CardBus I/O Voltage Specifications ................................................... 21
3.4.2
System Bus Reset ............................................................................................ 22
3.4.3
PCI and CardBus Clock Specifications ............................................................ 22
3.4.4
Other PCI and CardBus Signals....................................................................... 24
3.5
AUI and Twisted-Pair DC Specifications .......................................................................... 25
3.6
Serial Interface Attachment Specifications ....................................................................... 26
3.6.1
Serial Clock Timing .......................................................................................... 26
3.6.2
Internal SIA Mode AUI Timing--Transmit ........................................................ 27
3.6.3
Internal SIA Mode AUI Timing--Receive ......................................................... 28
3.6.4
Internal SIA Mode AUI Timing--Collision......................................................... 28
3.6.5
Internal SIA Mode 10BASE-T Interface Timing--Transmit .............................. 29
3.6.6
Internal SIA Mode 10BASE-T Interface Timing--Receive ...............................30
3.6.7
Internal SIA Mode 10BASE-T Interface Timing--Idle Link Pulse ..................... 31
3.7
MII Interface Specifications .............................................................................................. 32
3.8
MII/SYM Port Timing ........................................................................................................ 32
3.8.1
MII/SYM 10/100-Mb/s and 10-Mb/s Timing--Transmit .................................... 32
3.8.2
MII/SYM 10/100-Mb/s Timing--Receive .......................................................... 34
3.8.3
SYM 10/100-Mb/s Timing--Signal Detect ........................................................ 35
3.8.4
MII 10/100-Mb/s Timing--Receive Error .......................................................... 35
3.8.5
MII 10/100-Mb/s Timing--Carrier Sense and Collision .................................... 36
3.9
Boot ROM and Serial ROM Port Specification ................................................................. 36
3.10 Boot ROM Port Timing ..................................................................................................... 37
3.10.1 Boot ROM Read Timing ................................................................................... 37
3.10.2 Boot ROM Write Timing.................................................................................... 38
3.11 Serial ROM Port Timing.................................................................................................... 39
3.12 External Register Timing .................................................................................................. 39
3.13 Joint Test Action Group--Test Access Port .....................................................................41
3.13.1 JTAG DC Specifications ................................................................................... 41
3.13.2 JTAG Boundary-Scan Timing........................................................................... 42
4.0
MECHANICAL SPECIFICATIONS ...............................................................................................43
Preliminary
Datasheet
1
21143
1.0
21143 Overview
The Intel 21143 PCI/CardBus* 10/100-Mb/s Ethernet LAN Controller (21143) supports the
peripheral component interconnect (PCI) bus or CardBus. It provides a direct interface connection
to the PCI bus and adapts easily to the CardBus and most other standard buses. The 21143 software
interface and data structures are optimized to minimize the host CPU load and to allow for
maximum flexibility in the buffer descriptor management. The 21143 contains large onchip FIFOs,
so no additional onboard memory is required. The 21143 also provides an upgradable boot ROM
interface.
In addition to the features listed on the title pages, the following features are also supported by the
21143:
PCI and CardBus Features:
Supports PCI and CardBus interfaces.
Supports PCI/CardBus clock control through clkrun.
Supports CardBus cstschg pin and Status Changed registers.
Supports automatic loading of subvendor ID and CardBus card information structure (CIS)
pointer from serial ROM to configuration registers.
Supports storage of CardBus card information structure (CIS) in the serial ROM or the
expansion ROM.
Supports the advanced PCI/CardBus read multiple, read line, and write and invalidate
commands.
Supports an unlimited PCI/CardBus burst.
Host Interface Features:
Includes a powerful onchip direct memory access (DMA) with programmable burst size,
providing low CPU utilization.
Supports early interrupt on transmit and receive.
Supports interrupt mitigation on transmit and receive.
Supports big or little endian byte ordering for buffers and descriptors.
Implements unique, patented intelligent arbitration between DMA channels to minimize
underflow and overflow.
Contains large independent receive and transmit FIFOs.
Network Side Features:
Supports three network ports: 10BASE-T (10 Mb/s), AUI (10 Mb/s), and
MII/SYM (10/100 Mb/s).
Contains a variety of flexible address filtering modes.
Implements signal-detect filtering to avoid false detection of link with 100BASE-TX symbol
interfaces.
Enables automatic detection and correction of 10BASE-T receive polarity.
Supports autodetection between 10BASE-T, AUI, and MII/SYM ports.
Offers a unique, patented solution to Ethernet capture-effect problem.
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