21152 PCI-to-PCI Bridge
Preliminary Datasheet
October 1998
Notice:
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ize a design with this information. Revised information will be published when the product is available.
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Order Number:
278060-001
21152 PCI-to-PCI Bridge Preliminary Datasheet
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Copyright Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
21152 PCI-to-PCI Bridge Preliminary Datasheet
iii
Contents
1
Introduction.................................................................................................................................... 1-1
1.1
Features............................................................................................................................ 1-1
1.2
Architecture ..................................................................................................................... 1-4
1.3
Data Path ......................................................................................................................... 1-6
1.3.1
Posted Write Queue .......................................................................................... 1-6
1.3.2
Delayed Transaction Queue .............................................................................. 1-7
1.3.3
Read Data Queue .............................................................................................. 1-7
2
Signal Pins ..................................................................................................................................... 2-1
2.1
Primary PCI Bus Interface Signals.................................................................................. 2-2
2.2
Secondary PCI Bus Interface Signals.............................................................................. 2-5
2.3
Secondary Bus Arbitration Signals ................................................................................. 2-7
2.4
Clock Signals................................................................................................................... 2-7
2.5
Reset Signals ................................................................................................................... 2-8
2.6
Miscellaneous Signals ..................................................................................................... 2-8
2.7
Nand Tree Signals ........................................................................................................... 2-9
3
Pin Assignment .............................................................................................................................. 3-1
3.1
Pin Location List (Numeric)............................................................................................ 3-2
3.2
Pin Signal List (Alphanumeric)....................................................................................... 3-5
4
PCI Bus Operation ......................................................................................................................... 4-1
4.1
Types of Transactions...................................................................................................... 4-1
4.2
Address Phase.................................................................................................................. 4-2
4.2.1
Single Address Phase ........................................................................................ 4-2
4.2.2
Dual Address Phase .......................................................................................... 4-2
4.3
Device Select (DEVSEL#) Generation ........................................................................... 4-3
4.4
Data Phase ....................................................................................................................... 4-3
4.5
Write Transactions........................................................................................................... 4-3
4.5.1
Posted Write Transactions ................................................................................ 4-4
4.5.2
Memory Write and Invalidate Transactions...................................................... 4-6
4.5.3
Delayed Write Transactions.............................................................................. 4-7
4.5.4
Write Transaction Address Boundaries ............................................................ 4-9
4.5.5
Buffering Multiple Write Transactions............................................................. 4-9
4.5.6
Fast Back-to-Back Write Transactions ........................................................... 4-10
4.6
Read Transactions ......................................................................................................... 4-11
4.6.1
Prefetchable Read Transactions ...................................................................... 4-11
4.6.2
Nonprefetchable Read Transactions ............................................................... 4-12
4.6.3
Read Prefetch Address Boundaries ................................................................. 4-12
4.6.4
Delayed Read Requests................................................................................... 4-13
4.6.5
Delayed Read Completion with Target........................................................... 4-13
4.6.6
Delayed Read Completion on Initiator Bus .................................................... 4-14
4.7
Configuration Transactions ........................................................................................... 4-17
4.7.1
Type 0 Access to the 21152 ............................................................................ 4-18
4.7.2
Type 1 to Type 0 Translation .......................................................................... 4-18
4.7.3
Type 1 to Type 1 Forwarding ......................................................................... 4-20
4.7.4
Special Cycles ................................................................................................. 4-20
iv
21152 PCI-to-PCI Bridge Preliminary Datasheet
4.8
Transaction Termination................................................................................................ 4-21
4.8.1
Master Termination Initiated by the 21152..................................................... 4-22
4.8.2
Master Abort Received by the 21152.............................................................. 4-22
4.8.3
Target Termination Received by the 21152 .................................................... 4-24
4.8.3.1 Delayed Write Target Termination Response .................................. 4-24
4.8.3.2 Posted Write Target Termination Response ..................................... 4-25
4.8.3.3 Delayed Read Target Termination Response ................................... 4-25
4.8.4
Target Termination Initiated by the 21152 ..................................................... 4-27
4.8.4.1 Target Retry ...................................................................................... 4-27
4.8.4.2 Target Disconnect ............................................................................. 4-28
4.8.4.3 Target Abort...................................................................................... 4-28
5
Address Decoding .......................................................................................................................... 5-1
5.1
Address Ranges ............................................................................................................... 5-1
5.2
I/O Address Decoding ..................................................................................................... 5-1
5.2.1
I/O Base and Limit Address Registers .............................................................. 5-2
5.2.2
ISA Mode .......................................................................................................... 5-3
5.3
Memory Address Decoding ............................................................................................. 5-4
5.3.1
Memory-Mapped I/O Base and Limit Address Registers ................................. 5-5
5.3.2
Prefetchable Memory Base and Limit Address Registers................................. 5-7
5.3.3
Prefetchable Memory 64-Bit Addressing Registers.......................................... 5-8
5.4
VGA Support ................................................................................................................... 5-9
5.4.1
VGA Mode ........................................................................................................ 5-9
5.4.2
VGA Snoop Mode............................................................................................. 5-9
6
Transaction Ordering ..................................................................................................................... 6-1
6.1
Transactions Governed by Ordering Rules ..................................................................... 6-1
6.2
General Ordering Guidelines ........................................................................................... 6-2
6.3
Ordering Rules................................................................................................................. 6-3
6.4
Data Synchronization ...................................................................................................... 6-4
7
Error Handling ............................................................................................................................... 7-1
7.1
Address Parity Errors....................................................................................................... 7-1
7.2
Data Parity Errors ............................................................................................................ 7-2
7.2.1
Configuration Write Transactions to 21152 Configuration Space.................... 7-2
7.2.2
Read Transactions ............................................................................................. 7-2
7.2.3
Delayed Write Transactions .............................................................................. 7-3
7.2.4
Posted Write Transactions................................................................................. 7-5
7.3
Data Parity Error Reporting Summary ............................................................................ 7-7
7.4
System Error (SERR#) Reporting ................................................................................. 7-14
8
Exclusive Access............................................................................................................................ 8-1
8.1
Concurrent Locks ............................................................................................................ 8-1
8.2
Acquiring Exclusive Access Across the 21152 ............................................................... 8-1
8.3
Ending Exclusive Access................................................................................................. 8-3
9
PCI Bus Arbitration ....................................................................................................................... 9-1
9.1
Primary PCI Bus Arbitration ........................................................................................... 9-1
9.2
Secondary PCI Bus Arbitration ....................................................................................... 9-1
9.2.1
Secondary Bus Arbitration Using the Internal Arbiter...................................... 9-2
9.2.2
Secondary Bus Arbitration Using an External Arbiter...................................... 9-3
21152 PCI-to-PCI Bridge Preliminary Datasheet
v
9.2.3
Bus Parking ....................................................................................................... 9-3
10
Clocks .......................................................................................................................................... 10-1
10.1
Primary and Secondary Clock Inputs ............................................................................ 10-1
10.2
Secondary Clock Outputs .............................................................................................. 10-2
10.2.1
Disabling Unused Secondary Clock Outputs.................................................. 10-2
11
Reset............................................................................................................................................. 11-1
11.1
Primary Interface Reset ................................................................................................. 11-1
11.2
Secondary Interface Reset ............................................................................................. 11-1
11.3
Chip Reset ..................................................................................................................... 11-2
12
PCI Power Management .............................................................................................................. 12-1
13
Configuration Space Registers..................................................................................................... 13-1
13.1
PCI-to-PCI Bridge Standard Configuration Registers .................................................. 13-3
13.1.1
Vendor ID Register -- Offset 00h .................................................................. 13-3
13.1.2
Device ID Register -- Offset 02h................................................................... 13-3
13.1.3
Command Register -- Offset 04h................................................................... 13-4
13.1.4
Status Register -- Offset 06h.......................................................................... 13-6
13.1.5
Revision ID Register -- Offset 08h ................................................................ 13-7
13.1.6
Programming Interface Register -- Offset 09h .............................................. 13-7
13.1.7
Subclass Code Register -- Offset 0Ah ........................................................... 13-7
13.1.8
Base Class Code Register -- Offset 0Bh........................................................ 13-8
13.1.9
Cache Line Size Register -- Offset 0Ch ........................................................ 13-8
13.1.10 Primary Latency Timer Register -- Offset 0Dh ............................................. 13-8
13.1.11 Header Type Register -- Offset 0Eh .............................................................. 13-9
13.1.12 Primary Bus Number Register -- Offset 18h ................................................. 13-9
13.1.13 Secondary Bus Number Register -- Offset 19h ............................................. 13-9
13.1.14 Subordinate Bus Number Register -- Offset 1Ah........................................ 13-10
13.1.15 Secondary Latency Timer Register -- Offset 1Bh ....................................... 13-10
13.1.16 I/O Base Address Register -- Offset 1Ch .................................................... 13-11
13.1.17 I/O Limit Address Register -- Offset 1Dh ................................................... 13-11
13.1.18 Secondary Status Register -- Offset 1Eh ..................................................... 13-12
13.1.19 Memory Base Address Register -- Offset 20h............................................. 13-13
13.1.20 Memory Limit Address Register -- Offset 22h............................................ 13-13
13.1.21 Prefetchable Memory Base Address Register -- Offset 24h........................ 13-14
13.1.22 Prefetchable Memory Limit Address Register -- Offset 26h....................... 13-14
13.1.23 Prefetchable Memory Base Address Upper 32 Bits
Register -- Offset 28h .................................................................................. 13-15
13.1.24 Prefetchable Memory Limit Address Upper 32 Bits
Register -- Offset 2Ch.................................................................................. 13-15
13.1.25 I/O Base Address Upper 16 Bits Register -- Offset 30h.............................. 13-16
13.1.26 I/O Limit Address Upper 16 Bits Register -- Offset 32h............................. 13-16
13.1.27 Capabilities Pointer Register -- Offset 34h.................................................. 13-17
13.1.28 Interrupt Pin -- Offset 3Dh .......................................................................... 13-17
13.1.29 Bridge Control -- Offset 3Eh ....................................................................... 13-18
13.1.30 Capability ID Register -- Offset DCh .......................................................... 13-21
13.1.31 Next Item Register -- Offset DDh ............................................................... 13-21
13.1.32 Power Management Capabilities Registers -- Offset DEh .......................... 13-22
13.1.33 Power Management Control and Status Registers -- Offset E0h ................ 13-23
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