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Электронный компонент: 21554BC

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21554 PCI-to-PCI Bridge for Embedded
Applications
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Datasheet
Product Features
s
Full compliance with the PCI Local Bus
Specification, Revision 2.1
s
3.3 V operation with 5 V-tolerant I/O
s
Selectable asynchronous or synchronous
primary and secondary interface clocks
s
Concurrent primary and secondary bus
operation
s
Queuing of multiple transactions in either
direction
s
256 bytes of posted write (data and
address) buffering in each direction
s
256 bytes of read data buffering in each
direction
s
Four delayed transaction entries in each
direction
s
Two dedicated I
2
O delayed transaction
entries
s
Two sets of standard PCI configuration
registers corresponding to the primary and
secondary interface; each set is accessible
from either the primary or secondary
interface
s
Memory and I/O mapping of 21554 CSRs
on both the primary and secondary
interface
s
Four downstream and three upstream
address ranges, with programmable size
and prefetchability
s
Look-up table based address translation for
one upstream range; direct offset address
translation for all other forwarding ranges
s
Inverse decoding above the 4 GB address
boundary for upstream DACs
s
Ability to generate Type 0 and Type 1
configuration transactions on the primary
or secondary interface via configuration or
I/O CSR accesses
s
Ability to generate I/O transactions on the
primary or secondary interface via I/O
CSR
s
I
2
O message unit
s
Doorbell registers for software generation
of primary and secondary bus interrupts,
16 bits per interface
s
Eight Dwords of scratchpad registers
s
Parallel ROM interface with primary bus
expansion ROM base address register
s
Serial ROM interface
s
Secondary bus arbiter support for up to
nine devices (in addition to the 21554)
s
CompactPCI Hot Swap Controller
s
Configurable PCI power management
support
s
IEEE Standard 1149.1 boundary-scan
JTAG interface
Order Number: 278089-001
Dec 1998
Notice: This document contains information on products in the design phase of development.
Do not finalize a design with this information. Revised information will be published when the
product is available. Verify with your local Intel sales office that you have the latest datasheet
before finalizing a design.
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Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 21554 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
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Datasheet
iii
21554 PCI-to-PCI Bridge for Embedded Applications
Contents
1.0
Introduction......................................................................................................................... 1
1.1
General Information............................................................................................... 1
1.2
Comparison of 21554 and Standard PCI-to-PCI Bridge........................................ 1
1.3
Architectural Overview .......................................................................................... 3
1.3.1
Data Buffers ............................................................................................. 4
1.3.1.1 Registers ..................................................................................... 4
1.3.2
Control Logic ............................................................................................ 4
1.4
Conventions and Terminology............................................................................... 5
1.4.1
Caution ..................................................................................................... 5
1.4.2
Data Units................................................................................................. 5
1.4.3
Note.......................................................................................................... 6
1.4.4
Numbering ................................................................................................ 6
1.4.5
Signal Names ........................................................................................... 6
1.4.6
SIGNAME# ............................................................................................... 6
1.5
Manual Organization ............................................................................................. 6
2.0
Signal Pins ......................................................................................................................... 7
2.1
Primary PCI Bus Interface 64-Bit Extension Signals........................................... 10
2.2
Secondary PCI Bus Interface Signals ................................................................. 11
2.3
Secondary PCI Bus Interface 64-Bit Extension Signals ...................................... 13
2.4
Secondary PCI Bus Arbitration Signals...............................................................14
2.5
Clock Signals....................................................................................................... 14
2.6
Power Management, Hot Swap, and Reset Signals ........................................... 15
2.7
ROM Interface Signals ........................................................................................ 16
2.8
Miscellaneous Signals.........................................................................................17
2.9
Diagnostic Signals...............................................................................................18
3.0
Pin Assignment ................................................................................................................ 19
3.1
Pin Location List (Alphanumeric)......................................................................... 20
3.2
Pin Signal List (Alphanumeric) ............................................................................24
4.0
JTAG Boundary Scan....................................................................................................... 30
4.1
Test Access Port Controller................................................................................. 30
4.1.1
Initialization............................................................................................. 30
4.2
Instruction Register ............................................................................................. 31
4.3
Bypass Register .................................................................................................. 31
4.4
Boundary-Scan Register ..................................................................................... 31
4.5
Boundary-Scan Order .........................................................................................32
5.0
Electrical Specifications.................................................................................................... 38
5.1
PCI Electrical Specification Conformance........................................................... 38
5.2
Absolute Maximum Ratings................................................................................. 38
5.3
DC Specifications ................................................................................................ 39
5.4
AC Timing Specifications .................................................................................... 39
5.4.1
Clock Timing Specifications ................................................................... 40
5.4.2
PCI Signal Timing Specifications ........................................................... 41
5.4.3
Reset Timing Specifications ................................................................... 42
21554 PCI-to-PCI Bridge for Embedded Applications
iv
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Datasheet
5.4.4
Serial ROM Timing Specifications.......................................................... 42
5.4.5
Parallel ROM Timing Specifications ....................................................... 43
5.4.6
JTAG Timing Specifications ................................................................... 43
6.0
Mechanical Specifications................................................................................................ 44
Figures
1
21554 Intelligent Controller Application................................................................. 2
2
21554 Microarchitecture........................................................................................ 5
3
21554 PBGA Cavity Down View ......................................................................... 19
4
PCI Clock Signal AC Parameter Measurements................................................. 40
5
PCI Signal Timing Measurement Conditions ...................................................... 41
6
304 PBGA (Two-Layer) Package ........................................................................ 44
Tables
1
21554 and PPB Feature Comparison .................................................................. 3
2
Data-unit Terminology........................................................................................... 6
3
Signal Pin Function Groups .................................................................................. 7
4
Signal Type Abbreviations .................................................................................... 7
5
Primary PCI Bus Interface Signals (Sheet 1 of 2) ................................................. 8
6
Primary PCI Bus Interface 64-Bit Extension Signals .......................................... 10
7
Secondary PCI Bus Interface Signals (Sheet 1 of 2) .......................................... 11
8
Secondary PCI Bus Interface 64-Bit Extension Signals ..................................... 13
9
Secondary PCI Bus Arbitration Signals............................................................... 14
10
Clock Signals ..................................................................................................... 14
11
Power Management, Hot Swap, and Reset Signals .......................................... 15
12
ROM Interface Signals (Sheet 1 of 2) ................................................................ 16
13
Miscellaneous Signals......................................................................................... 17
14
JTAG Signals ...................................................................................................... 18
15
Signal Type Abbreviations .................................................................................. 20
16
21554 Pin Location List (Alphanumeric) (Sheet 1 of 5)....................................... 20
17
Signal Type Abbreviations .................................................................................. 25
18
21554 Pin Signal List (Alphanumeric) (Sheet 1 of 5) .......................................... 25
19
JTAG Signal Pins ................................................................................................ 30
20
JTAG Instruction Register Options ..................................................................... 31
21
Boundary-Scan Order (Sheet 1 of 6) ................................................................. 32
22
Absolute Maximum Ratings ................................................................................ 38
23
Functional Operating Range ............................................................................... 38
24
DC Parameters ................................................................................................... 39
25
PCI Clock Signal AC Parameters........................................................................ 40
26
PCI Signal Timing Specifications ........................................................................ 41
27
Reset Timing Specifications................................................................................ 42
28
Serial ROM Timing Specifications....................................................................... 42
29
Parallel ROM Timing Specifications.................................................................... 43
30
JTAG Timing Specifications ................................................................................ 43
31
304-Point 2-Layer PBGA Package Dimensions.................................................. 45
21554 PCI-to-PCI Bridge for Embedded Applications
Product Preview
Datasheet
1
1.0
Introduction
This data sheet describes the 21554 PCI-to-PCI bridge chip for embedded applications. For a
detailed functional and register description, see the 21554 PCI-to-PCI Bridge for Embedded
Applications Hardware Reference Manual
.
1.1
General Information
The 21554 is a PCI peripheral chip that performs PCI bridging functions for embedded and
intelligent I/O applications. The 21554 is a "non-transparent" PCI-to-PCI bridge that acts as a
gateway to an intelligent subsystem. It allows a local processor to independently configure and
control the local subsystem. The 21554 implements an I
2
O message unit that enables any local
processor to function as an intelligent I/O processor (IOP) in an I
2
O-capable system. Because the
21554 is architecture independent, it works with any host and local processors that support a PCI
bus. This architecture independence enables vendors to leverage existing investments while
moving products to PCI technology.
Unlike a transparent PCI-to-PCI bridge, the 21554 is specifically designed to bridge between two
processor domains. The processor domain on the primary interface of the 21554 is also referred to
as the host domain, and its processor is the host processor. The secondary bus interfaces to the local
domain and the local processor. Special features include support of independent primary and
secondary PCI clocks, independent primary and secondary address spaces, and address translation
between the primary (host) and secondary (local) domains.
The 21554 enables add-in card vendors to present to the host system a higher level of abstraction
than is possible with a transparent PCI-to-PCI bridge. The 21554 uses a Type 0 configuration
header, which presents the entire subsystem as a single "device" to the host processor. This allows
loading of a single device driver for the entire subsystem, and independent local processor
initialization and control of the subsystem devices. Because the 21554 uses a Type 0 configuration
header, it does not require hierarchical PCI-to-PCI bridge configuration code.
The 21554 forwards transactions between the primary and secondary PCI buses as does a transparent
PCI-to-PCI bridge. In contrast to a transparent PCI-to-PCI bridge, however, the 21554 can translate
the address of a forwarded transaction from a system address to a local address, or vice versa. This
mechanism allows the 21554 to hide subsystem resources from the host processor and to resolve any
resource conflicts that may exist between the host and local subsystems.
The 21554 operates at 3.3 V, but is also 5.0 V I/O tolerant. Adapter cards designed using the 21554
can be keyed as universal, thus permitting use in either a 5 V or 3 V slot.
The 21554 supports a 64-bit primary PCI bus, a 64-bit secondary PCI bus, and a maximum
operating frequency of 33 MHz.
1.2
Comparison of 21554 and Standard PCI-to-PCI Bridge
The 21554 is functionally similar to a standard PCI-to-PCI bridge (PPB) in that both provide a
connection path between devices attached to two independent PCI buses. A 21554 and a PPB allow
the electrical loading of devices on one PCI bus to be isolated from the other bus while permitting
concurrent operation on both buses. Because the PCI Local Bus Specification restricts PCI option
cards to a single electrical load, the ability of PPBs and the 21554 to spawn PCI buses enables the
design of multidevice PCI option cards. The key difference between a PPB and the 21554 is that