Ultra-Low Voltage Intel
Celeron
Processor (0.13 ) in the Micro FC-BGA
Package
at 650 MHz and 400 MHz
Datasheet
Product Features
Ultra-Low Voltage Intel
Celeron
Processor (0.13) with the following
processor core/bus speeds:
-- 650/100 MHz at 1.10 V
-- 400/100 MHz at 0.95 V
Supports the Intel Architecture with
Dynamic Execution
On-die primary 16-Kbyte instruction cache
and 16-Kbyte write-back data cache
On-die second level cache (256-Kbyte)
with Advanced Transfer Cache
Architecture
Data Prefetch Logic
Integrated AGTL termination
Integrated math co-processor
Micro-FCBGA packaging technologies
-- Supports small form factor applied
computing designs
-- Exposed die enables more efficient heat
dissipation
Fully compatible with previous Intel
microprocessors
-- Binary compatible with all applications
-- Support for MMXTM technology
-- Support for Streaming SIMD Extensions
Power Management Features
-- Quick Start and Deep Sleep modes
provide low power dissipation
On-die thermal diode
Order Number: 273804-002
May 2003
2
Datasheet
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ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Ultra Low Voltage Intel
Celeron
Processor (0.13 ) in the Micro FC-BGA Package at 650 Mhz and 400 MHz may contain design defects or
errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright Intel Corporation, 2003
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Datasheet
3
Contents
Contents
1.0
Introduction....................................................................................................................................9
1.1
Overview ............................................................................................................................... 9
1.2
State of the Data ................................................................................................................. 10
1.3
Terminology ........................................................................................................................ 10
1.4
References ......................................................................................................................... 10
2.0
Ultra-Low Voltage Intel
Celeron
Processor Features...........................................................13
2.1
New Features in the Ultra-Low Voltage Intel
Celeron
Processor.................................... 13
2.1.1
100-MHz PSB With AGTL Signaling...................................................................... 13
2.1.2
256-K On-die Integrated L2 Cache ........................................................................ 13
2.1.3
Data Prefetch Logic ............................................................................................... 13
2.1.4
Differential Clocking ............................................................................................... 13
2.1.5
Signal Differences Between the Mobile Intel
Celeron
Processor in BGA2 and Micro-PGA2 Packages and
the Ultra-Low Voltage Intel
Celeron
Processor in Micro FC-BGA Packages..... 13
2.2
Power Management............................................................................................................ 14
2.2.1
Clock Control Architecture .....................................................................................14
2.2.2
Normal State .......................................................................................................... 14
2.2.3
Auto Halt State....................................................................................................... 14
2.2.4
Quick Start State.................................................................................................... 15
2.2.5
HALT/Grant Snoop State ....................................................................................... 16
2.2.6
Deep Sleep State................................................................................................... 16
2.2.7
Operating System Implications of Low-power States ............................................ 16
2.3
AGTL Signals......................................................................................................................17
2.4
Ultra-Low Voltage Intel
Celeron
Processor CPUID ........................................................ 17
3.0
Electrical Specifications ............................................................................................................. 19
3.1
Processor System Signals .................................................................................................. 19
3.1.1
Power Sequencing Requirements .........................................................................20
3.1.2
Test Access Port (TAP) Connection ...................................................................... 21
3.1.3
Catastrophic Thermal Protection ........................................................................... 21
3.1.4
Unused Signals...................................................................................................... 21
3.1.5
Signal State in Low-power States .......................................................................... 21
3.2
Power Supply Requirements .............................................................................................. 22
3.2.1
Decoupling Guidelines ........................................................................................... 22
3.2.2
Voltage Planes....................................................................................................... 23
3.2.3
PLL RLC Filter Specification .................................................................................. 23
3.2.4
Voltage Identification ............................................................................................. 26
3.2.5
VTTPWRGD Signal Quality Specification.............................................................. 27
3.3
System Bus Clock and Processor Clocking........................................................................ 28
3.4
Maximum Ratings ...............................................................................................................29
3.5
DC Specifications ...............................................................................................................30
3.6
AC Specifications................................................................................................................ 34
3.6.1
System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications ........ 34
4.0
System Signal Simulations......................................................................................................... 47
4.1
System Bus Clock (BCLK) and PICCLK DC
Contents
4
Datasheet
Specifications and AC Signal Quality Specifications47
4.2
AGTL AC Signal Quality Specifications .............................................................................. 48
4.3
Non-AGTL Signal Quality Specifications ............................................................................ 50
4.3.1
PWRGOOD, VTTPWRGD Signal Quality Specifications ...................................... 50
5.0
Mechanical Specifications.......................................................................................................... 53
5.1
Surface Mount Micro FC-BGA Package ............................................................................. 53
5.2
Signal Listings..................................................................................................................... 55
6.0
VCC Thermal Specifications....................................................................................................... 65
6.1
Thermal Diode .................................................................................................................... 66
7.0
Processor Initialization and Configuration ............................................................................... 67
7.1
Description.......................................................................................................................... 67
7.1.1
Quick Start Enable................................................................................................. 67
7.1.2
System Bus Frequency.......................................................................................... 67
7.1.3
APIC Enable .......................................................................................................... 67
7.2
Clock Frequencies and Ratios............................................................................................ 67
8.0
Processor Interface ..................................................................................................................... 69
8.1
Alphabetical Signal Reference............................................................................................ 69
8.1.1
A[35:3]# (I/O AGTL)............................................................................................ 69
8.1.2
A20M# (I - 1.5V Tolerant) ...................................................................................... 69
8.1.3
ADS# (I/O - AGTL)................................................................................................. 69
8.1.4
AERR# (I/O - AGTL) .............................................................................................. 69
8.1.5
AP[1:0]# (I/O - AGTL) ............................................................................................ 69
8.1.6
BCLK, BCLK# (I).................................................................................................... 70
8.1.7
BERR# (I/O - AGTL) .............................................................................................. 70
8.1.8
BINIT# (I/O - AGTL)............................................................................................... 70
8.1.9
BNR# (I/O - AGTL) ................................................................................................ 71
8.1.10 BP[3:2]# (I/O - AGTL) ............................................................................................ 71
8.1.11 BPM[1:0]# (I/O - AGTL) ......................................................................................... 71
8.1.12 BPRI# (I - AGTL) ................................................................................................... 71
8.1.13 BREQ0# (I/O - AGTL)............................................................................................ 71
8.1.14 BSEL[1:0] (O 3.3V Tolerant)............................................................................... 71
8.1.15 CLKREF (Analog) .................................................................................................. 72
8.1.16 CMOSREF (Analog) .............................................................................................. 72
8.1.17 D[63:0]# (I/O - AGTL) ............................................................................................ 72
8.1.18 DBSY# (I/O - AGTL) .............................................................................................. 72
8.1.19 DEFER# (I - AGTL)................................................................................................ 72
8.1.20 DEP[7:0]# (I/O - AGTL).......................................................................................... 73
8.1.21 DRDY# (I/O - AGTL).............................................................................................. 73
8.1.22 DPSLP# (I - 1.5 V Tolerant)................................................................................... 73
8.1.23 EDGCTRLP (I-Analog) .......................................................................................... 73
8.1.24 FERR# (O - 1.5 V Tolerant Open-drain) ................................................................ 73
8.1.25 FLUSH# (I - 1.5 V Tolerant)................................................................................... 73
8.1.26 HIT# (I/O - AGTL), HITM# (I/O - AGTL)................................................................. 73
8.1.27 IERR# (O - 1.5 V Tolerant Open-drain) ................................................................. 74
8.1.28 IGNNE# (I - 1.5 V Tolerant) ................................................................................... 74
8.1.29 INIT# (I - 1.5 V Tolerant)........................................................................................ 74
8.1.30 INTR (I - 1.5 V Tolerant) ........................................................................................ 74
Datasheet
5
Contents
8.1.31 LINT[1:0] (I - 1.5 V Tolerant) .................................................................................. 74
8.1.32 LOCK# (I/O - AGTL) .............................................................................................. 75
8.1.33 NCTRL (I - Analog) ................................................................................................ 75
8.1.34 NMI (I - 1.5 V Tolerant) ..........................................................................................75
8.1.35 PICCLK (I 2.0 V Tolerant) ................................................................................... 75
8.1.36 PICD[1:0] (I/O - 1.5 V Tolerant Open-drain) .......................................................... 75
8.1.37 PLL1, PLL2 (Analog) ............................................................................................. 75
8.1.38 PRDY# (O - AGTL) ................................................................................................ 76
8.1.39 PREQ# (I - 1.5 V Tolerant) .................................................................................... 76
8.1.40 PWRGOOD (I 1.8 V Tolerant)............................................................................. 76
8.1.41 REQ[4:0]# (I/O - AGTL) ......................................................................................... 76
8.1.42 RESET# (I - AGTL) ................................................................................................ 76
8.1.43 RP# (I/O - AGTL) ................................................................................................... 77
8.1.44 RS[2:0]# (I/O - AGTL) ............................................................................................77
8.1.45 RSP# (I - AGTL) .................................................................................................... 77
8.1.46 RTTIMPEDP (I-Analog) ......................................................................................... 77
8.1.47 SMI# (I - 1.5 V Tolerant) ........................................................................................ 77
8.1.48 STPCLK# (I - 1.5 V Tolerant)................................................................................. 77
8.1.49 TCK (I - 1.5 V Tolerant) ......................................................................................... 78
8.1.50 TDI (I - 1.5 V Tolerant) ........................................................................................... 78
8.1.51 TDO (O - 1.5 V Tolerant Open-drain) .................................................................... 78
8.1.52 TESTHI[2:1] (I - 1.25 V Tolerant) ........................................................................... 78
8.1.53 TESTLO[2:1] (I - 1.5 V Tolerant)............................................................................ 78
8.1.54 THERMDA, THERMDC (Analog)........................................................................... 78
8.1.55 TMS (I - 1.5 V Tolerant) ......................................................................................... 78
8.1.56 TRDY# (I/O - AGTL) .............................................................................................. 78
8.1.57 TRST# (I - 1.5 V Tolerant) .....................................................................................78
8.1.58 VID[4:0] (O Open-drain)...................................................................................... 79
8.1.59 V
REF
(Analog) ........................................................................................................79
8.1.60 VTTPWRGD (I 1.25 V) ....................................................................................... 79
8.2
Signal Summaries...............................................................................................................79
Figures
1
Clock Control States ................................................................................................................... 15
2
PLL RLC Filter ............................................................................................................................ 23
3
PLL Filter Specifications ............................................................................................................. 24
4
VTTPWRGD System-Level Connections ................................................................................... 27
5
Noise Estimation ......................................................................................................................... 28
6
BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform....................................... 39
7
Differential BCLK/BCLK# Waveform (Common Mode) .............................................................. 39
8
BCLK/BCLK# Waveform (Differential Mode) ..............................................................................40
9
Valid Delay Timings ....................................................................................................................40
10
Setup and Hold Timings ............................................................................................................. 40
11
Cold/Warm Reset and Configuration Timings ............................................................................ 41
12
Power-on Sequence and Reset Timings .................................................................................... 42
13
Power Down Sequencing and Timings (V
CC
Leading) ............................................................... 43
14
Power Down Sequencing and Timings (VCCT Leading)............................................................ 44
15
Test Timings (Boundary Scan) ................................................................................................... 45
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