1.8 Volt Intel
Wireless Flash Memory
with 3-Volt I/O (W30)
28F640W30, 28F320W30, 28F128W30
Datasheet
Product Features
The 1.8 Volt Intel
Wireless Flash Memory with 3-Volt I/O (W30) device combines state-of-the-art Intel
Flash
technology to provide the most versatile memory solution for high performance, low power, board constraint
memory applications.
The W30 device offers a multi-partition, dual-operation flash architecture that enables the device to read from one
partition while programming or erasing in another partition. This Read-While-Write or Read-While-Erase
capability makes it possible to achieve higher data throughput rates as compared to single partition devices, and it
allows two processors to interleave code execution because program and erase operations can now occur as
background processes.
The W30 device incorporates a new Enhanced Factory Programming (EFP) mode to improve 12 V factory
programming performance. This new feature helps eliminate manufacturing bottlenecks associated with
programming high density flash devices. Compare the EFP program time of 3.5 s per word to the standard
factory program time of 8.0 s per word and save significant factory programming time for improved factory
efficiency.
Additionally, the W30 device includes block lock-down and programmable WAIT signal polarity, and is
supported by an array of software tools. All these features make this product a perfect solution for any demanding
memory application.
High Performance Read-While-Write/Erase
-- Burst Frequency at 40 MHz
-- 70 ns Initial Access Speed
-- 25 ns Page-Mode Read Speed
-- 20 ns Burst-Mode Read Speed
-- Burst and Page Mode in All Blocks and
across All Partition Boundaries
-- Burst Suspend Feature
-- Enhanced Factory Programming:
3.5 s per Word Program Time
-- Programmable WAIT Signal Polarity
Flash Power
-- V
CC
= 1.70 V 1.90 V
-- V
CCQ
= 2.20 V 3.30 V
-- Standby Current (0.13 m) = 8 A (typ.)
-- Read Current = 7 mA
(4 word burst, typ.)
Flash Software
-- 5/9 s (typ.) Program/Erase Suspend Latency
Time
-- Intel
Flash Data Integrator (FDI) and
Common Flash Interface (CFI) Compatible
Quality and Reliability
-- Operating Temperature:
40 C to +85 C
-- 100K Minimum Erase Cycles
-- 0.13 m ETOXTM VIII Process
-- 0.18 m ETOXTM VII Process
Flash Architecture
-- Multiple 4-Mbit Partitions
-- Dual Operation: RWW or RWE
-- Parameter Block Size = 4-Kword
-- Main block size = 32-Kword
-- Top and Bottom Parameter Devices
Flash Security
-- 128-bit Protection Register: 64 Unique Device
Identifier Bits; 64 User OTP Protection
Register Bits
-- Absolute Write Protection with V
PP
at Ground
-- Program and Erase Lockout during Power
Transitions
-- Individual and Instantaneous Block Locking/
Unlocking with Lock-Down
Density and Packaging
-- 0.13 m: 32-, 64-, and 128-Mbit Densities in
VF BGA Package
-- 0.18 m: 32- and 128-Mbit Densities in VF
BGA Package; 64-Mbit Density in BGA*
Package
-- 56 Active Ball Matrix, 0.75 mm Ball-Pitch
-- 16-bit Data Bus
290702-007
March 2003
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Datasheet
2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O (W30) may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright 2003, Intel Corporation.
*Other names and brands may be claimed as the property of others.
Datasheet
3
28F320W30, 28F640W30, 28F128W30
Contents
1.0
Introduction
..................................................................................................................7
1.1
Document Purpose................................................................................................7
1.2
Nomenclature ........................................................................................................7
1.3
Conventions ..........................................................................................................7
2.0
Device Description
....................................................................................................9
2.1
Product Overview ..................................................................................................9
2.2
Package Diagram................................................................................................10
2.3
Signal Descriptions..............................................................................................11
2.4
Memory Map and Partitioning .............................................................................12
3.0
Device Operations
...................................................................................................15
3.1
Bus Operations....................................................................................................15
3.1.1
Read.......................................................................................................15
3.1.2
Burst Suspend........................................................................................16
3.1.3
Standby ..................................................................................................16
3.1.4
Reset ......................................................................................................16
3.1.5
Write .......................................................................................................17
3.2
Device Commands ..............................................................................................17
3.3
Command Sequencing........................................................................................20
4.0
Read Operations
.......................................................................................................22
4.1
Read Array ..........................................................................................................22
4.2
Read Device ID ...................................................................................................22
4.3
Read Query (CFI)................................................................................................23
4.4
Read Status Register ..........................................................................................23
4.5
Clear Status Register ..........................................................................................25
5.0
Program Operations
................................................................................................25
5.1
Word Program .....................................................................................................25
5.2
Factory Programming..........................................................................................26
5.3
Enhanced Factory Program (EFP) ......................................................................27
5.3.1
EFP Requirements and Considerations .................................................27
5.3.2
Setup ......................................................................................................28
5.3.3
Program..................................................................................................28
5.3.4
Verify ......................................................................................................28
5.3.5
Exit .........................................................................................................29
6.0
Program and Erase Operations
..........................................................................31
6.1
Program/Erase Suspend and Resume................................................................31
6.2
Block Erase .........................................................................................................33
6.3
Read-While-Write and Read-While-Erase...........................................................35
7.0
Security Modes
.........................................................................................................36
7.1
Block Lock Operations ........................................................................................36
7.1.1
Lock........................................................................................................37
7.1.2
Unlock ....................................................................................................37
28F320W30, 28F640W30, 28F128W30
4
Datasheet
7.1.3
Lock-Down ............................................................................................. 37
7.1.4
Block Lock Status................................................................................... 38
7.1.5
Lock During Erase Suspend .................................................................. 38
7.1.6
Status Register Error Checking.............................................................. 38
7.1.7
WP# Lock-Down Control........................................................................ 39
7.2
Protection Register.............................................................................................. 39
7.2.1
Reading the Protection Register ............................................................ 40
7.2.2
Programing the Protection Register ....................................................... 40
7.2.3
Locking the Protection Register ............................................................. 41
7.3
VPP Protection.................................................................................................... 42
8.0
Set Configuration Register
................................................................................... 43
8.1
Read Mode (CR[15]) ........................................................................................... 45
8.2
First Access Latency Count (CR[13:11])............................................................. 45
8.2.1
Latency Count Settings .......................................................................... 46
8.3
WAIT Signal Polarity (CR[10])............................................................................. 46
8.4
WAIT Signal Function ......................................................................................... 46
8.5
Data Hold (CR[9])................................................................................................ 47
8.6
WAIT Delay (CR[8]) ............................................................................................ 48
8.7
Burst Sequence (CR[7]) ...................................................................................... 48
8.8
Clock Edge (CR[6]) ............................................................................................. 50
8.9
Burst Wrap (CR[3]).............................................................................................. 50
8.10
Burst Length (CR[2:0]) ........................................................................................ 50
9.0
Power Consumption
............................................................................................... 51
9.1
Active Power ....................................................................................................... 51
9.2
Automatic Power Savings (APS)......................................................................... 51
9.3
Standby Power.................................................................................................... 51
9.4
Power-Up/Down Characteristics ......................................................................... 52
9.4.1
System Reset and RST#........................................................................ 52
9.4.2
VCC, VPP, and RST# Transitions.......................................................... 52
9.5
Power Supply Decoupling ................................................................................... 52
10.0
Thermal and DC Characteristics
........................................................................ 53
10.1
Absolute Maximum Ratings ................................................................................ 53
10.2
Operating Conditions .......................................................................................... 53
10.3
DC Current Characteristics ................................................................................. 55
10.4
DC Voltage Characteristics ................................................................................. 57
11.0
AC Characteristics
................................................................................................... 58
11.1
Read Operations ................................................................................................ 58
11.2
AC Write Characteristics ..................................................................................... 68
11.3
Erase and Program Times .................................................................................. 72
11.4
Reset Specifications............................................................................................ 73
11.5
AC I/O Test Conditions ....................................................................................... 74
11.6
Device Capacitance ............................................................................................ 75
Appendix A Write State Machine States
............................................................................... 76
Appendix B Common Flash Interface
.................................................................................... 79
Appendix C Mechanical Specifications
................................................................................ 88
Appendix D Ordering Information
........................................................................................... 94
Datasheet
5
28F320W30, 28F640W30, 28F128W30
Revision History
Date of
Revision
Version
Description
09/19/00
-001
Original Version
03/14/01
-002
28F3208W30 product references removed (product was discontinued)
28F640W30 product added
Revised Table 2, Signal Descriptions (DQ
150
, ADV#, WAIT, S-UB#, S-LB#, V
CCQ
)
Revised Section 3.1, Bus Operations
Revised Table 5, Command Bus Definitions, Notes 1 and 2
Revised Section 4.2.2, First Latency Count (LC
20
); revised Figure 6, Data Output
with LC Setting at Code 3; added Figure 7, First Access Latency Configuration
Revised Section 4.2.3, WAIT Signal Polarity (WT)
Added Section 4.2.4, WAIT Signal Function
Revised Section 4.2.5, Data Output Configuration (DOC)
Added Figure 8, Data Output Configuration with WAIT Signal Delay
Revised Table 13, Status Register DWS and PWS Description
Revised entire Section 5.0, Program and Erase Voltages
Revised entire Section 5.3, Enhanced Factory Programming (EFP)
Revised entire Section 8.0, Flash Security Modes
Revised entire Section 9.0, Flash Protection Register; added Table 15, Simulta-
neous Operations Allowed with the Protection Register
Revised Section 10.1, Power-Up/Down Characteristics
Revised Section 11.3, DC Characteristics. Changed I
CCS,
I
CCWS,
I
CCES
Specs from
18 A to 21A; changed I
CCR
Spec from 12 mA to 15 mA (burst length = 4)
Added Figure 20, WAIT Signal in Synchronous Non-Read Array Operation Wave-
form
Added Figure 21, WAIT Signal in Asynchronous Page-Mode Read Operation
Waveform
Added Figure 22, WAIT Signal in Asynchronous Single-Word Read Operation
Waveform
Revised Figure 23, Write Waveform
Revised Section 12.4, Reset Operations
Clarified Section 13.2, SRAM Write Operation, Note 2
Revised Section 14.0, Ordering Information
Minor text edits
04/05/02
-003
Deleted SRAM Section
Added 128M DC and AC Specifications
Added Burst Suspend
Added Read While Write Transition Waveforms
Various text edits
04/24/02
-004
Revised Device ID
Revised Write Speed Bin
Various text edits
10/20/02
-005
Added Latency Count Tables
Updated Packing Ball-Out and Dimension
Various text edits
Minor text clarifications
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