5 Volt Intel StrataFlash
Memory
28F320J5 and 28F640J5 (x8/x16)
Datasheet
Product Features
Capitalizing on two-bit-per-cell technology, 5 Volt Intel StrataFlash
memory products provide 2Xthe bits
in 1Xthe space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory
devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market.
Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOXTM technology as Intel's one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result,
Intel StrataFlash components are ideal for code or data applications where high density and low cost are
required. Examples include networking, telecommunications, audio recording, and digital imaging.
Intel StrataFlash memory components deliver a new generation of forward-compatible software support.
By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel's 0.4 micron ETOXTM V process technology and Intel's 0.25 micron ETOX VI
process technology, 5 Volt Intel StrataFlash memory provides the highest levels of quality and reliability.
s
High-Density Symmetrically-Blocked
Architecture
-- 64 128-Kbyte Erase Blocks (64 M)
-- 32 128-Kbyte Erase Blocks (32 M)
s
4.5 V5.5 V V
CC
Operation
-- 2.7 V3.6 V and 4.5 V5.5 V I/O
Capable
s
120 ns Read Access Time (32 M)
150 ns Read Access Time (64 M)
s
Enhanced Data Protection Features
-- Absolute Protection with
V
PEN
= GND
-- Flexible Block Locking
-- Block Erase/Program Lockout during
Power Transitions
s
Industry-Standard Packaging
-- SSOP Package (32, 64 M)
TSOP Package (32 M)
s
Cross-Compatible Command Support
-- Intel Basic Command Set
-- Common Flash Interface
-- Scalable Command Set
s
32-Byte Write Buffer
-- 6 s per Byte Effective Programming
Time
s
6,400,000 Total Erase Cycles (64 M)
3,200,000 Total Erase Cycles (32 M)
-- 100,000 Erase Cycles per Block
s
Automation Suspend Options
-- Block Erase Suspend to Read
-- Block Erase Suspend to Program
s
System Performance Enhancements
-- STS Status Output
s
Operating Temperature 20 C to + 85 C
(40 C to +85 C on .25
micron ETOXVI)
process technology parts)
Order Number: 290606-015
April 2002
Notice: This document contains information on products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizinga design.
2
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relatingto sale and/or use of Intel products includingliability or warranties relatingto
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arisingfrom future changes to them.
The 28F320J5 and 28F640J5 may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placingyour product order.
Copies of documents which have an orderingnumber and are referenced in this document, or other Intel literature may be obtained by calling1-800-
548-4725 or by visitingIntel's website at http://www.intel.com.
Copyright Intel Corporation 19972002.
*Other names and brands may be claimed as the property of others.
Datasheet
3
28F320J5 and 28F640J5
Contents
1.0
Product Overview
.......................................................................................................7
2.0
Principles of Operation
..........................................................................................11
2.1
Data Protection.................................................................................................... 11
3.0
Bus Operation
............................................................................................................ 12
3.1
Read.................................................................................................................... 13
3.2
Output Disable.....................................................................................................13
3.3
Standby ...............................................................................................................13
3.4
Reset/Power-Down ............................................................................................. 13
3.5
Read Query ......................................................................................................... 14
3.6
Read Identifier Codes..........................................................................................14
3.7
Write .................................................................................................................... 16
4.0
Command Definitions
............................................................................................. 17
4.1
Read Array Command......................................................................................... 18
4.2
Read Query Mode Command ............................................................................. 18
4.2.1
Query Structure Output .......................................................................... 19
4.2.2
Query Structure Overview ...................................................................... 20
4.2.3
Block Status Register ............................................................................. 21
4.2.4
CFI Query Identification String............................................................... 21
4.2.5
System Interface Information ................................................................. 22
4.2.6
Device Geometry Definition....................................................................23
4.2.7
Primary-Vendor Specific Extended Query Table....................................23
4.3
Read Identifier Codes Command ........................................................................ 24
4.4
Read Status Register Command......................................................................... 25
4.5
Clear Status Register Command......................................................................... 25
4.6
Block Erase Command........................................................................................ 26
4.7
Block Erase Suspend Command ........................................................................ 26
4.8
Write to Buffer Command.................................................................................... 27
4.9
Byte/Word Program Commands ......................................................................... 27
4.10
Configuration Command ..................................................................................... 28
4.11
Set Block and Master Lock-Bit Commands......................................................... 28
4.12
Clear Block Lock-Bits Command......................................................................... 29
5.0
Design Considerations
..........................................................................................38
5.1
Three-Line Output Control................................................................................... 38
5.2
STS and Block Erase, Program, and Lock-Bit Configuration Polling .................. 38
5.3
Power Supply Decoupling................................................................................... 38
5.4
Input Signal Transitions Reducing Overshoots and Undershoots When Using
Buffers/Transceivers ...........................................................................................39
5.5
V
CC
, V
PEN
, RP# Transitions ................................................................................39
5.6
Power-Up/Down Protection ................................................................................. 39
5.7
Power Dissipation................................................................................................ 40
6.0
Electrical Specifications
........................................................................................ 40
6.1
Absolute Maximum Ratings................................................................................. 40
28F320J5 and 28F640J5
4
Datasheet
6.2
OperatingConditions .......................................................................................... 40
6.3
Capacitance ........................................................................................................ 41
6.4
DC Characteristics .............................................................................................. 41
6.5
AC Characteristics--Read-Only Operations ....................................................... 44
6.6
AC Characteristics-- Write Operations ............................................................... 46
6.7
Block Erase, Program, and Lock-Bit Configuration Performance ....................... 49
7.0
Ordering Information
.............................................................................................. 50
8.0
Additional Information
........................................................................................... 51
Datasheet
5
28F320J5 and 28F640J5
Revision History
Date of
Revision
Version
Description
09/01/97
-001
Original version
09/17/97
-002
Modifications made to cover sheet
12/01/97
-003
V
CC
/GND Pins Converted to No Connects Specification Change added
I
CCS
, I
CCD
, I
CCW
and I
CCE
Specification Change added
Order Codes Specification Change added
01/31/98
-004
The BGA* chip-scale package in Figure 2 was changed to a 52-ball package
and appropriate documentation added. The 64-Mb BGA package dimensions
were changed in Figure 2. Changed Figure 4 to read SSOP instead of TSOP.
03/23/98
-005
32-Mbit Intel StrataFlash memory read access time added. The number of
block erase cycles was changed. The write buffer program time was changed.
The operatingtemperature was changed. A read parameter was added. Sev-
eral program, erase, and lock-bit specifications were changed. Minor docu-
mentation changes were made as well. Datasheet designation changed from
Advance Information to Preliminary.
07/13/98
-006
Intel StrataFlash memory 32-Mbit BGA package removed. t
EHEL
read specifi-
cation reduced. Table 4 was modified. The Ordering Information was updated.
12/01/98
-007
Removed 32 Mbit, 100 ns references and orderinginformation for same. Pro-
vided clearer V
OH
specifications. Provided maximum program/erase specifica-
tion. Added Input Signal Transitions--Reducing Overshoots and Undershoots
When Using Buffers/Transceivers to Design Considerations section.
Name of document changed from Intel StrataFlashTM Memory Technology 32
and 64 Mbit.
05/04/99
-008
Updated CFI Tables, Section 4.2.1--Section 4.2.7.
09/16/99
-009
OperatingTemperature Range Specification was increased to 20 C to
+85 C. The 32-Mbit Read Access at +85 C was changed (Section 6.5, AC
Characteristics-Read Only Operations).
10/20/99
-010
Modified Write Pulse Width definition
Added lock-bit default status (Section 4.11)
Added order code information for 20 C to +85 C
11/08/99
-011
Modified Chip Enable Truth Table
12/16/99
-012
Corrected error in command table
Removed erase queuingoption from Figure 9, Block Erase Flowchart
06/26/00
-013
Add reference to 0.25 micron process on cover page
Corrected error in Table 10, Maximum buffer write time.
Updated section 6.7 program/erase times.
Corrected error in table 19 maximum temperature range
03/28/01
-014
Changed Clear Block-Lock Bit Time in Section 6.7.
04/23/02
-015
Added .25
micron ETOXVI process technology ordering information
Removed BGA CSP information
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